Maemo patchset 20101501+0m5

[h-e-n] / arch / arm / plat-omap / sram.c

diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index dcd9d16..a67ab51 100644 (file)
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -24,6 +24,7 @@
 
 #include <mach/sram.h>
 #include <mach/board.h>
+#include <mach/cpu.h>
 
 #include <mach/control.h>
 
@@ -37,12 +38,12 @@
 #define OMAP1_SRAM_VA          VMALLOC_END
 #define OMAP2_SRAM_PA          0x40200000
 #define OMAP2_SRAM_PUB_PA      0x4020f800
-#define OMAP2_SRAM_VA          VMALLOC_END
-#define OMAP2_SRAM_PUB_VA      (VMALLOC_END + 0x800)
+#define OMAP2_SRAM_VA          0xe3000000
+#define OMAP2_SRAM_PUB_VA      (OMAP2_SRAM_VA + 0x800)
 #define OMAP3_SRAM_PA           0x40200000
-#define OMAP3_SRAM_VA           0xd7000000
+#define OMAP3_SRAM_VA           0xe3000000
 #define OMAP3_SRAM_PUB_PA       0x40208000
-#define OMAP3_SRAM_PUB_VA       0xd7008000
+#define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
 
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 #define SRAM_BOOTLOADER_SZ     0x00
@@ -87,7 +88,7 @@ static int is_sram_locked(void)
        int type = 0;
 
        if (cpu_is_omap242x())
-               type = system_rev & OMAP2_DEVICETYPE_MASK;
+               type = omap_rev() & OMAP2_DEVICETYPE_MASK;
 
        if (type == GP_DEVICE) {
                /* RAMFW: R/W access to all initiators for all qualifier sets */
@@ -121,9 +122,15 @@ void __init omap_detect_sram(void)
        if (cpu_class_is_omap2()) {
                if (is_sram_locked()) {
                        if (cpu_is_omap34xx()) {
-                               omap_sram_base = OMAP3_SRAM_PUB_VA;
-                               omap_sram_start = OMAP3_SRAM_PUB_PA;
-                               omap_sram_size = 0x8000; /* 32K */
+                               if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
+                                       omap_sram_base = OMAP3_SRAM_PUB_VA;
+                                       omap_sram_start = OMAP3_SRAM_PUB_PA;
+                                       omap_sram_size = 0x8000; /* 32K */
+                               } else {
+                                       omap_sram_base = OMAP3_SRAM_PUB_VA;
+                                       omap_sram_start = OMAP3_SRAM_PUB_PA;
+                                       omap_sram_size = 0x7000; /* 28K */
+                               }
                        } else {
                                omap_sram_base = OMAP2_SRAM_PUB_VA;
                                omap_sram_start = OMAP2_SRAM_PUB_PA;
@@ -200,6 +207,15 @@ void __init omap_map_sram(void)
                base = OMAP3_SRAM_PA;
                base = ROUND_DOWN(base, PAGE_SIZE);
                omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
+
+               /*
+                * SRAM must be marked as non-cached on OMAP3 since the
+                * CORE DPLL M2 divider change code (in SRAM) runs with the
+                * SDRAM controller disabled, and if it is marked cached,
+                * the ARM may attempt to write cache lines back to SDRAM
+                * which will cause the system to hang.
+                */
+               omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
        }
 
        omap_sram_io_desc[0].length = 1024 * 1024;      /* Use section desc */
@@ -352,41 +368,46 @@ static inline int omap243x_sram_init(void)
 
 #ifdef CONFIG_ARCH_OMAP3
 
-static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
-                                             u32 sdrc_actim_ctrla,
-                                             u32 sdrc_actim_ctrlb,
-                                             u32 m2);
-u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
-                             u32 sdrc_actim_ctrlb, u32 m2)
+static u32 (*_omap3_sram_configure_core_dpll)(
+                               u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                               u32 sdrc_rfr_ctrl_0, u32 sdrc_mr_0,
+                               u32 sdrc_rfr_ctrl_1, u32 sdrc_mr_1);
+
+u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                             u32 sdrc_rfr_ctrl_0, u32 sdrc_mr_0,
+                             u32 sdrc_rfr_ctrl_1, u32 sdrc_mr_1)
 {
        if (!_omap3_sram_configure_core_dpll)
                omap_sram_error();
 
-       return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
-                                              sdrc_actim_ctrla,
-                                              sdrc_actim_ctrlb, m2);
+       return _omap3_sram_configure_core_dpll(
+                               m2, unlock_dll, f, inc,
+                               sdrc_rfr_ctrl_0, sdrc_mr_0,
+                               sdrc_rfr_ctrl_1, sdrc_mr_1);
 }
 
-/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
-void restore_sram_functions(void)
+#ifdef CONFIG_PM
+void omap3_sram_restore_context(void)
 {
        omap_sram_ceil = omap_sram_base + omap_sram_size;
 
        _omap3_sram_configure_core_dpll =
                omap_sram_push(omap3_sram_configure_core_dpll,
                               omap3_sram_configure_core_dpll_sz);
+       omap_push_sram_idle();
 }
+#endif /* CONFIG_PM */
 
-int __init omap34xx_sram_init(void)
+int __init omap3_sram_init(void)
 {
        _omap3_sram_configure_core_dpll =
                omap_sram_push(omap3_sram_configure_core_dpll,
                               omap3_sram_configure_core_dpll_sz);
-
+       omap_push_sram_idle();
        return 0;
 }
 #else
-static inline int omap34xx_sram_init(void)
+static inline int omap3_sram_init(void)
 {
        return 0;
 }
@@ -404,7 +425,7 @@ int __init omap_sram_init(void)
        else if (cpu_is_omap2430())
                omap243x_sram_init();
        else if (cpu_is_omap34xx())
-               omap34xx_sram_init();
+               omap3_sram_init();
 
        return 0;
 }