Fix MIPS SC

[qemu] / target-mips / translate.c

diff --git a/target-mips/translate.c b/target-mips/translate.c
index cf467f8..cc8b329 100644 (file)
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1174,13 +1174,13 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
 #if defined(TARGET_MIPS64)
     case OPC_SCD:
         save_cpu_state(ctx, 0);
-        op_ldst_scd(t0, t1, t0, ctx);
+        op_ldst_scd(t1, t0, rt, ctx);
         opn = "scd";
         break;
 #endif
     case OPC_SC:
         save_cpu_state(ctx, 0);
-        op_ldst_sc(t0, t1, t0, ctx);
+        op_ldst_sc(t1, t0, rt, ctx);
         opn = "sc";
         break;
     }