SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).

[qemu] / target-sh4 / helper.c

diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index f077462..c2cc432 100644 (file)
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -439,19 +439,7 @@ int get_physical_address(CPUState * env, target_ulong * physical,
        if (address >= 0x80000000 && address < 0xc0000000) {
            /* Mask upper 3 bits for P1 and P2 areas */
            *physical = address & 0x1fffffff;
-        } else if (address >= 0xfd000000 && address < 0xfe000000) {
-            /* PCI memory space */
-            *physical = address;
-       } else if (address >= 0xfc000000) {
-           /*
-            * Mask upper 3 bits for control registers in P4 area,
-            * to unify access to control registers via P0-P3 area.
-            * The addresses for cache store queue, TLB address array
-            * are not masked.
-            */
-       *physical = address & 0x1fffffff;
        } else {
-           /* access to cache store queue, or TLB address array. */
            *physical = address;
        }
        *prot = PAGE_READ | PAGE_WRITE;