VL_OBJS+= cirrus_vga.o parallel.o
VL_OBJS+= magic-load.o
else
-VL_OBJS+= sun4m.o tcx.o lance.o iommu.o m48t08.o magic-load.o slavio_intctl.o slavio_timer.o slavio_serial.o slavio_misc.o fdc.o esp.o
+VL_OBJS+= sun4m.o tcx.o lance.o iommu.o m48t59.o magic-load.o slavio_intctl.o
+VL_OBJS+= slavio_timer.o slavio_serial.o slavio_misc.o fdc.o esp.o
endif
endif
ifdef CONFIG_GDBSTUB
+++ /dev/null
-/*
- * QEMU M48T08 NVRAM emulation for Sparc platform
- *
- * Copyright (c) 2003-2004 Jocelyn Mayer
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-#include "vl.h"
-#include "m48t08.h"
-
-//#define DEBUG_NVRAM
-
-#if defined(DEBUG_NVRAM)
-#define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
-#else
-#define NVRAM_PRINTF(fmt, args...) do { } while (0)
-#endif
-
-#define NVRAM_MAX_MEM 0x1ff0
-#define NVRAM_MAXADDR 0x1fff
-
-struct m48t08_t {
- /* RTC management */
- time_t time_offset;
- time_t stop_time;
- /* NVRAM storage */
- uint8_t *buffer;
-};
-
-/* Fake timer functions */
-/* Generic helpers for BCD */
-static inline uint8_t toBCD (uint8_t value)
-{
- return (((value / 10) % 10) << 4) | (value % 10);
-}
-
-static inline uint8_t fromBCD (uint8_t BCD)
-{
- return ((BCD >> 4) * 10) + (BCD & 0x0F);
-}
-
-/* RTC management helpers */
-static void get_time (m48t08_t *NVRAM, struct tm *tm)
-{
- time_t t;
-
- t = time(NULL) + NVRAM->time_offset;
-#ifdef _WIN32
- memcpy(tm,localtime(&t),sizeof(*tm));
-#else
- localtime_r (&t, tm) ;
-#endif
-}
-
-static void set_time (m48t08_t *NVRAM, struct tm *tm)
-{
- time_t now, new_time;
-
- new_time = mktime(tm);
- now = time(NULL);
- NVRAM->time_offset = new_time - now;
-}
-
-/* Direct access to NVRAM */
-void m48t08_write (m48t08_t *NVRAM, uint32_t addr, uint8_t val)
-{
- struct tm tm;
- int tmp;
-
- addr &= NVRAM_MAXADDR;
- switch (addr) {
- case 0x1FF8:
- /* control */
- NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90;
- break;
- case 0x1FF9:
- /* seconds (BCD) */
- tmp = fromBCD(val & 0x7F);
- if (tmp >= 0 && tmp <= 59) {
- get_time(NVRAM, &tm);
- tm.tm_sec = tmp;
- set_time(NVRAM, &tm);
- }
- if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) {
- if (val & 0x80) {
- NVRAM->stop_time = time(NULL);
- } else {
- NVRAM->time_offset += NVRAM->stop_time - time(NULL);
- NVRAM->stop_time = 0;
- }
- }
- NVRAM->buffer[0x1FF9] = val & 0x80;
- break;
- case 0x1FFA:
- /* minutes (BCD) */
- tmp = fromBCD(val & 0x7F);
- if (tmp >= 0 && tmp <= 59) {
- get_time(NVRAM, &tm);
- tm.tm_min = tmp;
- set_time(NVRAM, &tm);
- }
- break;
- case 0x1FFB:
- /* hours (BCD) */
- tmp = fromBCD(val & 0x3F);
- if (tmp >= 0 && tmp <= 23) {
- get_time(NVRAM, &tm);
- tm.tm_hour = tmp;
- set_time(NVRAM, &tm);
- }
- break;
- case 0x1FFC:
- /* day of the week / century */
- tmp = fromBCD(val & 0x07);
- get_time(NVRAM, &tm);
- tm.tm_wday = tmp;
- set_time(NVRAM, &tm);
- NVRAM->buffer[0x1FFC] = val & 0x40;
- break;
- case 0x1FFD:
- /* date */
- tmp = fromBCD(val & 0x1F);
- if (tmp != 0) {
- get_time(NVRAM, &tm);
- tm.tm_mday = tmp;
- set_time(NVRAM, &tm);
- }
- break;
- case 0x1FFE:
- /* month */
- tmp = fromBCD(val & 0x1F);
- if (tmp >= 1 && tmp <= 12) {
- get_time(NVRAM, &tm);
- tm.tm_mon = tmp - 1;
- set_time(NVRAM, &tm);
- }
- break;
- case 0x1FFF:
- /* year */
- tmp = fromBCD(val);
- if (tmp >= 0 && tmp <= 99) {
- get_time(NVRAM, &tm);
- tm.tm_year = fromBCD(val);
- set_time(NVRAM, &tm);
- }
- break;
- default:
- NVRAM->buffer[addr] = val & 0xFF;
- break;
- }
-}
-
-uint8_t m48t08_read (m48t08_t *NVRAM, uint32_t addr)
-{
- struct tm tm;
- uint8_t retval = 0xFF;
-
- addr &= NVRAM_MAXADDR;
- switch (addr) {
- case 0x1FF8:
- /* control */
- goto do_read;
- case 0x1FF9:
- /* seconds (BCD) */
- get_time(NVRAM, &tm);
- retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec);
- break;
- case 0x1FFA:
- /* minutes (BCD) */
- get_time(NVRAM, &tm);
- retval = toBCD(tm.tm_min);
- break;
- case 0x1FFB:
- /* hours (BCD) */
- get_time(NVRAM, &tm);
- retval = toBCD(tm.tm_hour);
- break;
- case 0x1FFC:
- /* day of the week / century */
- get_time(NVRAM, &tm);
- retval = NVRAM->buffer[0x1FFC] | tm.tm_wday;
- break;
- case 0x1FFD:
- /* date */
- get_time(NVRAM, &tm);
- retval = toBCD(tm.tm_mday);
- break;
- case 0x1FFE:
- /* month */
- get_time(NVRAM, &tm);
- retval = toBCD(tm.tm_mon + 1);
- break;
- case 0x1FFF:
- /* year */
- get_time(NVRAM, &tm);
- retval = toBCD(tm.tm_year);
- break;
- default:
- do_read:
- retval = NVRAM->buffer[addr];
- break;
- }
- return retval;
-}
-
-static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
-{
- m48t08_t *NVRAM = opaque;
-
- m48t08_write(NVRAM, addr, value);
-}
-
-static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
-{
- m48t08_t *NVRAM = opaque;
-
- m48t08_write(NVRAM, addr, value);
- m48t08_write(NVRAM, addr + 1, value >> 8);
-}
-
-static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
-{
- m48t08_t *NVRAM = opaque;
-
- m48t08_write(NVRAM, addr, value);
- m48t08_write(NVRAM, addr + 1, value >> 8);
- m48t08_write(NVRAM, addr + 2, value >> 16);
- m48t08_write(NVRAM, addr + 3, value >> 24);
-}
-
-static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
-{
- m48t08_t *NVRAM = opaque;
- uint32_t retval = 0;
-
- retval = m48t08_read(NVRAM, addr);
- return retval;
-}
-
-static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
-{
- m48t08_t *NVRAM = opaque;
- uint32_t retval = 0;
-
- retval = m48t08_read(NVRAM, addr) << 8;
- retval |= m48t08_read(NVRAM, addr + 1);
- return retval;
-}
-
-static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
-{
- m48t08_t *NVRAM = opaque;
- uint32_t retval = 0;
-
- retval = m48t08_read(NVRAM, addr) << 24;
- retval |= m48t08_read(NVRAM, addr + 1) << 16;
- retval |= m48t08_read(NVRAM, addr + 2) << 8;
- retval |= m48t08_read(NVRAM, addr + 3);
- return retval;
-}
-
-static CPUWriteMemoryFunc *nvram_write[] = {
- &nvram_writeb,
- &nvram_writew,
- &nvram_writel,
-};
-
-static CPUReadMemoryFunc *nvram_read[] = {
- &nvram_readb,
- &nvram_readw,
- &nvram_readl,
-};
-
-static void nvram_save(QEMUFile *f, void *opaque)
-{
- m48t08_t *s = opaque;
-
- qemu_put_be32s(f, (uint32_t *)&s->time_offset);
- qemu_put_be32s(f, (uint32_t *)&s->stop_time);
- qemu_put_buffer(f, s->buffer, 0x2000);
-}
-
-static int nvram_load(QEMUFile *f, void *opaque, int version_id)
-{
- m48t08_t *s = opaque;
-
- if (version_id != 1)
- return -EINVAL;
-
- qemu_get_be32s(f, (uint32_t *)&s->time_offset);
- qemu_get_be32s(f, (uint32_t *)&s->stop_time);
- qemu_get_buffer(f, s->buffer, 0x2000);
- return 0;
-}
-
-static void m48t08_reset(void *opaque)
-{
- m48t08_t *s = opaque;
-
- s->time_offset = 0;
- s->stop_time = 0;
-}
-
-
-/* Initialisation routine */
-m48t08_t *m48t08_init(uint32_t mem_base, uint16_t size)
-{
- m48t08_t *s;
- int mem_index;
-
- s = qemu_mallocz(sizeof(m48t08_t));
- if (!s)
- return NULL;
- s->buffer = qemu_mallocz(size);
- if (!s->buffer) {
- qemu_free(s);
- return NULL;
- }
- if (mem_base != 0) {
- mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
- cpu_register_physical_memory(mem_base, 0x2000, mem_index);
- }
-
- register_savevm("nvram", mem_base, 1, nvram_save, nvram_load, s);
- qemu_register_reset(m48t08_reset, s);
- return s;
-}
-
-#if 0
-struct idprom
-{
- unsigned char id_format; /* Format identifier (always 0x01) */
- unsigned char id_machtype; /* Machine type */
- unsigned char id_ethaddr[6]; /* Hardware ethernet address */
- long id_date; /* Date of manufacture */
- unsigned int id_sernum:24; /* Unique serial number */
- unsigned char id_cksum; /* Checksum - xor of the data bytes */
- unsigned char reserved[16];
-};
-#endif
+++ /dev/null
-#if !defined (__M48T08_H__)
-#define __M48T08_H__
-
-typedef struct m48t08_t m48t08_t;
-
-void m48t08_write (m48t08_t *NVRAM, uint32_t addr, uint8_t val);
-uint8_t m48t08_read (m48t08_t *NVRAM, uint32_t addr);
-m48t08_t *m48t08_init(uint32_t mem_base, uint16_t size);
-
-#endif /* !defined (__M48T08_H__) */
/*
- * QEMU M48T59 NVRAM emulation for PPC PREP platform
+ * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
*
- * Copyright (c) 2003-2004 Jocelyn Mayer
+ * Copyright (c) 2003-2005 Jocelyn Mayer
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
#define NVRAM_PRINTF(fmt, args...) do { } while (0)
#endif
+/*
+ * The M48T08 and M48T59 chips are very similar. The newer '59 has
+ * alarm and a watchdog timer and related control registers. In the
+ * PPC platform there is also a nvram lock function.
+ */
struct m48t59_t {
+ /* Model parameters */
+ int type; // 8 = m48t08, 59 = m48t59
/* Hardware parameters */
int IRQ;
int mem_index;
}
/* Direct access to NVRAM */
-void m48t59_write (m48t59_t *NVRAM, uint32_t val)
+void m48t59_write (m48t59_t *NVRAM, uint32_t addr, uint32_t val)
{
struct tm tm;
int tmp;
- if (NVRAM->addr > 0x1FF8 && NVRAM->addr < 0x2000)
- NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, NVRAM->addr, val);
- switch (NVRAM->addr) {
+ if (addr > 0x1FF8 && addr < 0x2000)
+ NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
+ if (NVRAM->type == 8 &&
+ (addr >= 0x1ff0 && addr <= 0x1ff7))
+ goto do_write;
+ switch (addr) {
case 0x1FF0:
/* flags register : read-only */
break;
break;
case 0x1FF2:
/* alarm seconds */
- tmp = fromBCD(val & 0x7F);
- if (tmp >= 0 && tmp <= 59) {
- get_alarm(NVRAM, &tm);
- tm.tm_sec = tmp;
- NVRAM->buffer[0x1FF2] = val;
- set_alarm(NVRAM, &tm);
- }
+ tmp = fromBCD(val & 0x7F);
+ if (tmp >= 0 && tmp <= 59) {
+ get_alarm(NVRAM, &tm);
+ tm.tm_sec = tmp;
+ NVRAM->buffer[0x1FF2] = val;
+ set_alarm(NVRAM, &tm);
+ }
break;
case 0x1FF3:
/* alarm minutes */
- tmp = fromBCD(val & 0x7F);
- if (tmp >= 0 && tmp <= 59) {
- get_alarm(NVRAM, &tm);
- tm.tm_min = tmp;
- NVRAM->buffer[0x1FF3] = val;
- set_alarm(NVRAM, &tm);
- }
+ tmp = fromBCD(val & 0x7F);
+ if (tmp >= 0 && tmp <= 59) {
+ get_alarm(NVRAM, &tm);
+ tm.tm_min = tmp;
+ NVRAM->buffer[0x1FF3] = val;
+ set_alarm(NVRAM, &tm);
+ }
break;
case 0x1FF4:
/* alarm hours */
- tmp = fromBCD(val & 0x3F);
- if (tmp >= 0 && tmp <= 23) {
- get_alarm(NVRAM, &tm);
- tm.tm_hour = tmp;
- NVRAM->buffer[0x1FF4] = val;
- set_alarm(NVRAM, &tm);
- }
+ tmp = fromBCD(val & 0x3F);
+ if (tmp >= 0 && tmp <= 23) {
+ get_alarm(NVRAM, &tm);
+ tm.tm_hour = tmp;
+ NVRAM->buffer[0x1FF4] = val;
+ set_alarm(NVRAM, &tm);
+ }
break;
case 0x1FF5:
/* alarm date */
- tmp = fromBCD(val & 0x1F);
- if (tmp != 0) {
- get_alarm(NVRAM, &tm);
- tm.tm_mday = tmp;
- NVRAM->buffer[0x1FF5] = val;
- set_alarm(NVRAM, &tm);
- }
+ tmp = fromBCD(val & 0x1F);
+ if (tmp != 0) {
+ get_alarm(NVRAM, &tm);
+ tm.tm_mday = tmp;
+ NVRAM->buffer[0x1FF5] = val;
+ set_alarm(NVRAM, &tm);
+ }
break;
case 0x1FF6:
/* interrupts */
- NVRAM->buffer[0x1FF6] = val;
+ NVRAM->buffer[0x1FF6] = val;
break;
case 0x1FF7:
/* watchdog */
- NVRAM->buffer[0x1FF7] = val;
- set_up_watchdog(NVRAM, val);
+ NVRAM->buffer[0x1FF7] = val;
+ set_up_watchdog(NVRAM, val);
break;
case 0x1FF8:
/* control */
break;
default:
/* Check lock registers state */
- if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1))
+ if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
break;
- if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2))
+ if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
break;
- if (NVRAM->addr < 0x1FF0 ||
- (NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
- NVRAM->buffer[NVRAM->addr] = val & 0xFF;
+ do_write:
+ if (addr < NVRAM->size) {
+ NVRAM->buffer[addr] = val & 0xFF;
}
break;
}
}
-uint32_t m48t59_read (m48t59_t *NVRAM)
+uint32_t m48t59_read (m48t59_t *NVRAM, uint32_t addr)
{
struct tm tm;
uint32_t retval = 0xFF;
- switch (NVRAM->addr) {
+ if (NVRAM->type == 8 &&
+ (addr >= 0x1ff0 && addr <= 0x1ff7))
+ goto do_read;
+ switch (addr) {
case 0x1FF0:
/* flags register */
goto do_read;
break;
default:
/* Check lock registers state */
- if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1))
+ if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
break;
- if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2))
+ if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
break;
- if (NVRAM->addr < 0x1FF0 ||
- (NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
- do_read:
- retval = NVRAM->buffer[NVRAM->addr];
+ do_read:
+ if (addr < NVRAM->size) {
+ retval = NVRAM->buffer[addr];
}
break;
}
- if (NVRAM->addr > 0x1FF9 && NVRAM->addr < 0x2000)
- NVRAM_PRINTF("0x%08x <= 0x%08x\n", NVRAM->addr, retval);
+ if (addr > 0x1FF9 && addr < 0x2000)
+ NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr, retval);
return retval;
}
NVRAM->addr |= val << 8;
break;
case 3:
- m48t59_write(NVRAM, val);
+ m48t59_write(NVRAM, val, NVRAM->addr);
NVRAM->addr = 0x0000;
break;
default:
addr -= NVRAM->io_base;
switch (addr) {
case 3:
- retval = m48t59_read(NVRAM);
+ retval = m48t59_read(NVRAM, NVRAM->addr);
break;
default:
retval = -1;
m48t59_t *NVRAM = opaque;
addr -= NVRAM->mem_base;
- if (addr < 0x1FF0)
- NVRAM->buffer[addr] = value;
+ m48t59_write(NVRAM, addr, value & 0xff);
}
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
m48t59_t *NVRAM = opaque;
addr -= NVRAM->mem_base;
- if (addr < 0x1FF0) {
- NVRAM->buffer[addr] = value >> 8;
- NVRAM->buffer[addr + 1] = value;
- }
+ m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
+ m48t59_write(NVRAM, addr + 1, value & 0xff);
}
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
m48t59_t *NVRAM = opaque;
addr -= NVRAM->mem_base;
- if (addr < 0x1FF0) {
- NVRAM->buffer[addr] = value >> 24;
- NVRAM->buffer[addr + 1] = value >> 16;
- NVRAM->buffer[addr + 2] = value >> 8;
- NVRAM->buffer[addr + 3] = value;
- }
+ m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
+ m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
+ m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
+ m48t59_write(NVRAM, addr + 3, value & 0xff);
}
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
{
m48t59_t *NVRAM = opaque;
- uint32_t retval = 0;
+ uint32_t retval;
addr -= NVRAM->mem_base;
- if (addr < 0x1FF0)
- retval = NVRAM->buffer[addr];
-
+ retval = m48t59_read(NVRAM, addr);
return retval;
}
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
{
m48t59_t *NVRAM = opaque;
- uint32_t retval = 0;
+ uint32_t retval;
addr -= NVRAM->mem_base;
- if (addr < 0x1FF0) {
- retval = NVRAM->buffer[addr] << 8;
- retval |= NVRAM->buffer[addr + 1];
- }
-
+ retval = m48t59_read(NVRAM, addr) << 8;
+ retval |= m48t59_read(NVRAM, addr + 1);
return retval;
}
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
{
m48t59_t *NVRAM = opaque;
- uint32_t retval = 0;
-
- addr -= NVRAM->mem_base;
- if (addr < 0x1FF0) {
- retval = NVRAM->buffer[addr] << 24;
- retval |= NVRAM->buffer[addr + 1] << 16;
- retval |= NVRAM->buffer[addr + 2] << 8;
- retval |= NVRAM->buffer[addr + 3];
- }
+ uint32_t retval;
+ addr -= NVRAM->mem_base;
+ retval = m48t59_read(NVRAM, addr) << 24;
+ retval |= m48t59_read(NVRAM, addr + 1) << 16;
+ retval |= m48t59_read(NVRAM, addr + 2) << 8;
+ retval |= m48t59_read(NVRAM, addr + 3);
return retval;
}
&nvram_readw,
&nvram_readl,
};
+
/* Initialisation routine */
-m48t59_t *m48t59_init (int IRQ, uint32_t mem_base,
- uint32_t io_base, uint16_t size)
+m48t59_t *m48t59_init (int IRQ, target_ulong mem_base,
+ uint32_t io_base, uint16_t size,
+ int type)
{
m48t59_t *s;
s->mem_base = mem_base;
s->io_base = io_base;
s->addr = 0;
- register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
- register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
+ s->type = type;
+ if (io_base != 0) {
+ register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
+ register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
+ }
if (mem_base != 0) {
s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
cpu_register_physical_memory(mem_base, 0x4000, s->mem_index);
}
- s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
- s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
+ if (type == 59) {
+ s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
+ s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
+ }
s->lock = 0;
return s;
typedef struct m48t59_t m48t59_t;
-void m48t59_write (m48t59_t *NVRAM, uint32_t val);
-uint32_t m48t59_read (m48t59_t *NVRAM);
-void m48t59_set_addr (m48t59_t *NVRAM, uint32_t addr);
+void m48t59_write (m48t59_t *NVRAM, uint32_t addr, uint32_t val);
+uint32_t m48t59_read (m48t59_t *NVRAM, uint32_t addr);
void m48t59_toggle_lock (m48t59_t *NVRAM, int lock);
-m48t59_t *m48t59_init (int IRQ, uint32_t io_base,
- uint32_t mem_base, uint16_t size);
+m48t59_t *m48t59_init (int IRQ, target_ulong mem_base,
+ uint32_t io_base, uint16_t size,
+ int type);
#endif /* !defined (__M48T59_H__) */
/* NVRAM helpers */
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
{
- m48t59_set_addr(nvram, addr);
- m48t59_write(nvram, value);
+ m48t59_write(nvram, addr, value);
}
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
{
- m48t59_set_addr(nvram, addr);
- return m48t59_read(nvram);
+ return m48t59_read(nvram, addr);
}
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
{
- m48t59_set_addr(nvram, addr);
- m48t59_write(nvram, value >> 8);
- m48t59_set_addr(nvram, addr + 1);
- m48t59_write(nvram, value & 0xFF);
+ m48t59_write(nvram, addr, value >> 8);
+ m48t59_write(nvram, addr + 1, value & 0xFF);
}
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
{
uint16_t tmp;
- m48t59_set_addr(nvram, addr);
- tmp = m48t59_read(nvram) << 8;
- m48t59_set_addr(nvram, addr + 1);
- tmp |= m48t59_read(nvram);
-
+ tmp = m48t59_read(nvram, addr) << 8;
+ tmp |= m48t59_read(nvram, addr + 1);
return tmp;
}
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
{
- m48t59_set_addr(nvram, addr);
- m48t59_write(nvram, value >> 24);
- m48t59_set_addr(nvram, addr + 1);
- m48t59_write(nvram, (value >> 16) & 0xFF);
- m48t59_set_addr(nvram, addr + 2);
- m48t59_write(nvram, (value >> 8) & 0xFF);
- m48t59_set_addr(nvram, addr + 3);
- m48t59_write(nvram, value & 0xFF);
+ m48t59_write(nvram, addr, value >> 24);
+ m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
+ m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
+ m48t59_write(nvram, addr + 3, value & 0xFF);
}
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
{
uint32_t tmp;
- m48t59_set_addr(nvram, addr);
- tmp = m48t59_read(nvram) << 24;
- m48t59_set_addr(nvram, addr + 1);
- tmp |= m48t59_read(nvram) << 16;
- m48t59_set_addr(nvram, addr + 2);
- tmp |= m48t59_read(nvram) << 8;
- m48t59_set_addr(nvram, addr + 3);
- tmp |= m48t59_read(nvram);
-
+ tmp = m48t59_read(nvram, addr) << 24;
+ tmp |= m48t59_read(nvram, addr + 1) << 16;
+ tmp |= m48t59_read(nvram, addr + 2) << 8;
+ tmp |= m48t59_read(nvram, addr + 3);
return tmp;
}
int i;
for (i = 0; i < max && str[i] != '\0'; i++) {
- m48t59_set_addr(nvram, addr + i);
- m48t59_write(nvram, str[i]);
+ m48t59_write(nvram, addr + i, str[i]);
}
- m48t59_set_addr(nvram, addr + max - 1);
- m48t59_write(nvram, '\0');
+ m48t59_write(nvram, addr + max - 1, '\0');
}
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
macio_init(pci_bus, 0x0017);
- nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
+ nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
arch_name = "HEATHROW";
} else {
macio_init(pci_bus, 0x0022);
- nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
+ nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
arch_name = "MAC99";
}
cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
#endif
- nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE);
+ nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE, 59);
if (nvram == NULL)
return;
sysctrl->nvram = nvram;
* THE SOFTWARE.
*/
#include "vl.h"
-#include "m48t08.h"
#define KERNEL_LOAD_ADDR 0x00004000
#define CMDLINE_ADDR 0x007ff000
{
}
-static void nvram_set_word (m48t08_t *nvram, uint32_t addr, uint16_t value)
+static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
{
- m48t08_write(nvram, addr++, (value >> 8) & 0xff);
- m48t08_write(nvram, addr++, value & 0xff);
+ m48t59_write(nvram, addr++, (value >> 8) & 0xff);
+ m48t59_write(nvram, addr++, value & 0xff);
}
-static void nvram_set_lword (m48t08_t *nvram, uint32_t addr, uint32_t value)
+static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
{
- m48t08_write(nvram, addr++, value >> 24);
- m48t08_write(nvram, addr++, (value >> 16) & 0xff);
- m48t08_write(nvram, addr++, (value >> 8) & 0xff);
- m48t08_write(nvram, addr++, value & 0xff);
+ m48t59_write(nvram, addr++, value >> 24);
+ m48t59_write(nvram, addr++, (value >> 16) & 0xff);
+ m48t59_write(nvram, addr++, (value >> 8) & 0xff);
+ m48t59_write(nvram, addr++, value & 0xff);
}
-static void nvram_set_string (m48t08_t *nvram, uint32_t addr,
+static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
const unsigned char *str, uint32_t max)
{
unsigned int i;
for (i = 0; i < max && str[i] != '\0'; i++) {
- m48t08_write(nvram, addr + i, str[i]);
+ m48t59_write(nvram, addr + i, str[i]);
}
- m48t08_write(nvram, addr + max - 1, '\0');
+ m48t59_write(nvram, addr + max - 1, '\0');
}
-static m48t08_t *nvram;
+static m48t59_t *nvram;
extern int nographic;
-static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline,
+static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
int boot_device, uint32_t RAM_size,
uint32_t kernel_size,
int width, int height, int depth)
nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */
// NVRAM_size, arch not applicable
- m48t08_write(nvram, 0x2F, nographic & 0xff);
+ m48t59_write(nvram, 0x2F, nographic & 0xff);
nvram_set_lword(nvram, 0x30, RAM_size);
- m48t08_write(nvram, 0x34, boot_device & 0xff);
+ m48t59_write(nvram, 0x34, boot_device & 0xff);
nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
nvram_set_lword(nvram, 0x3C, kernel_size);
if (cmdline) {
// Sun4m specific use
i = 0x1fd8;
- m48t08_write(nvram, i++, 0x01);
- m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */
+ m48t59_write(nvram, i++, 0x01);
+ m48t59_write(nvram, i++, 0x80); /* Sun4m OBP */
j = 0;
- m48t08_write(nvram, i++, macaddr[j++]);
- m48t08_write(nvram, i++, macaddr[j++]);
- m48t08_write(nvram, i++, macaddr[j++]);
- m48t08_write(nvram, i++, macaddr[j++]);
- m48t08_write(nvram, i++, macaddr[j++]);
- m48t08_write(nvram, i, macaddr[j]);
+ m48t59_write(nvram, i++, macaddr[j++]);
+ m48t59_write(nvram, i++, macaddr[j++]);
+ m48t59_write(nvram, i++, macaddr[j++]);
+ m48t59_write(nvram, i++, macaddr[j++]);
+ m48t59_write(nvram, i++, macaddr[j++]);
+ m48t59_write(nvram, i, macaddr[j]);
/* Calculate checksum */
for (i = 0x1fd8; i < 0x1fe7; i++) {
- tmp ^= m48t08_read(nvram, i);
+ tmp ^= m48t59_read(nvram, i);
}
- m48t08_write(nvram, 0x1fe7, tmp);
+ m48t59_write(nvram, 0x1fe7, tmp);
}
static void *slavio_intctl;
slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height);
lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
- nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE);
+ nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8);
slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ);
slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ);
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
/* NVRAM helpers */
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
{
- m48t59_set_addr(nvram, addr);
- m48t59_write(nvram, value);
+ m48t59_write(nvram, addr, value);
}
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
{
- m48t59_set_addr(nvram, addr);
- return m48t59_read(nvram);
+ return m48t59_read(nvram, addr);
}
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
{
- m48t59_set_addr(nvram, addr);
- m48t59_write(nvram, value >> 8);
- m48t59_set_addr(nvram, addr + 1);
- m48t59_write(nvram, value & 0xFF);
+ m48t59_write(nvram, addr, value >> 8);
+ m48t59_write(nvram, addr + 1, value & 0xFF);
}
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
{
uint16_t tmp;
- m48t59_set_addr(nvram, addr);
- tmp = m48t59_read(nvram) << 8;
- m48t59_set_addr(nvram, addr + 1);
- tmp |= m48t59_read(nvram);
+ tmp = m48t59_read(nvram, addr) << 8;
+ tmp |= m48t59_read(nvram, addr + 1);
return tmp;
}
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
{
- m48t59_set_addr(nvram, addr);
- m48t59_write(nvram, value >> 24);
- m48t59_set_addr(nvram, addr + 1);
- m48t59_write(nvram, (value >> 16) & 0xFF);
- m48t59_set_addr(nvram, addr + 2);
- m48t59_write(nvram, (value >> 8) & 0xFF);
- m48t59_set_addr(nvram, addr + 3);
- m48t59_write(nvram, value & 0xFF);
+ m48t59_write(nvram, addr, value >> 24);
+ m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
+ m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
+ m48t59_write(nvram, addr + 3, value & 0xFF);
}
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
{
uint32_t tmp;
- m48t59_set_addr(nvram, addr);
- tmp = m48t59_read(nvram) << 24;
- m48t59_set_addr(nvram, addr + 1);
- tmp |= m48t59_read(nvram) << 16;
- m48t59_set_addr(nvram, addr + 2);
- tmp |= m48t59_read(nvram) << 8;
- m48t59_set_addr(nvram, addr + 3);
- tmp |= m48t59_read(nvram);
+ tmp = m48t59_read(nvram, addr) << 24;
+ tmp |= m48t59_read(nvram, addr + 1) << 16;
+ tmp |= m48t59_read(nvram, addr + 2) << 8;
+ tmp |= m48t59_read(nvram, addr + 3);
return tmp;
}
int i;
for (i = 0; i < max && str[i] != '\0'; i++) {
- m48t59_set_addr(nvram, addr + i);
- m48t59_write(nvram, str[i]);
+ m48t59_write(nvram, addr + i, str[i]);
}
- m48t59_set_addr(nvram, addr + max - 1);
- m48t59_write(nvram, '\0');
+ m48t59_write(nvram, addr + max - 1, '\0');
}
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
pci_cmd646_ide_init(pci_bus, bs_table, 1);
kbd_init();
floppy_controller = fdctrl_init(6, 2, 0, 0x3f0, fd_table);
- nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE);
+ nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE, 59);
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device,
KERNEL_LOAD_ADDR, kernel_size,
kernel_cmdline,
projects / qemu / commitdiff