* This code is licenced under the GPL.
*/
-#include "hw.h"
+#include "sysbus.h"
#include "pxa.h"
#include "sysemu.h"
#include "pc.h"
#include "i2c.h"
+#include "ssi.h"
#include "qemu-timer.h"
#include "qemu-char.h"
static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case PMCR ... PCMD31:
static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case PMCR:
static void pxa2xx_pm_save(QEMUFile *f, void *opaque)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
int i;
for (i = 0; i < 0x40; i ++)
static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
int i;
for (i = 0; i < 0x40; i ++)
static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case CCCR:
static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case CCCR:
static void pxa2xx_cm_save(QEMUFile *f, void *opaque)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
int i;
for (i = 0; i < 4; i ++)
static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
int i;
for (i = 0; i < 4; i ++)
static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
switch (reg) {
case 6: /* Clock Configuration register */
static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
uint32_t value)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
static const char *pwrmode[8] = {
"Normal", "Idle", "Deep-idle", "Standby",
"Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
switch (reg) {
case CPPMNC:
static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
uint32_t value)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
switch (reg) {
case CPPMNC:
static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case MDCNFG ... SA1110:
static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case MDCNFG ... SA1110:
static void pxa2xx_mm_save(QEMUFile *f, void *opaque)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
int i;
for (i = 0; i < 0x1a; i ++)
static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
int i;
for (i = 0; i < 0x1a; i ++)
}
/* Synchronous Serial Ports */
-struct pxa2xx_ssp_s {
+typedef struct {
+ SysBusDevice busdev;
qemu_irq irq;
int enable;
+ SSIBus *bus;
uint32_t sscr[2];
uint32_t sspsp;
uint32_t rx_fifo[16];
int rx_level;
int rx_start;
-
- uint32_t (*readfn)(void *opaque);
- void (*writefn)(void *opaque, uint32_t value);
- void *opaque;
-};
+} PXA2xxSSPState;
#define SSCR0 0x00 /* SSP Control register 0 */
#define SSCR1 0x04 /* SSP Control register 1 */
#define SSSR_BCE (1 << 23)
#define SSSR_RW 0x00bc0080
-static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s *s)
+static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
{
int level = 0;
qemu_set_irq(s->irq, !!level);
}
-static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s *s)
+static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
{
s->sssr &= ~(0xf << 12); /* Clear RFL */
s->sssr &= ~(0xf << 8); /* Clear TFL */
static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
{
- struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
+ PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
uint32_t retval;
switch (addr) {
static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
+ PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
switch (addr) {
case SSCR0:
* there directly to the slave, no need to buffer it.
*/
if (s->enable) {
- if (s->writefn)
- s->writefn(s->opaque, value);
-
+ uint32_t readval;
+ readval = ssi_transfer(s->bus, value);
if (s->rx_level < 0x10) {
- if (s->readfn)
- s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] =
- s->readfn(s->opaque);
- else
- s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = 0x0;
- } else
+ s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
+ } else {
s->sssr |= SSSR_ROR;
+ }
}
pxa2xx_ssp_fifo_update(s);
break;
}
}
-void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
- uint32_t (*readfn)(void *opaque),
- void (*writefn)(void *opaque, uint32_t value), void *opaque)
-{
- if (!port) {
- printf("%s: no such SSP\n", __FUNCTION__);
- exit(-1);
- }
-
- port->opaque = opaque;
- port->readfn = readfn;
- port->writefn = writefn;
-}
-
static CPUReadMemoryFunc *pxa2xx_ssp_readfn[] = {
pxa2xx_ssp_read,
pxa2xx_ssp_read,
static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
{
- struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
+ PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
int i;
qemu_put_be32(f, s->enable);
static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
{
- struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
+ PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
int i;
s->enable = qemu_get_be32(f);
return 0;
}
+static void pxa2xx_ssp_init(SysBusDevice *dev)
+{
+ int iomemtype;
+ PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev);
+
+ sysbus_init_irq(dev, &s->irq);
+
+ iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
+ pxa2xx_ssp_writefn, s);
+ sysbus_init_mmio(dev, 0x1000, iomemtype);
+ register_savevm("pxa2xx_ssp", -1, 0,
+ pxa2xx_ssp_save, pxa2xx_ssp_load, s);
+
+ s->bus = ssi_create_bus(&dev->qdev, "ssi");
+}
+
/* Real-Time Clock */
#define RCNR 0x00 /* RTC Counter register */
#define RTAR 0x04 /* RTC Alarm register */
#define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
#define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
-static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s *s)
+static inline void pxa2xx_rtc_int_update(PXA2xxState *s)
{
qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
}
-static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s *s)
+static void pxa2xx_rtc_hzupdate(PXA2xxState *s)
{
int64_t rt = qemu_get_clock(rt_clock);
s->last_rcnr += ((rt - s->last_hz) << 15) /
s->last_hz = rt;
}
-static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s *s)
+static void pxa2xx_rtc_swupdate(PXA2xxState *s)
{
int64_t rt = qemu_get_clock(rt_clock);
if (s->rtsr & (1 << 12))
s->last_sw = rt;
}
-static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s *s)
+static void pxa2xx_rtc_piupdate(PXA2xxState *s)
{
int64_t rt = qemu_get_clock(rt_clock);
if (s->rtsr & (1 << 15))
s->last_pi = rt;
}
-static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s *s,
+static inline void pxa2xx_rtc_alarm_update(PXA2xxState *s,
uint32_t rtsr)
{
if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
static inline void pxa2xx_rtc_hz_tick(void *opaque)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
s->rtsr |= (1 << 0);
pxa2xx_rtc_alarm_update(s, s->rtsr);
pxa2xx_rtc_int_update(s);
static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
s->rtsr |= (1 << 4);
pxa2xx_rtc_alarm_update(s, s->rtsr);
pxa2xx_rtc_int_update(s);
static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
s->rtsr |= (1 << 6);
pxa2xx_rtc_alarm_update(s, s->rtsr);
pxa2xx_rtc_int_update(s);
static inline void pxa2xx_rtc_swal1_tick(void *opaque)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
s->rtsr |= (1 << 8);
pxa2xx_rtc_alarm_update(s, s->rtsr);
pxa2xx_rtc_int_update(s);
static inline void pxa2xx_rtc_swal2_tick(void *opaque)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
s->rtsr |= (1 << 10);
pxa2xx_rtc_alarm_update(s, s->rtsr);
pxa2xx_rtc_int_update(s);
static inline void pxa2xx_rtc_pi_tick(void *opaque)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
s->rtsr |= (1 << 13);
pxa2xx_rtc_piupdate(s);
s->last_rtcpicr = 0;
static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case RTTR:
static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
switch (addr) {
case RTTR:
pxa2xx_rtc_write,
};
-static void pxa2xx_rtc_init(struct pxa2xx_state_s *s)
+static void pxa2xx_rtc_init(PXA2xxState *s)
{
struct tm tm;
int wom;
static void pxa2xx_rtc_save(QEMUFile *f, void *opaque)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
pxa2xx_rtc_hzupdate(s);
pxa2xx_rtc_piupdate(s);
static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
qemu_get_be32s(f, &s->rttr);
qemu_get_be32s(f, &s->rtsr);
}
/* I2C Interface */
-struct pxa2xx_i2c_s {
- i2c_slave slave;
+typedef struct {
+ i2c_slave i2c;
+ PXA2xxI2CState *host;
+} PXA2xxI2CSlaveState;
+
+struct PXA2xxI2CState {
+ PXA2xxI2CSlaveState *slave;
i2c_bus *bus;
qemu_irq irq;
target_phys_addr_t offset;
#define ISR 0x98 /* I2C Status register */
#define ISAR 0xa0 /* I2C Slave Address register */
-static void pxa2xx_i2c_update(struct pxa2xx_i2c_s *s)
+static void pxa2xx_i2c_update(PXA2xxI2CState *s)
{
uint16_t level = 0;
level |= s->status & s->control & (1 << 10); /* BED */
/* These are only stubs now. */
static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
{
- struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
+ PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
+ PXA2xxI2CState *s = slave->host;
switch (event) {
case I2C_START_SEND:
static int pxa2xx_i2c_rx(i2c_slave *i2c)
{
- struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
+ PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
+ PXA2xxI2CState *s = slave->host;
if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
return 0;
static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
{
- struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
+ PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
+ PXA2xxI2CState *s = slave->host;
if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
return 1;
static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
{
- struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
+ PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
addr -= s->offset;
switch (addr) {
case ISR:
return s->status | (i2c_bus_busy(s->bus) << 2);
case ISAR:
- return s->slave.address;
+ return s->slave->i2c.address;
case IDBR:
return s->data;
case IBMR:
static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
+ PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
int ack;
addr -= s->offset;
break;
case ISAR:
- i2c_set_slave_address(&s->slave, value & 0x7f);
+ i2c_set_slave_address(&s->slave->i2c, value & 0x7f);
break;
case IDBR:
static void pxa2xx_i2c_save(QEMUFile *f, void *opaque)
{
- struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
+ PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
qemu_put_be16s(f, &s->control);
qemu_put_be16s(f, &s->status);
qemu_put_8s(f, &s->ibmr);
qemu_put_8s(f, &s->data);
- i2c_slave_save(f, &s->slave);
+ i2c_slave_save(f, &s->slave->i2c);
}
static int pxa2xx_i2c_load(QEMUFile *f, void *opaque, int version_id)
{
- struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
+ PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
if (version_id != 1)
return -EINVAL;
qemu_get_8s(f, &s->ibmr);
qemu_get_8s(f, &s->data);
- i2c_slave_load(f, &s->slave);
+ i2c_slave_load(f, &s->slave->i2c);
return 0;
}
-struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
+static void pxa2xx_i2c_slave_init(i2c_slave *i2c)
+{
+ /* Nothing to do. */
+}
+
+static I2CSlaveInfo pxa2xx_i2c_slave_info = {
+ .init = pxa2xx_i2c_slave_init,
+ .event = pxa2xx_i2c_event,
+ .recv = pxa2xx_i2c_rx,
+ .send = pxa2xx_i2c_tx
+};
+
+PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
qemu_irq irq, uint32_t region_size)
{
int iomemtype;
+ DeviceState *dev;
+ PXA2xxI2CState *s = qemu_mallocz(sizeof(PXA2xxI2CState));
+
/* FIXME: Should the slave device really be on a separate bus? */
- struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *)
- i2c_slave_init(i2c_init_bus(), 0, sizeof(struct pxa2xx_i2c_s));
+ dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0);
+ s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE_FROM_QDEV(dev));
+ s->slave->host = s;
s->irq = irq;
- s->slave.event = pxa2xx_i2c_event;
- s->slave.recv = pxa2xx_i2c_rx;
- s->slave.send = pxa2xx_i2c_tx;
- s->bus = i2c_init_bus();
+ s->bus = i2c_init_bus(NULL, "i2c");
s->offset = base - (base & (~region_size) & TARGET_PAGE_MASK);
iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
return s;
}
-i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s)
+i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
{
return s->bus;
}
/* PXA Inter-IC Sound Controller */
-static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s *i2s)
+static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
{
i2s->rx_len = 0;
i2s->tx_len = 0;
#define SACR_DREC(val) (val & (1 << 3))
#define SACR_DPRL(val) (val & (1 << 4))
-static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s *i2s)
+static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
{
int rfs, tfs;
rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
{
- struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
+ PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
switch (addr) {
case SACR0:
static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
+ PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
uint32_t *sample;
switch (addr) {
static void pxa2xx_i2s_save(QEMUFile *f, void *opaque)
{
- struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
+ PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
qemu_put_be32s(f, &s->control[0]);
qemu_put_be32s(f, &s->control[1]);
static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id)
{
- struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
+ PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
qemu_get_be32s(f, &s->control[0]);
qemu_get_be32s(f, &s->control[1]);
static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
{
- struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
+ PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
uint32_t *sample;
/* Signal FIFO errors */
pxa2xx_i2s_update(s);
}
-static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base,
- qemu_irq irq, struct pxa2xx_dma_state_s *dma)
+static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
+ qemu_irq irq, PXA2xxDMAState *dma)
{
int iomemtype;
- struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *)
- qemu_mallocz(sizeof(struct pxa2xx_i2s_s));
+ PXA2xxI2SState *s = (PXA2xxI2SState *)
+ qemu_mallocz(sizeof(PXA2xxI2SState));
s->irq = irq;
s->dma = dma;
}
/* PXA Fast Infra-red Communications Port */
-struct pxa2xx_fir_s {
+struct PXA2xxFIrState {
qemu_irq irq;
- struct pxa2xx_dma_state_s *dma;
+ PXA2xxDMAState *dma;
int enable;
CharDriverState *chr;
uint8_t rx_fifo[64];
};
-static void pxa2xx_fir_reset(struct pxa2xx_fir_s *s)
+static void pxa2xx_fir_reset(PXA2xxFIrState *s)
{
s->control[0] = 0x00;
s->control[1] = 0x00;
s->enable = 0;
}
-static inline void pxa2xx_fir_update(struct pxa2xx_fir_s *s)
+static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
{
static const int tresh[4] = { 8, 16, 32, 0 };
int intr = 0;
static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
{
- struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
+ PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
uint8_t ret;
switch (addr) {
static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
+ PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
uint8_t ch;
switch (addr) {
static int pxa2xx_fir_is_empty(void *opaque)
{
- struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
+ PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
return (s->rx_len < 64);
}
static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
{
- struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
+ PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
if (!(s->control[0] & (1 << 4))) /* RXE */
return;
static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
{
- struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
+ PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
int i;
qemu_put_be32(f, s->enable);
static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
{
- struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
+ PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
int i;
s->enable = qemu_get_be32(f);
return 0;
}
-static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base,
- qemu_irq irq, struct pxa2xx_dma_state_s *dma,
+static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
+ qemu_irq irq, PXA2xxDMAState *dma,
CharDriverState *chr)
{
int iomemtype;
- struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *)
- qemu_mallocz(sizeof(struct pxa2xx_fir_s));
+ PXA2xxFIrState *s = (PXA2xxFIrState *)
+ qemu_mallocz(sizeof(PXA2xxFIrState));
s->irq = irq;
s->dma = dma;
static void pxa2xx_reset(void *opaque, int line, int level)
{
- struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
+ PXA2xxState *s = (PXA2xxState *) opaque;
if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
cpu_reset(s->env);
}
/* Initialise a PXA270 integrated chip (ARM based core). */
-struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, const char *revision)
+PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
{
- struct pxa2xx_state_s *s;
- struct pxa2xx_ssp_s *ssp;
+ PXA2xxState *s;
int iomemtype, i;
int index;
- s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
+ s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
if (revision && strncmp(revision, "pxa27", 5)) {
fprintf(stderr, "Machine requires a PXA27x processor.\n");
register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
for (i = 0; pxa27x_ssp[i].io_base; i ++);
- s->ssp = (struct pxa2xx_ssp_s **)
- qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
- ssp = (struct pxa2xx_ssp_s *)
- qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
+ s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
for (i = 0; pxa27x_ssp[i].io_base; i ++) {
- target_phys_addr_t ssp_base;
- s->ssp[i] = &ssp[i];
- ssp_base = pxa27x_ssp[i].io_base;
- ssp[i].irq = s->pic[pxa27x_ssp[i].irqn];
-
- iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
- pxa2xx_ssp_writefn, &ssp[i]);
- cpu_register_physical_memory(ssp_base, 0x1000, iomemtype);
- register_savevm("pxa2xx_ssp", i, 0,
- pxa2xx_ssp_save, pxa2xx_ssp_load, s);
+ DeviceState *dev;
+ dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
+ s->pic[pxa27x_ssp[i].irqn]);
+ s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
}
if (usb_enabled) {
}
/* Initialise a PXA255 integrated chip (ARM based core). */
-struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size)
+PXA2xxState *pxa255_init(unsigned int sdram_size)
{
- struct pxa2xx_state_s *s;
- struct pxa2xx_ssp_s *ssp;
+ PXA2xxState *s;
int iomemtype, i;
int index;
- s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
+ s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
s->env = cpu_init("pxa255");
if (!s->env) {
register_savevm("pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
for (i = 0; pxa255_ssp[i].io_base; i ++);
- s->ssp = (struct pxa2xx_ssp_s **)
- qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
- ssp = (struct pxa2xx_ssp_s *)
- qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
+ s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
for (i = 0; pxa255_ssp[i].io_base; i ++) {
- target_phys_addr_t ssp_base;
- s->ssp[i] = &ssp[i];
- ssp_base = pxa255_ssp[i].io_base;
- ssp[i].irq = s->pic[pxa255_ssp[i].irqn];
-
- iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
- pxa2xx_ssp_writefn, &ssp[i]);
- cpu_register_physical_memory(ssp_base, 0x1000, iomemtype);
- register_savevm("pxa2xx_ssp", i, 0,
- pxa2xx_ssp_save, pxa2xx_ssp_load, s);
+ DeviceState *dev;
+ dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
+ s->pic[pxa255_ssp[i].irqn]);
+ s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
}
if (usb_enabled) {
pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
return s;
}
+
+static void pxa2xx_register_devices(void)
+{
+ i2c_register_slave("pxa2xx-i2c-slave", sizeof(PXA2xxI2CSlaveState),
+ &pxa2xx_i2c_slave_info);
+ sysbus_register_dev("pxa2xx-ssp", sizeof(PXA2xxSSPState), pxa2xx_ssp_init);
+}
+
+device_init(pxa2xx_register_devices)
projects / qemu / blobdiff