Merge commit 'gnu/master' into test

[qemu] / hw / pxa2xx_pic.c

diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c
index e8a601d..aa17ba3 100644 (file)
--- a/hw/pxa2xx_pic.c
+++ b/hw/pxa2xx_pic.c
@@ -30,19 +30,19 @@
 
 #define PXA2XX_PIC_SRCS        40
 
-struct pxa2xx_pic_state_s {
+typedef struct {
     CPUState *cpu_env;
     uint32_t int_enabled[2];
     uint32_t int_pending[2];
     uint32_t is_fiq[2];
     uint32_t int_idle;
     uint32_t priority[PXA2XX_PIC_SRCS];
-};
+} PXA2xxPICState;
 
 static void pxa2xx_pic_update(void *opaque)
 {
     uint32_t mask[2];
-    struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
+    PXA2xxPICState *s = (PXA2xxPICState *) opaque;
 
     if (s->cpu_env->halted) {
         mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
@@ -69,7 +69,7 @@ static void pxa2xx_pic_update(void *opaque)
  * IRQ/FIQ distinction as in PXA Developer Manual.  */
 static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
 {
-    struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
+    PXA2xxPICState *s = (PXA2xxPICState *) opaque;
     int int_set = (irq >= 32);
     irq &= 31;
 
@@ -81,7 +81,7 @@ static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
     pxa2xx_pic_update(opaque);
 }
 
-static inline uint32_t pxa2xx_pic_highest(struct pxa2xx_pic_state_s *s) {
+static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
     int i, int_set, irq;
     uint32_t bit, mask[2];
     uint32_t ichp = 0x003f003f;        /* Both IDs invalid */
@@ -115,7 +115,7 @@ static inline uint32_t pxa2xx_pic_highest(struct pxa2xx_pic_state_s *s) {
 
 static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset)
 {
-    struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
+    PXA2xxPICState *s = (PXA2xxPICState *) opaque;
 
     switch (offset) {
     case ICIP: /* IRQ Pending register */
@@ -155,7 +155,7 @@ static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset)
 static void pxa2xx_pic_mem_write(void *opaque, target_phys_addr_t offset,
                 uint32_t value)
 {
-    struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
+    PXA2xxPICState *s = (PXA2xxPICState *) opaque;
 
     switch (offset) {
     case ICMR: /* Mask register */
@@ -243,7 +243,7 @@ static CPUWriteMemoryFunc *pxa2xx_pic_writefn[] = {
 
 static void pxa2xx_pic_save(QEMUFile *f, void *opaque)
 {
-    struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
+    PXA2xxPICState *s = (PXA2xxPICState *) opaque;
     int i;
 
     for (i = 0; i < 2; i ++)
@@ -259,7 +259,7 @@ static void pxa2xx_pic_save(QEMUFile *f, void *opaque)
 
 static int pxa2xx_pic_load(QEMUFile *f, void *opaque, int version_id)
 {
-    struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
+    PXA2xxPICState *s = (PXA2xxPICState *) opaque;
     int i;
 
     for (i = 0; i < 2; i ++)
@@ -278,12 +278,12 @@ static int pxa2xx_pic_load(QEMUFile *f, void *opaque, int version_id)
 
 qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
 {
-    struct pxa2xx_pic_state_s *s;
+    PXA2xxPICState *s;
     int iomemtype;
     qemu_irq *qi;
 
-    s = (struct pxa2xx_pic_state_s *)
-            qemu_mallocz(sizeof(struct pxa2xx_pic_state_s));
+    s = (PXA2xxPICState *)
+            qemu_mallocz(sizeof(PXA2xxPICState));
     if (!s)
         return NULL;