2 * i386 emulator main execution loop
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 int tb_invalidated_flag;
27 //#define DEBUG_SIGNAL
29 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
30 /* XXX: unify with i386 target */
31 void cpu_loop_exit(void)
33 longjmp(env->jmp_env, 1);
37 /* main execution loop */
39 int cpu_exec(CPUState *env1)
41 int saved_T0, saved_T1, saved_T2;
70 int code_gen_size, ret, interrupt_request;
71 void (*gen_func)(void);
72 TranslationBlock *tb, **ptb;
73 uint8_t *tc_ptr, *cs_base, *pc;
76 /* first we save global registers */
83 /* we also save i7 because longjmp may not restore it */
84 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
87 #if defined(TARGET_I386)
90 EAX = env->regs[R_EAX];
94 ECX = env->regs[R_ECX];
98 EDX = env->regs[R_EDX];
102 EBX = env->regs[R_EBX];
106 ESP = env->regs[R_ESP];
110 EBP = env->regs[R_EBP];
114 ESI = env->regs[R_ESI];
118 EDI = env->regs[R_EDI];
121 /* put eflags in CPU temporary format */
122 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
123 DF = 1 - (2 * ((env->eflags >> 10) & 1));
124 CC_OP = CC_OP_EFLAGS;
125 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
126 #elif defined(TARGET_ARM)
130 env->CF = (psr >> 29) & 1;
131 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
132 env->VF = (psr << 3) & 0x80000000;
133 env->cpsr = psr & ~0xf0000000;
135 #elif defined(TARGET_SPARC)
137 #error unsupported target CPU
139 env->exception_index = -1;
141 /* prepare setjmp context for exception handling */
143 if (setjmp(env->jmp_env) == 0) {
144 /* if an exception is pending, we execute it here */
145 if (env->exception_index >= 0) {
146 if (env->exception_index >= EXCP_INTERRUPT) {
147 /* exit request from the cpu execution loop */
148 ret = env->exception_index;
150 } else if (env->user_mode_only) {
151 /* if user mode only, we simulate a fake exception
152 which will be hanlded outside the cpu execution
154 #if defined(TARGET_I386)
155 do_interrupt_user(env->exception_index,
156 env->exception_is_int,
158 env->exception_next_eip);
160 ret = env->exception_index;
163 #if defined(TARGET_I386)
164 /* simulate a real cpu exception. On i386, it can
165 trigger new exceptions, but we do not handle
166 double or triple faults yet. */
167 do_interrupt(env->exception_index,
168 env->exception_is_int,
170 env->exception_next_eip, 0);
173 env->exception_index = -1;
175 T0 = 0; /* force lookup of first TB */
178 /* g1 can be modified by some libc? functions */
181 interrupt_request = env->interrupt_request;
182 if (__builtin_expect(interrupt_request, 0)) {
183 #if defined(TARGET_I386)
184 /* if hardware interrupt pending, we execute it */
185 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
186 (env->eflags & IF_MASK) &&
187 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
189 intno = cpu_x86_get_pic_interrupt(env);
191 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
193 do_interrupt(intno, 0, 0, 0, 1);
194 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
195 /* ensure that no TB jump will be modified as
196 the program flow was changed */
204 if (interrupt_request & CPU_INTERRUPT_EXIT) {
205 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
206 env->exception_index = EXCP_INTERRUPT;
212 #if defined(TARGET_I386)
213 /* restore flags in standard format */
214 env->regs[R_EAX] = EAX;
215 env->regs[R_EBX] = EBX;
216 env->regs[R_ECX] = ECX;
217 env->regs[R_EDX] = EDX;
218 env->regs[R_ESI] = ESI;
219 env->regs[R_EDI] = EDI;
220 env->regs[R_EBP] = EBP;
221 env->regs[R_ESP] = ESP;
222 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
223 cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
224 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
225 #elif defined(TARGET_ARM)
226 env->cpsr = compute_cpsr();
227 cpu_arm_dump_state(env, logfile, 0);
228 env->cpsr &= ~0xf0000000;
229 #elif defined(TARGET_SPARC)
230 cpu_sparc_dump_state (env, logfile, 0);
232 #error unsupported target CPU
236 /* we record a subset of the CPU state. It will
237 always be the same before a given translated block
239 #if defined(TARGET_I386)
241 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
242 cs_base = env->segs[R_CS].base;
243 pc = cs_base + env->eip;
244 #elif defined(TARGET_ARM)
247 pc = (uint8_t *)env->regs[15];
248 #elif defined(TARGET_SPARC)
255 pc = (uint8_t *) env->pc;
257 #error unsupported CPU
259 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
263 /* if no translated code available, then translate it now */
264 tb = tb_alloc((unsigned long)pc);
266 /* flush must be done */
268 /* cannot fail at this point */
269 tb = tb_alloc((unsigned long)pc);
270 /* don't forget to invalidate previous TB info */
271 ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
274 tc_ptr = code_gen_ptr;
276 tb->cs_base = (unsigned long)cs_base;
278 tb_invalidated_flag = 0;
279 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
280 if (tb_invalidated_flag) {
281 /* as some TB could have been invalidated because
282 of memory exceptions while generating the code, we
283 must recompute the hash index here */
284 ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
286 ptb = &(*ptb)->hash_next;
290 tb->hash_next = NULL;
292 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
293 spin_unlock(&tb_lock);
297 fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
298 (long)tb->tc_ptr, (long)tb->pc,
299 lookup_symbol((void *)tb->pc));
305 /* see if we can patch the calling TB. */
308 tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
309 spin_unlock(&tb_lock);
312 env->current_tb = tb;
313 /* execute the generated code */
314 gen_func = (void *)tc_ptr;
315 #if defined(__sparc__)
316 __asm__ __volatile__("call %0\n\t"
320 : "i0", "i1", "i2", "i3", "i4", "i5");
321 #elif defined(__arm__)
322 asm volatile ("mov pc, %0\n\t"
323 ".global exec_loop\n\t"
327 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
331 env->current_tb = NULL;
332 /* reset soft MMU for next block (it can currently
333 only be set by a memory fault) */
334 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
335 if (env->hflags & HF_SOFTMMU_MASK) {
336 env->hflags &= ~HF_SOFTMMU_MASK;
337 /* do not allow linking to another block */
347 #if defined(TARGET_I386)
348 /* restore flags in standard format */
349 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
351 /* restore global registers */
376 #elif defined(TARGET_ARM)
377 env->cpsr = compute_cpsr();
378 #elif defined(TARGET_SPARC)
380 #error unsupported target CPU
383 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
392 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
394 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
396 CPUX86State *saved_env;
400 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
402 cpu_x86_load_seg_cache(env, seg_reg, selector,
403 (uint8_t *)(selector << 4), 0xffff, 0);
405 load_seg(seg_reg, selector, 0);
410 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
412 CPUX86State *saved_env;
417 helper_fsave(ptr, data32);
422 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
424 CPUX86State *saved_env;
429 helper_frstor(ptr, data32);
434 #endif /* TARGET_I386 */
446 #include <sys/ucontext.h>
448 #if defined(TARGET_I386)
450 /* 'pc' is the host PC at which the exception was raised. 'address' is
451 the effective address of the memory exception. 'is_write' is 1 if a
452 write caused the exception and otherwise 0'. 'old_set' is the
453 signal set which should be restored */
454 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
455 int is_write, sigset_t *old_set)
457 TranslationBlock *tb;
461 env = cpu_single_env; /* XXX: find a correct solution for multithread */
462 #if defined(DEBUG_SIGNAL)
463 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
464 pc, address, is_write, *(unsigned long *)old_set);
466 /* XXX: locking issue */
467 if (is_write && page_unprotect(address)) {
470 /* see if it is an MMU fault */
471 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
472 ((env->hflags & HF_CPL_MASK) == 3), 0);
474 return 0; /* not an MMU fault */
476 return 1; /* the MMU fault was handled without causing real CPU fault */
477 /* now we have a real cpu fault */
480 /* the PC is inside the translated code. It means that we have
481 a virtual CPU fault */
482 cpu_restore_state(tb, env, pc);
486 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
487 env->eip, env->cr[2], env->error_code);
489 /* we restore the process signal mask as the sigreturn should
490 do it (XXX: use sigsetjmp) */
491 sigprocmask(SIG_SETMASK, old_set, NULL);
492 raise_exception_err(EXCP0E_PAGE, env->error_code);
494 /* activate soft MMU for this block */
495 env->hflags |= HF_SOFTMMU_MASK;
496 sigprocmask(SIG_SETMASK, old_set, NULL);
499 /* never comes here */
503 #elif defined(TARGET_ARM)
504 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
505 int is_write, sigset_t *old_set)
510 #elif defined(TARGET_SPARC)
511 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
512 int is_write, sigset_t *old_set)
517 #error unsupported target CPU
520 #if defined(__i386__)
522 int cpu_signal_handler(int host_signum, struct siginfo *info,
525 struct ucontext *uc = puc;
532 #define REG_TRAPNO TRAPNO
534 pc = uc->uc_mcontext.gregs[REG_EIP];
535 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
536 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
537 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
541 #elif defined(__powerpc)
543 int cpu_signal_handler(int host_signum, struct siginfo *info,
546 struct ucontext *uc = puc;
547 struct pt_regs *regs = uc->uc_mcontext.regs;
555 if (regs->dsisr & 0x00800000)
558 if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
561 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
562 is_write, &uc->uc_sigmask);
565 #elif defined(__alpha__)
567 int cpu_signal_handler(int host_signum, struct siginfo *info,
570 struct ucontext *uc = puc;
571 uint32_t *pc = uc->uc_mcontext.sc_pc;
575 /* XXX: need kernel patch to get write flag faster */
576 switch (insn >> 26) {
591 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
592 is_write, &uc->uc_sigmask);
594 #elif defined(__sparc__)
596 int cpu_signal_handler(int host_signum, struct siginfo *info,
599 uint32_t *regs = (uint32_t *)(info + 1);
600 void *sigmask = (regs + 20);
605 /* XXX: is there a standard glibc define ? */
607 /* XXX: need kernel patch to get write flag faster */
609 insn = *(uint32_t *)pc;
610 if ((insn >> 30) == 3) {
611 switch((insn >> 19) & 0x3f) {
623 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
627 #elif defined(__arm__)
629 int cpu_signal_handler(int host_signum, struct siginfo *info,
632 struct ucontext *uc = puc;
636 pc = uc->uc_mcontext.gregs[R15];
637 /* XXX: compute is_write */
639 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
644 #elif defined(__mc68000)
646 int cpu_signal_handler(int host_signum, struct siginfo *info,
649 struct ucontext *uc = puc;
653 pc = uc->uc_mcontext.gregs[16];
654 /* XXX: compute is_write */
656 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
663 #error host CPU specific signal handler needed