2 * i386 emulator main execution loop
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include "exec-i386.h"
31 //#define DEBUG_SIGNAL
33 #if defined(TARGET_ARM)
34 /* XXX: unify with i386 target */
35 void cpu_loop_exit(void)
37 longjmp(env->jmp_env, 1);
41 /* main execution loop */
43 int cpu_exec(CPUState *env1)
45 int saved_T0, saved_T1, saved_T2;
74 int code_gen_size, ret, interrupt_request;
75 void (*gen_func)(void);
76 TranslationBlock *tb, **ptb;
77 uint8_t *tc_ptr, *cs_base, *pc;
80 /* first we save global registers */
87 /* we also save i7 because longjmp may not restore it */
88 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
91 #if defined(TARGET_I386)
94 EAX = env->regs[R_EAX];
98 ECX = env->regs[R_ECX];
102 EDX = env->regs[R_EDX];
106 EBX = env->regs[R_EBX];
110 ESP = env->regs[R_ESP];
114 EBP = env->regs[R_EBP];
118 ESI = env->regs[R_ESI];
122 EDI = env->regs[R_EDI];
125 /* put eflags in CPU temporary format */
126 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
127 DF = 1 - (2 * ((env->eflags >> 10) & 1));
128 CC_OP = CC_OP_EFLAGS;
129 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
130 #elif defined(TARGET_ARM)
134 env->CF = (psr >> 29) & 1;
135 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
136 env->VF = (psr << 3) & 0x80000000;
137 env->cpsr = psr & ~0xf0000000;
140 #error unsupported target CPU
142 env->exception_index = -1;
144 /* prepare setjmp context for exception handling */
146 if (setjmp(env->jmp_env) == 0) {
147 /* if an exception is pending, we execute it here */
148 if (env->exception_index >= 0) {
149 if (env->exception_index >= EXCP_INTERRUPT) {
150 /* exit request from the cpu execution loop */
151 ret = env->exception_index;
153 } else if (env->user_mode_only) {
154 /* if user mode only, we simulate a fake exception
155 which will be hanlded outside the cpu execution
157 #if defined(TARGET_I386)
158 do_interrupt_user(env->exception_index,
159 env->exception_is_int,
161 env->exception_next_eip);
163 ret = env->exception_index;
166 #if defined(TARGET_I386)
167 /* simulate a real cpu exception. On i386, it can
168 trigger new exceptions, but we do not handle
169 double or triple faults yet. */
170 do_interrupt(env->exception_index,
171 env->exception_is_int,
173 env->exception_next_eip);
176 env->exception_index = -1;
178 T0 = 0; /* force lookup of first TB */
181 /* g1 can be modified by some libc? functions */
184 interrupt_request = env->interrupt_request;
185 if (interrupt_request) {
186 #if defined(TARGET_I386)
187 /* if hardware interrupt pending, we execute it */
188 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
189 (env->eflags & IF_MASK)) {
191 intno = cpu_x86_get_pic_interrupt(env);
193 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
195 do_interrupt(intno, 0, 0, 0);
196 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
199 if (interrupt_request & CPU_INTERRUPT_EXIT) {
200 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
201 env->exception_index = EXCP_INTERRUPT;
207 #if defined(TARGET_I386)
208 /* restore flags in standard format */
209 env->regs[R_EAX] = EAX;
210 env->regs[R_EBX] = EBX;
211 env->regs[R_ECX] = ECX;
212 env->regs[R_EDX] = EDX;
213 env->regs[R_ESI] = ESI;
214 env->regs[R_EDI] = EDI;
215 env->regs[R_EBP] = EBP;
216 env->regs[R_ESP] = ESP;
217 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
218 cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
219 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
220 #elif defined(TARGET_ARM)
221 cpu_arm_dump_state(env, logfile, 0);
223 #error unsupported target CPU
227 /* we compute the CPU state. We assume it will not
228 change during the whole generated block. */
229 #if defined(TARGET_I386)
230 flags = (env->segs[R_CS].flags & DESC_B_MASK)
231 >> (DESC_B_SHIFT - GEN_FLAG_CODE32_SHIFT);
232 flags |= (env->segs[R_SS].flags & DESC_B_MASK)
233 >> (DESC_B_SHIFT - GEN_FLAG_SS32_SHIFT);
234 flags |= (((unsigned long)env->segs[R_DS].base |
235 (unsigned long)env->segs[R_ES].base |
236 (unsigned long)env->segs[R_SS].base) != 0) <<
237 GEN_FLAG_ADDSEG_SHIFT;
238 if (!(env->eflags & VM_MASK)) {
239 flags |= (env->segs[R_CS].selector & 3) << GEN_FLAG_CPL_SHIFT;
241 /* NOTE: a dummy CPL is kept */
242 flags |= (1 << GEN_FLAG_VM_SHIFT);
243 flags |= (3 << GEN_FLAG_CPL_SHIFT);
245 flags |= (env->eflags & (IOPL_MASK | TF_MASK));
246 cs_base = env->segs[R_CS].base;
247 pc = cs_base + env->eip;
248 #elif defined(TARGET_ARM)
251 pc = (uint8_t *)env->regs[15];
253 #error unsupported CPU
255 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
259 /* if no translated code available, then translate it now */
260 tb = tb_alloc((unsigned long)pc);
262 /* flush must be done */
264 /* cannot fail at this point */
265 tb = tb_alloc((unsigned long)pc);
266 /* don't forget to invalidate previous TB info */
267 ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
270 tc_ptr = code_gen_ptr;
272 tb->cs_base = (unsigned long)cs_base;
274 ret = cpu_gen_code(tb, CODE_GEN_MAX_SIZE, &code_gen_size);
275 #if defined(TARGET_I386)
276 /* XXX: suppress that, this is incorrect */
277 /* if invalid instruction, signal it */
279 /* NOTE: the tb is allocated but not linked, so we
281 spin_unlock(&tb_lock);
282 raise_exception(EXCP06_ILLOP);
286 tb->hash_next = NULL;
288 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
289 spin_unlock(&tb_lock);
293 fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
294 (long)tb->tc_ptr, (long)tb->pc,
295 lookup_symbol((void *)tb->pc));
301 /* see if we can patch the calling TB. XXX: remove TF test */
303 #if defined(TARGET_I386)
304 && !(env->eflags & TF_MASK)
308 tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
309 spin_unlock(&tb_lock);
312 env->current_tb = tb;
313 /* execute the generated code */
314 gen_func = (void *)tc_ptr;
315 #if defined(__sparc__)
316 __asm__ __volatile__("call %0\n\t"
320 : "i0", "i1", "i2", "i3", "i4", "i5");
321 #elif defined(__arm__)
322 asm volatile ("mov pc, %0\n\t"
323 ".global exec_loop\n\t"
327 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
331 env->current_tb = NULL;
338 #if defined(TARGET_I386)
339 /* restore flags in standard format */
340 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
342 /* restore global registers */
367 #elif defined(TARGET_ARM)
370 ZF = (env->NZF == 0);
371 env->cpsr = env->cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
372 (env->CF << 29) | ((env->VF & 0x80000000) >> 3);
375 #error unsupported target CPU
378 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
387 #if defined(TARGET_I386)
389 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
391 CPUX86State *saved_env;
395 if (env->eflags & VM_MASK) {
398 sc = &env->segs[seg_reg];
399 /* NOTE: in VM86 mode, limit and flags are never reloaded,
400 so we must load them here */
401 sc->base = (void *)(selector << 4);
404 sc->selector = selector;
406 load_seg(seg_reg, selector, 0);
411 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
413 CPUX86State *saved_env;
418 helper_fsave(ptr, data32);
423 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
425 CPUX86State *saved_env;
430 helper_frstor(ptr, data32);
435 #endif /* TARGET_I386 */
447 #include <sys/ucontext.h>
449 #if defined(TARGET_I386)
451 /* 'pc' is the host PC at which the exception was raised. 'address' is
452 the effective address of the memory exception. 'is_write' is 1 if a
453 write caused the exception and otherwise 0'. 'old_set' is the
454 signal set which should be restored */
455 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
456 int is_write, sigset_t *old_set)
458 TranslationBlock *tb;
462 env = cpu_single_env; /* XXX: find a correct solution for multithread */
463 #if defined(DEBUG_SIGNAL)
464 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
465 pc, address, is_write, *(unsigned long *)old_set);
467 /* XXX: locking issue */
468 if (is_write && page_unprotect(address)) {
471 /* see if it is an MMU fault */
472 ret = cpu_x86_handle_mmu_fault(env, address, is_write);
474 return 0; /* not an MMU fault */
476 return 1; /* the MMU fault was handled without causing real CPU fault */
477 /* now we have a real cpu fault */
480 /* the PC is inside the translated code. It means that we have
481 a virtual CPU fault */
482 cpu_restore_state(tb, env, pc);
485 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
486 env->eip, env->cr[2], env->error_code);
488 /* we restore the process signal mask as the sigreturn should
489 do it (XXX: use sigsetjmp) */
490 sigprocmask(SIG_SETMASK, old_set, NULL);
491 raise_exception_err(EXCP0E_PAGE, env->error_code);
492 /* never comes here */
496 #elif defined(TARGET_ARM)
497 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
498 int is_write, sigset_t *old_set)
504 #error unsupported target CPU
507 #if defined(__i386__)
509 int cpu_signal_handler(int host_signum, struct siginfo *info,
512 struct ucontext *uc = puc;
519 #define REG_TRAPNO TRAPNO
521 pc = uc->uc_mcontext.gregs[REG_EIP];
522 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
523 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
524 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
528 #elif defined(__powerpc)
530 int cpu_signal_handler(int host_signum, struct siginfo *info,
533 struct ucontext *uc = puc;
534 struct pt_regs *regs = uc->uc_mcontext.regs;
542 if (regs->dsisr & 0x00800000)
545 if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
548 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
549 is_write, &uc->uc_sigmask);
552 #elif defined(__alpha__)
554 int cpu_signal_handler(int host_signum, struct siginfo *info,
557 struct ucontext *uc = puc;
558 uint32_t *pc = uc->uc_mcontext.sc_pc;
562 /* XXX: need kernel patch to get write flag faster */
563 switch (insn >> 26) {
578 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
579 is_write, &uc->uc_sigmask);
581 #elif defined(__sparc__)
583 int cpu_signal_handler(int host_signum, struct siginfo *info,
586 uint32_t *regs = (uint32_t *)(info + 1);
587 void *sigmask = (regs + 20);
592 /* XXX: is there a standard glibc define ? */
594 /* XXX: need kernel patch to get write flag faster */
596 insn = *(uint32_t *)pc;
597 if ((insn >> 30) == 3) {
598 switch((insn >> 19) & 0x3f) {
610 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
614 #elif defined(__arm__)
616 int cpu_signal_handler(int host_signum, struct siginfo *info,
619 struct ucontext *uc = puc;
623 pc = uc->uc_mcontext.gregs[R15];
624 /* XXX: compute is_write */
626 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
633 #error host CPU specific signal handler needed