2 * i386 emulator main execution loop
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #if !defined(CONFIG_SOFTMMU)
35 #include <sys/ucontext.h>
38 int tb_invalidated_flag;
41 //#define DEBUG_SIGNAL
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
47 longjmp(env->jmp_env, 1);
51 /* exit the current TB from a signal handler. The host registers are
52 restored in a state compatible with the CPU emulator
54 void cpu_resume_from_signal(CPUState *env1, void *puc)
56 #if !defined(CONFIG_SOFTMMU)
57 struct ucontext *uc = puc;
62 /* XXX: restore cpu registers saved in host registers */
64 #if !defined(CONFIG_SOFTMMU)
66 /* XXX: use siglongjmp ? */
67 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
70 longjmp(env->jmp_env, 1);
73 /* main execution loop */
75 int cpu_exec(CPUState *env1)
77 int saved_T0, saved_T1, saved_T2;
104 int saved_i7, tmp_T0;
106 int code_gen_size, ret, interrupt_request;
107 void (*gen_func)(void);
108 TranslationBlock *tb, **ptb;
109 target_ulong cs_base, pc;
113 /* first we save global registers */
120 /* we also save i7 because longjmp may not restore it */
121 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
124 #if defined(TARGET_I386)
151 /* put eflags in CPU temporary format */
152 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
153 DF = 1 - (2 * ((env->eflags >> 10) & 1));
154 CC_OP = CC_OP_EFLAGS;
155 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
156 #elif defined(TARGET_ARM)
160 env->CF = (psr >> 29) & 1;
161 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
162 env->VF = (psr << 3) & 0x80000000;
163 env->QF = (psr >> 27) & 1;
164 env->cpsr = psr & ~CACHED_CPSR_BITS;
166 #elif defined(TARGET_SPARC)
167 #elif defined(TARGET_PPC)
169 #error unsupported target CPU
171 env->exception_index = -1;
173 /* prepare setjmp context for exception handling */
175 if (setjmp(env->jmp_env) == 0) {
176 env->current_tb = NULL;
177 /* if an exception is pending, we execute it here */
178 if (env->exception_index >= 0) {
179 if (env->exception_index >= EXCP_INTERRUPT) {
180 /* exit request from the cpu execution loop */
181 ret = env->exception_index;
183 } else if (env->user_mode_only) {
184 /* if user mode only, we simulate a fake exception
185 which will be hanlded outside the cpu execution
187 #if defined(TARGET_I386)
188 do_interrupt_user(env->exception_index,
189 env->exception_is_int,
191 env->exception_next_eip);
193 ret = env->exception_index;
196 #if defined(TARGET_I386)
197 /* simulate a real cpu exception. On i386, it can
198 trigger new exceptions, but we do not handle
199 double or triple faults yet. */
200 do_interrupt(env->exception_index,
201 env->exception_is_int,
203 env->exception_next_eip, 0);
204 #elif defined(TARGET_PPC)
206 #elif defined(TARGET_SPARC)
207 do_interrupt(env->exception_index);
210 env->exception_index = -1;
213 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
215 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
216 ret = kqemu_cpu_exec(env);
217 /* put eflags in CPU temporary format */
218 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
219 DF = 1 - (2 * ((env->eflags >> 10) & 1));
220 CC_OP = CC_OP_EFLAGS;
221 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
224 longjmp(env->jmp_env, 1);
225 } else if (ret == 2) {
226 /* softmmu execution needed */
228 if (env->interrupt_request != 0) {
229 /* hardware interrupt will be executed just after */
231 /* otherwise, we restart */
232 longjmp(env->jmp_env, 1);
238 T0 = 0; /* force lookup of first TB */
241 /* g1 can be modified by some libc? functions */
244 interrupt_request = env->interrupt_request;
245 if (__builtin_expect(interrupt_request, 0)) {
246 #if defined(TARGET_I386)
247 /* if hardware interrupt pending, we execute it */
248 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
249 (env->eflags & IF_MASK) &&
250 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
252 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
253 intno = cpu_get_pic_interrupt(env);
254 if (loglevel & CPU_LOG_TB_IN_ASM) {
255 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
257 do_interrupt(intno, 0, 0, 0, 1);
258 /* ensure that no TB jump will be modified as
259 the program flow was changed */
266 #elif defined(TARGET_PPC)
268 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
273 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
275 env->exception_index = EXCP_EXTERNAL;
278 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
279 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
281 env->exception_index = EXCP_DECR;
284 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
287 #elif defined(TARGET_SPARC)
288 if (interrupt_request & CPU_INTERRUPT_HARD) {
289 do_interrupt(env->interrupt_index);
290 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
291 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
292 //do_interrupt(0, 0, 0, 0, 0);
293 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
296 if (interrupt_request & CPU_INTERRUPT_EXITTB) {
297 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
298 /* ensure that no TB jump will be modified as
299 the program flow was changed */
306 if (interrupt_request & CPU_INTERRUPT_EXIT) {
307 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
308 env->exception_index = EXCP_INTERRUPT;
313 if ((loglevel & CPU_LOG_EXEC)) {
314 #if defined(TARGET_I386)
315 /* restore flags in standard format */
316 env->regs[R_EAX] = EAX;
317 env->regs[R_EBX] = EBX;
318 env->regs[R_ECX] = ECX;
319 env->regs[R_EDX] = EDX;
320 env->regs[R_ESI] = ESI;
321 env->regs[R_EDI] = EDI;
322 env->regs[R_EBP] = EBP;
323 env->regs[R_ESP] = ESP;
324 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
325 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
326 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
327 #elif defined(TARGET_ARM)
328 env->cpsr = compute_cpsr();
329 cpu_dump_state(env, logfile, fprintf, 0);
330 env->cpsr &= ~CACHED_CPSR_BITS;
331 #elif defined(TARGET_SPARC)
332 cpu_dump_state (env, logfile, fprintf, 0);
333 #elif defined(TARGET_PPC)
334 cpu_dump_state(env, logfile, fprintf, 0);
336 #error unsupported target CPU
340 /* we record a subset of the CPU state. It will
341 always be the same before a given translated block
343 #if defined(TARGET_I386)
345 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
346 cs_base = env->segs[R_CS].base;
347 pc = cs_base + env->eip;
348 #elif defined(TARGET_ARM)
352 #elif defined(TARGET_SPARC)
356 #elif defined(TARGET_PPC)
357 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) | (msr_se << MSR_SE);
361 #error unsupported CPU
363 tb = tb_find(&ptb, pc, cs_base,
366 TranslationBlock **ptb1;
368 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
373 tb_invalidated_flag = 0;
375 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
377 /* find translated block using physical mappings */
378 phys_pc = get_phys_addr_code(env, pc);
379 phys_page1 = phys_pc & TARGET_PAGE_MASK;
381 h = tb_phys_hash_func(phys_pc);
382 ptb1 = &tb_phys_hash[h];
388 tb->page_addr[0] == phys_page1 &&
389 tb->cs_base == cs_base &&
390 tb->flags == flags) {
391 /* check next page if needed */
392 if (tb->page_addr[1] != -1) {
393 virt_page2 = (pc & TARGET_PAGE_MASK) +
395 phys_page2 = get_phys_addr_code(env, virt_page2);
396 if (tb->page_addr[1] == phys_page2)
402 ptb1 = &tb->phys_hash_next;
405 /* if no translated code available, then translate it now */
408 /* flush must be done */
410 /* cannot fail at this point */
412 /* don't forget to invalidate previous TB info */
413 ptb = &tb_hash[tb_hash_func(pc)];
416 tc_ptr = code_gen_ptr;
418 tb->cs_base = cs_base;
420 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
421 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
423 /* check next page if needed */
424 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
426 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
427 phys_page2 = get_phys_addr_code(env, virt_page2);
429 tb_link_phys(tb, phys_pc, phys_page2);
432 if (tb_invalidated_flag) {
433 /* as some TB could have been invalidated because
434 of memory exceptions while generating the code, we
435 must recompute the hash index here */
436 ptb = &tb_hash[tb_hash_func(pc)];
438 ptb = &(*ptb)->hash_next;
441 /* we add the TB in the virtual pc hash table */
443 tb->hash_next = NULL;
445 spin_unlock(&tb_lock);
448 if ((loglevel & CPU_LOG_EXEC)) {
449 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
450 (long)tb->tc_ptr, tb->pc,
451 lookup_symbol(tb->pc));
457 /* see if we can patch the calling TB. */
460 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
461 && (tb->cflags & CF_CODE_COPY) ==
462 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
466 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
467 #if defined(USE_CODE_COPY)
468 /* propagates the FP use info */
469 ((TranslationBlock *)(T0 & ~3))->cflags |=
470 (tb->cflags & CF_FP_USED);
472 spin_unlock(&tb_lock);
476 env->current_tb = tb;
477 /* execute the generated code */
478 gen_func = (void *)tc_ptr;
479 #if defined(__sparc__)
480 __asm__ __volatile__("call %0\n\t"
484 : "i0", "i1", "i2", "i3", "i4", "i5");
485 #elif defined(__arm__)
486 asm volatile ("mov pc, %0\n\t"
487 ".global exec_loop\n\t"
491 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
492 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
494 if (!(tb->cflags & CF_CODE_COPY)) {
495 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
496 save_native_fp_state(env);
500 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
501 restore_native_fp_state(env);
503 /* we work with native eflags */
504 CC_SRC = cc_table[CC_OP].compute_all();
505 CC_OP = CC_OP_EFLAGS;
506 asm(".globl exec_loop\n"
511 " fs movl %11, %%eax\n"
512 " andl $0x400, %%eax\n"
513 " fs orl %8, %%eax\n"
516 " fs movl %%esp, %12\n"
517 " fs movl %0, %%eax\n"
518 " fs movl %1, %%ecx\n"
519 " fs movl %2, %%edx\n"
520 " fs movl %3, %%ebx\n"
521 " fs movl %4, %%esp\n"
522 " fs movl %5, %%ebp\n"
523 " fs movl %6, %%esi\n"
524 " fs movl %7, %%edi\n"
527 " fs movl %%esp, %4\n"
528 " fs movl %12, %%esp\n"
529 " fs movl %%eax, %0\n"
530 " fs movl %%ecx, %1\n"
531 " fs movl %%edx, %2\n"
532 " fs movl %%ebx, %3\n"
533 " fs movl %%ebp, %5\n"
534 " fs movl %%esi, %6\n"
535 " fs movl %%edi, %7\n"
538 " movl %%eax, %%ecx\n"
539 " andl $0x400, %%ecx\n"
541 " andl $0x8d5, %%eax\n"
542 " fs movl %%eax, %8\n"
544 " subl %%ecx, %%eax\n"
545 " fs movl %%eax, %11\n"
546 " fs movl %9, %%ebx\n" /* get T0 value */
549 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
550 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
551 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
552 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
553 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
554 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
555 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
556 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
557 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
558 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
560 "m" (*(uint8_t *)offsetof(CPUState, df)),
561 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
569 env->current_tb = NULL;
570 /* reset soft MMU for next block (it can currently
571 only be set by a memory fault) */
572 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
573 if (env->hflags & HF_SOFTMMU_MASK) {
574 env->hflags &= ~HF_SOFTMMU_MASK;
575 /* do not allow linking to another block */
586 #if defined(TARGET_I386)
587 #if defined(USE_CODE_COPY)
588 if (env->native_fp_regs) {
589 save_native_fp_state(env);
592 /* restore flags in standard format */
593 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
595 /* restore global registers */
620 #elif defined(TARGET_ARM)
621 env->cpsr = compute_cpsr();
622 #elif defined(TARGET_SPARC)
623 #elif defined(TARGET_PPC)
625 #error unsupported target CPU
628 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
637 /* must only be called from the generated code as an exception can be
639 void tb_invalidate_page_range(target_ulong start, target_ulong end)
641 /* XXX: cannot enable it yet because it yields to MMU exception
642 where NIP != read address on PowerPC */
644 target_ulong phys_addr;
645 phys_addr = get_phys_addr_code(env, start);
646 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
650 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
652 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
654 CPUX86State *saved_env;
658 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
660 cpu_x86_load_seg_cache(env, seg_reg, selector,
661 (selector << 4), 0xffff, 0);
663 load_seg(seg_reg, selector);
668 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
670 CPUX86State *saved_env;
675 helper_fsave((target_ulong)ptr, data32);
680 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
682 CPUX86State *saved_env;
687 helper_frstor((target_ulong)ptr, data32);
692 #endif /* TARGET_I386 */
694 #if !defined(CONFIG_SOFTMMU)
696 #if defined(TARGET_I386)
698 /* 'pc' is the host PC at which the exception was raised. 'address' is
699 the effective address of the memory exception. 'is_write' is 1 if a
700 write caused the exception and otherwise 0'. 'old_set' is the
701 signal set which should be restored */
702 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
703 int is_write, sigset_t *old_set,
706 TranslationBlock *tb;
710 env = cpu_single_env; /* XXX: find a correct solution for multithread */
711 #if defined(DEBUG_SIGNAL)
712 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
713 pc, address, is_write, *(unsigned long *)old_set);
715 /* XXX: locking issue */
716 if (is_write && page_unprotect(address, pc, puc)) {
720 /* see if it is an MMU fault */
721 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
722 ((env->hflags & HF_CPL_MASK) == 3), 0);
724 return 0; /* not an MMU fault */
726 return 1; /* the MMU fault was handled without causing real CPU fault */
727 /* now we have a real cpu fault */
730 /* the PC is inside the translated code. It means that we have
731 a virtual CPU fault */
732 cpu_restore_state(tb, env, pc, puc);
736 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
737 env->eip, env->cr[2], env->error_code);
739 /* we restore the process signal mask as the sigreturn should
740 do it (XXX: use sigsetjmp) */
741 sigprocmask(SIG_SETMASK, old_set, NULL);
742 raise_exception_err(EXCP0E_PAGE, env->error_code);
744 /* activate soft MMU for this block */
745 env->hflags |= HF_SOFTMMU_MASK;
746 cpu_resume_from_signal(env, puc);
748 /* never comes here */
752 #elif defined(TARGET_ARM)
753 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
754 int is_write, sigset_t *old_set,
757 TranslationBlock *tb;
761 env = cpu_single_env; /* XXX: find a correct solution for multithread */
762 #if defined(DEBUG_SIGNAL)
763 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
764 pc, address, is_write, *(unsigned long *)old_set);
766 /* XXX: locking issue */
767 if (is_write && page_unprotect(address, pc, puc)) {
770 /* see if it is an MMU fault */
771 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
773 return 0; /* not an MMU fault */
775 return 1; /* the MMU fault was handled without causing real CPU fault */
776 /* now we have a real cpu fault */
779 /* the PC is inside the translated code. It means that we have
780 a virtual CPU fault */
781 cpu_restore_state(tb, env, pc, puc);
783 /* we restore the process signal mask as the sigreturn should
784 do it (XXX: use sigsetjmp) */
785 sigprocmask(SIG_SETMASK, old_set, NULL);
788 #elif defined(TARGET_SPARC)
789 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
790 int is_write, sigset_t *old_set,
793 TranslationBlock *tb;
797 env = cpu_single_env; /* XXX: find a correct solution for multithread */
798 #if defined(DEBUG_SIGNAL)
799 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
800 pc, address, is_write, *(unsigned long *)old_set);
802 /* XXX: locking issue */
803 if (is_write && page_unprotect(address, pc, puc)) {
806 /* see if it is an MMU fault */
807 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
809 return 0; /* not an MMU fault */
811 return 1; /* the MMU fault was handled without causing real CPU fault */
812 /* now we have a real cpu fault */
815 /* the PC is inside the translated code. It means that we have
816 a virtual CPU fault */
817 cpu_restore_state(tb, env, pc, puc);
819 /* we restore the process signal mask as the sigreturn should
820 do it (XXX: use sigsetjmp) */
821 sigprocmask(SIG_SETMASK, old_set, NULL);
824 #elif defined (TARGET_PPC)
825 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
826 int is_write, sigset_t *old_set,
829 TranslationBlock *tb;
833 env = cpu_single_env; /* XXX: find a correct solution for multithread */
834 #if defined(DEBUG_SIGNAL)
835 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
836 pc, address, is_write, *(unsigned long *)old_set);
838 /* XXX: locking issue */
839 if (is_write && page_unprotect(address, pc, puc)) {
843 /* see if it is an MMU fault */
844 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
846 return 0; /* not an MMU fault */
848 return 1; /* the MMU fault was handled without causing real CPU fault */
850 /* now we have a real cpu fault */
853 /* the PC is inside the translated code. It means that we have
854 a virtual CPU fault */
855 cpu_restore_state(tb, env, pc, puc);
859 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
860 env->nip, env->error_code, tb);
862 /* we restore the process signal mask as the sigreturn should
863 do it (XXX: use sigsetjmp) */
864 sigprocmask(SIG_SETMASK, old_set, NULL);
865 do_raise_exception_err(env->exception_index, env->error_code);
867 /* activate soft MMU for this block */
868 cpu_resume_from_signal(env, puc);
870 /* never comes here */
874 #error unsupported target CPU
877 #if defined(__i386__)
879 #if defined(USE_CODE_COPY)
880 static void cpu_send_trap(unsigned long pc, int trap,
883 TranslationBlock *tb;
886 env = cpu_single_env; /* XXX: find a correct solution for multithread */
887 /* now we have a real cpu fault */
890 /* the PC is inside the translated code. It means that we have
891 a virtual CPU fault */
892 cpu_restore_state(tb, env, pc, uc);
894 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
895 raise_exception_err(trap, env->error_code);
899 int cpu_signal_handler(int host_signum, struct siginfo *info,
902 struct ucontext *uc = puc;
910 #define REG_TRAPNO TRAPNO
912 pc = uc->uc_mcontext.gregs[REG_EIP];
913 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
914 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
915 if (trapno == 0x00 || trapno == 0x05) {
916 /* send division by zero or bound exception */
917 cpu_send_trap(pc, trapno, uc);
921 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
923 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
924 &uc->uc_sigmask, puc);
927 #elif defined(__x86_64__)
929 int cpu_signal_handler(int host_signum, struct siginfo *info,
932 struct ucontext *uc = puc;
935 pc = uc->uc_mcontext.gregs[REG_RIP];
936 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
937 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
938 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
939 &uc->uc_sigmask, puc);
942 #elif defined(__powerpc__)
944 /***********************************************************************
945 * signal context platform-specific definitions
949 /* All Registers access - only for local access */
950 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
951 /* Gpr Registers access */
952 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
953 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
954 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
955 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
956 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
957 # define LR_sig(context) REG_sig(link, context) /* Link register */
958 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
959 /* Float Registers access */
960 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
961 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
962 /* Exception Registers access */
963 # define DAR_sig(context) REG_sig(dar, context)
964 # define DSISR_sig(context) REG_sig(dsisr, context)
965 # define TRAP_sig(context) REG_sig(trap, context)
969 # include <sys/ucontext.h>
970 typedef struct ucontext SIGCONTEXT;
971 /* All Registers access - only for local access */
972 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
973 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
974 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
975 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
976 /* Gpr Registers access */
977 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
978 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
979 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
980 # define CTR_sig(context) REG_sig(ctr, context)
981 # define XER_sig(context) REG_sig(xer, context) /* Link register */
982 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
983 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
984 /* Float Registers access */
985 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
986 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
987 /* Exception Registers access */
988 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
989 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
990 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
991 #endif /* __APPLE__ */
993 int cpu_signal_handler(int host_signum, struct siginfo *info,
996 struct ucontext *uc = puc;
1004 if (DSISR_sig(uc) & 0x00800000)
1007 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1010 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1011 is_write, &uc->uc_sigmask, puc);
1014 #elif defined(__alpha__)
1016 int cpu_signal_handler(int host_signum, struct siginfo *info,
1019 struct ucontext *uc = puc;
1020 uint32_t *pc = uc->uc_mcontext.sc_pc;
1021 uint32_t insn = *pc;
1024 /* XXX: need kernel patch to get write flag faster */
1025 switch (insn >> 26) {
1040 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1041 is_write, &uc->uc_sigmask, puc);
1043 #elif defined(__sparc__)
1045 int cpu_signal_handler(int host_signum, struct siginfo *info,
1048 uint32_t *regs = (uint32_t *)(info + 1);
1049 void *sigmask = (regs + 20);
1054 /* XXX: is there a standard glibc define ? */
1056 /* XXX: need kernel patch to get write flag faster */
1058 insn = *(uint32_t *)pc;
1059 if ((insn >> 30) == 3) {
1060 switch((insn >> 19) & 0x3f) {
1072 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1073 is_write, sigmask, NULL);
1076 #elif defined(__arm__)
1078 int cpu_signal_handler(int host_signum, struct siginfo *info,
1081 struct ucontext *uc = puc;
1085 pc = uc->uc_mcontext.gregs[R15];
1086 /* XXX: compute is_write */
1088 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1093 #elif defined(__mc68000)
1095 int cpu_signal_handler(int host_signum, struct siginfo *info,
1098 struct ucontext *uc = puc;
1102 pc = uc->uc_mcontext.gregs[16];
1103 /* XXX: compute is_write */
1105 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1107 &uc->uc_sigmask, puc);
1112 #error host CPU specific signal handler needed
1116 #endif /* !defined(CONFIG_SOFTMMU) */