2 * i386 emulator main execution loop
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 int tb_invalidated_flag;
27 //#define DEBUG_SIGNAL
29 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
30 /* XXX: unify with i386 target */
31 void cpu_loop_exit(void)
33 longjmp(env->jmp_env, 1);
37 /* main execution loop */
39 int cpu_exec(CPUState *env1)
41 int saved_T0, saved_T1, saved_T2;
70 int code_gen_size, ret, interrupt_request;
71 void (*gen_func)(void);
72 TranslationBlock *tb, **ptb;
73 uint8_t *tc_ptr, *cs_base, *pc;
76 /* first we save global registers */
83 /* we also save i7 because longjmp may not restore it */
84 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
87 #if defined(TARGET_I386)
90 EAX = env->regs[R_EAX];
94 ECX = env->regs[R_ECX];
98 EDX = env->regs[R_EDX];
102 EBX = env->regs[R_EBX];
106 ESP = env->regs[R_ESP];
110 EBP = env->regs[R_EBP];
114 ESI = env->regs[R_ESI];
118 EDI = env->regs[R_EDI];
121 /* put eflags in CPU temporary format */
122 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
123 DF = 1 - (2 * ((env->eflags >> 10) & 1));
124 CC_OP = CC_OP_EFLAGS;
125 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
126 #elif defined(TARGET_ARM)
130 env->CF = (psr >> 29) & 1;
131 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
132 env->VF = (psr << 3) & 0x80000000;
133 env->cpsr = psr & ~0xf0000000;
135 #elif defined(TARGET_SPARC)
136 #elif defined(TARGET_PPC)
138 #error unsupported target CPU
140 env->exception_index = -1;
142 /* prepare setjmp context for exception handling */
144 if (setjmp(env->jmp_env) == 0) {
145 env->current_tb = NULL;
146 /* if an exception is pending, we execute it here */
147 if (env->exception_index >= 0) {
148 if (env->exception_index >= EXCP_INTERRUPT) {
149 /* exit request from the cpu execution loop */
150 ret = env->exception_index;
152 } else if (env->user_mode_only) {
153 /* if user mode only, we simulate a fake exception
154 which will be hanlded outside the cpu execution
156 #if defined(TARGET_I386)
157 do_interrupt_user(env->exception_index,
158 env->exception_is_int,
160 env->exception_next_eip);
162 ret = env->exception_index;
165 #if defined(TARGET_I386)
166 /* simulate a real cpu exception. On i386, it can
167 trigger new exceptions, but we do not handle
168 double or triple faults yet. */
169 do_interrupt(env->exception_index,
170 env->exception_is_int,
172 env->exception_next_eip, 0);
173 #elif defined(TARGET_PPC)
177 env->exception_index = -1;
179 T0 = 0; /* force lookup of first TB */
182 /* g1 can be modified by some libc? functions */
185 interrupt_request = env->interrupt_request;
186 if (__builtin_expect(interrupt_request, 0)) {
187 #if defined(TARGET_I386)
188 /* if hardware interrupt pending, we execute it */
189 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
190 (env->eflags & IF_MASK) &&
191 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
193 intno = cpu_x86_get_pic_interrupt(env);
195 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
197 do_interrupt(intno, 0, 0, 0, 1);
198 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
199 /* ensure that no TB jump will be modified as
200 the program flow was changed */
207 #elif defined(TARGET_PPC)
208 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
209 do_queue_exception(EXCP_EXTERNAL);
210 if (check_exception_state(env))
212 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
215 if (interrupt_request & CPU_INTERRUPT_EXIT) {
216 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
217 env->exception_index = EXCP_INTERRUPT;
223 #if defined(TARGET_I386)
224 /* restore flags in standard format */
225 env->regs[R_EAX] = EAX;
226 env->regs[R_EBX] = EBX;
227 env->regs[R_ECX] = ECX;
228 env->regs[R_EDX] = EDX;
229 env->regs[R_ESI] = ESI;
230 env->regs[R_EDI] = EDI;
231 env->regs[R_EBP] = EBP;
232 env->regs[R_ESP] = ESP;
233 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
234 cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
235 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
236 #elif defined(TARGET_ARM)
237 env->cpsr = compute_cpsr();
238 cpu_arm_dump_state(env, logfile, 0);
239 env->cpsr &= ~0xf0000000;
240 #elif defined(TARGET_SPARC)
241 cpu_sparc_dump_state (env, logfile, 0);
242 #elif defined(TARGET_PPC)
243 cpu_ppc_dump_state(env, logfile, 0);
245 #error unsupported target CPU
249 /* we record a subset of the CPU state. It will
250 always be the same before a given translated block
252 #if defined(TARGET_I386)
254 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
255 cs_base = env->segs[R_CS].base;
256 pc = cs_base + env->eip;
257 #elif defined(TARGET_ARM)
260 pc = (uint8_t *)env->regs[15];
261 #elif defined(TARGET_SPARC)
263 cs_base = (uint8_t *)env->npc;
264 pc = (uint8_t *) env->pc;
265 #elif defined(TARGET_PPC)
268 pc = (uint8_t *)env->nip;
270 #error unsupported CPU
272 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
275 TranslationBlock **ptb1;
277 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
282 tb_invalidated_flag = 0;
284 /* find translated block using physical mappings */
285 phys_pc = get_phys_addr_code(env, (unsigned long)pc);
286 phys_page1 = phys_pc & TARGET_PAGE_MASK;
288 h = tb_phys_hash_func(phys_pc);
289 ptb1 = &tb_phys_hash[h];
294 if (tb->pc == (unsigned long)pc &&
295 tb->page_addr[0] == phys_page1 &&
296 tb->cs_base == (unsigned long)cs_base &&
297 tb->flags == flags) {
298 /* check next page if needed */
299 if (tb->page_addr[1] != -1) {
300 virt_page2 = ((unsigned long)pc & TARGET_PAGE_MASK) +
302 phys_page2 = get_phys_addr_code(env, virt_page2);
303 if (tb->page_addr[1] == phys_page2)
309 ptb1 = &tb->phys_hash_next;
312 /* if no translated code available, then translate it now */
313 tb = tb_alloc((unsigned long)pc);
315 /* flush must be done */
317 /* cannot fail at this point */
318 tb = tb_alloc((unsigned long)pc);
319 /* don't forget to invalidate previous TB info */
320 ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
323 tc_ptr = code_gen_ptr;
325 tb->cs_base = (unsigned long)cs_base;
327 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
328 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
330 /* check next page if needed */
331 virt_page2 = ((unsigned long)pc + tb->size - 1) & TARGET_PAGE_MASK;
333 if (((unsigned long)pc & TARGET_PAGE_MASK) != virt_page2) {
334 phys_page2 = get_phys_addr_code(env, virt_page2);
336 tb_link_phys(tb, phys_pc, phys_page2);
339 if (tb_invalidated_flag) {
340 /* as some TB could have been invalidated because
341 of memory exceptions while generating the code, we
342 must recompute the hash index here */
343 ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
345 ptb = &(*ptb)->hash_next;
348 /* we add the TB in the virtual pc hash table */
350 tb->hash_next = NULL;
352 spin_unlock(&tb_lock);
356 fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
357 (long)tb->tc_ptr, (long)tb->pc,
358 lookup_symbol((void *)tb->pc));
364 /* see if we can patch the calling TB. */
367 tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
368 spin_unlock(&tb_lock);
371 env->current_tb = tb;
372 /* execute the generated code */
373 gen_func = (void *)tc_ptr;
374 #if defined(__sparc__)
375 __asm__ __volatile__("call %0\n\t"
379 : "i0", "i1", "i2", "i3", "i4", "i5");
380 #elif defined(__arm__)
381 asm volatile ("mov pc, %0\n\t"
382 ".global exec_loop\n\t"
386 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
390 env->current_tb = NULL;
391 /* reset soft MMU for next block (it can currently
392 only be set by a memory fault) */
393 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
394 if (env->hflags & HF_SOFTMMU_MASK) {
395 env->hflags &= ~HF_SOFTMMU_MASK;
396 /* do not allow linking to another block */
406 #if defined(TARGET_I386)
407 /* restore flags in standard format */
408 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
410 /* restore global registers */
435 #elif defined(TARGET_ARM)
436 env->cpsr = compute_cpsr();
437 #elif defined(TARGET_SPARC)
438 #elif defined(TARGET_PPC)
440 #error unsupported target CPU
443 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
452 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
454 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
456 CPUX86State *saved_env;
460 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
462 cpu_x86_load_seg_cache(env, seg_reg, selector,
463 (uint8_t *)(selector << 4), 0xffff, 0);
465 load_seg(seg_reg, selector);
470 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
472 CPUX86State *saved_env;
477 helper_fsave(ptr, data32);
482 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
484 CPUX86State *saved_env;
489 helper_frstor(ptr, data32);
494 #endif /* TARGET_I386 */
506 #include <sys/ucontext.h>
508 #if defined(TARGET_I386)
510 /* 'pc' is the host PC at which the exception was raised. 'address' is
511 the effective address of the memory exception. 'is_write' is 1 if a
512 write caused the exception and otherwise 0'. 'old_set' is the
513 signal set which should be restored */
514 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
515 int is_write, sigset_t *old_set)
517 TranslationBlock *tb;
521 env = cpu_single_env; /* XXX: find a correct solution for multithread */
522 #if defined(DEBUG_SIGNAL)
523 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
524 pc, address, is_write, *(unsigned long *)old_set);
526 /* XXX: locking issue */
527 if (is_write && page_unprotect(address)) {
530 /* see if it is an MMU fault */
531 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
532 ((env->hflags & HF_CPL_MASK) == 3), 0);
534 return 0; /* not an MMU fault */
536 return 1; /* the MMU fault was handled without causing real CPU fault */
537 /* now we have a real cpu fault */
540 /* the PC is inside the translated code. It means that we have
541 a virtual CPU fault */
542 cpu_restore_state(tb, env, pc);
546 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
547 env->eip, env->cr[2], env->error_code);
549 /* we restore the process signal mask as the sigreturn should
550 do it (XXX: use sigsetjmp) */
551 sigprocmask(SIG_SETMASK, old_set, NULL);
552 raise_exception_err(EXCP0E_PAGE, env->error_code);
554 /* activate soft MMU for this block */
555 env->hflags |= HF_SOFTMMU_MASK;
556 sigprocmask(SIG_SETMASK, old_set, NULL);
559 /* never comes here */
563 #elif defined(TARGET_ARM)
564 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
565 int is_write, sigset_t *old_set)
570 #elif defined(TARGET_SPARC)
571 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
572 int is_write, sigset_t *old_set)
574 /* XXX: locking issue */
575 if (is_write && page_unprotect(address)) {
580 #elif defined (TARGET_PPC)
581 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
582 int is_write, sigset_t *old_set)
584 TranslationBlock *tb;
589 env = cpu_single_env; /* XXX: find a correct solution for multithread */
591 #if defined(DEBUG_SIGNAL)
592 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
593 pc, address, is_write, *(unsigned long *)old_set);
595 /* XXX: locking issue */
596 if (is_write && page_unprotect(address)) {
600 /* see if it is an MMU fault */
601 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
603 return 0; /* not an MMU fault */
605 return 1; /* the MMU fault was handled without causing real CPU fault */
607 /* now we have a real cpu fault */
610 /* the PC is inside the translated code. It means that we have
611 a virtual CPU fault */
612 cpu_restore_state(tb, env, pc);
616 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
617 env->nip, env->error_code, tb);
619 /* we restore the process signal mask as the sigreturn should
620 do it (XXX: use sigsetjmp) */
621 sigprocmask(SIG_SETMASK, old_set, NULL);
622 do_queue_exception_err(env->exception_index, env->error_code);
624 /* activate soft MMU for this block */
625 sigprocmask(SIG_SETMASK, old_set, NULL);
628 /* never comes here */
632 #error unsupported target CPU
635 #if defined(__i386__)
637 int cpu_signal_handler(int host_signum, struct siginfo *info,
640 struct ucontext *uc = puc;
647 #define REG_TRAPNO TRAPNO
649 pc = uc->uc_mcontext.gregs[REG_EIP];
650 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
651 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
652 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
656 #elif defined(__powerpc)
658 int cpu_signal_handler(int host_signum, struct siginfo *info,
661 struct ucontext *uc = puc;
662 struct pt_regs *regs = uc->uc_mcontext.regs;
670 if (regs->dsisr & 0x00800000)
673 if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
676 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
677 is_write, &uc->uc_sigmask);
680 #elif defined(__alpha__)
682 int cpu_signal_handler(int host_signum, struct siginfo *info,
685 struct ucontext *uc = puc;
686 uint32_t *pc = uc->uc_mcontext.sc_pc;
690 /* XXX: need kernel patch to get write flag faster */
691 switch (insn >> 26) {
706 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
707 is_write, &uc->uc_sigmask);
709 #elif defined(__sparc__)
711 int cpu_signal_handler(int host_signum, struct siginfo *info,
714 uint32_t *regs = (uint32_t *)(info + 1);
715 void *sigmask = (regs + 20);
720 /* XXX: is there a standard glibc define ? */
722 /* XXX: need kernel patch to get write flag faster */
724 insn = *(uint32_t *)pc;
725 if ((insn >> 30) == 3) {
726 switch((insn >> 19) & 0x3f) {
738 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
742 #elif defined(__arm__)
744 int cpu_signal_handler(int host_signum, struct siginfo *info,
747 struct ucontext *uc = puc;
751 pc = uc->uc_mcontext.gregs[R15];
752 /* XXX: compute is_write */
754 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
759 #elif defined(__mc68000)
761 int cpu_signal_handler(int host_signum, struct siginfo *info,
764 struct ucontext *uc = puc;
768 pc = uc->uc_mcontext.gregs[16];
769 /* XXX: compute is_write */
771 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
778 #error host CPU specific signal handler needed