git.maemo.org Git - h-e-n/blob - drivers/net/wireless/wl12xx/wl1251_boot.c

   1 /*
   2  * This file is part of wl1251
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Kalle Valo <kalle.valo@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/gpio.h>
  25
  26 #include "wl1251_reg.h"
  27 #include "wl1251_boot.h"
  28 #include "wl1251_spi.h"
  29 #include "wl1251_event.h"
  30 #include "wl1251_acx.h"
  31
  32 static void wl1251_boot_enable_interrupts(struct wl1251 *wl)
  33 {
  34         enable_irq(wl->irq);
  35 }
  36
  37 void wl1251_boot_target_enable_interrupts(struct wl1251 *wl)
  38 {
  39         wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask));
  40         wl1251_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
  41 }
  42
  43 int wl1251_boot_soft_reset(struct wl1251 *wl)
  44 {
  45         unsigned long timeout;
  46         u32 boot_data;
  47
  48         /* perform soft reset */
  49         wl1251_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
  50
  51         /* SOFT_RESET is self clearing */
  52         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
  53         while (1) {
  54                 boot_data = wl1251_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
  55                 wl1251_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
  56                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
  57                         break;
  58
  59                 if (time_after(jiffies, timeout)) {
  60                         /* 1.2 check pWhalBus->uSelfClearTime if the
  61                          * timeout was reached */
  62                         wl1251_error("soft reset timeout");
  63                         return -1;
  64                 }
  65
  66                 udelay(SOFT_RESET_STALL_TIME);
  67         }
  68
  69         /* disable Rx/Tx */
  70         wl1251_reg_write32(wl, ENABLE, 0x0);
  71
  72         /* disable auto calibration on start*/
  73         wl1251_reg_write32(wl, SPARE_A2, 0xffff);
  74
  75         return 0;
  76 }
  77
  78 int wl1251_boot_init_seq(struct wl1251 *wl)
  79 {
  80         u32 scr_pad6, init_data, tmp, elp_cmd, ref_freq;
  81
  82         /*
  83          * col #1: INTEGER_DIVIDER
  84          * col #2: FRACTIONAL_DIVIDER
  85          * col #3: ATTN_BB
  86          * col #4: ALPHA_BB
  87          * col #5: STOP_TIME_BB
  88          * col #6: BB_PLL_LOOP_FILTER
  89          */
  90         static const u32 LUT[REF_FREQ_NUM][LUT_PARAM_NUM] = {
  91
  92                 {   83, 87381,  0xB, 5, 0xF00,  3}, /* REF_FREQ_19_2*/
  93                 {   61, 141154, 0xB, 5, 0x1450, 2}, /* REF_FREQ_26_0*/
  94                 {   41, 174763, 0xC, 6, 0x2D00, 1}, /* REF_FREQ_38_4*/
  95                 {   40, 0,      0xC, 6, 0x2EE0, 1}, /* REF_FREQ_40_0*/
  96                 {   47, 162280, 0xC, 6, 0x2760, 1}  /* REF_FREQ_33_6        */
  97         };
  98
  99         /* read NVS params */
 100         scr_pad6 = wl1251_reg_read32(wl, SCR_PAD6);
 101         wl1251_debug(DEBUG_BOOT, "scr_pad6 0x%x", scr_pad6);
 102
 103         /* read ELP_CMD */
 104         elp_cmd = wl1251_reg_read32(wl, ELP_CMD);
 105         wl1251_debug(DEBUG_BOOT, "elp_cmd 0x%x", elp_cmd);
 106
 107         /* set the BB calibration time to be 300 usec (PLL_CAL_TIME) */
 108         ref_freq = scr_pad6 & 0x000000FF;
 109         wl1251_debug(DEBUG_BOOT, "ref_freq 0x%x", ref_freq);
 110
 111         wl1251_reg_write32(wl, PLL_CAL_TIME, 0x9);
 112
 113         /*
 114          * PG 1.2: set the clock buffer time to be 210 usec (CLK_BUF_TIME)
 115          */
 116         wl1251_reg_write32(wl, CLK_BUF_TIME, 0x6);
 117
 118         /*
 119          * set the clock detect feature to work in the restart wu procedure
 120          * (ELP_CFG_MODE[14]) and Select the clock source type
 121          * (ELP_CFG_MODE[13:12])
 122          */
 123         tmp = ((scr_pad6 & 0x0000FF00) << 4) | 0x00004000;
 124         wl1251_reg_write32(wl, ELP_CFG_MODE, tmp);
 125
 126         /* PG 1.2: enable the BB PLL fix. Enable the PLL_LIMP_CLK_EN_CMD */
 127         elp_cmd |= 0x00000040;
 128         wl1251_reg_write32(wl, ELP_CMD, elp_cmd);
 129
 130         /* PG 1.2: Set the BB PLL stable time to be 1000usec
 131          * (PLL_STABLE_TIME) */
 132         wl1251_reg_write32(wl, CFG_PLL_SYNC_CNT, 0x20);
 133
 134         /* PG 1.2: read clock request time */
 135         init_data = wl1251_reg_read32(wl, CLK_REQ_TIME);
 136
 137         /*
 138          * PG 1.2: set the clock request time to be ref_clk_settling_time -
 139          * 1ms = 4ms
 140          */
 141         if (init_data > 0x21)
 142                 tmp = init_data - 0x21;
 143         else
 144                 tmp = 0;
 145         wl1251_reg_write32(wl, CLK_REQ_TIME, tmp);
 146
 147         /* set BB PLL configurations in RF AFE */
 148         wl1251_reg_write32(wl, 0x003058cc, 0x4B5);
 149
 150         /* set RF_AFE_REG_5 */
 151         wl1251_reg_write32(wl, 0x003058d4, 0x50);
 152
 153         /* set RF_AFE_CTRL_REG_2 */
 154         wl1251_reg_write32(wl, 0x00305948, 0x11c001);
 155
 156         /*
 157          * change RF PLL and BB PLL divider for VCO clock and adjust VCO
 158          * bais current(RF_AFE_REG_13)
 159          */
 160         wl1251_reg_write32(wl, 0x003058f4, 0x1e);
 161
 162         /* set BB PLL configurations */
 163         tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000;
 164         wl1251_reg_write32(wl, 0x00305840, tmp);
 165
 166         /* set fractional divider according to Appendix C-BB PLL
 167          * Calculations
 168          */
 169         tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER];
 170         wl1251_reg_write32(wl, 0x00305844, tmp);
 171
 172         /* set the initial data for the sigma delta */
 173         wl1251_reg_write32(wl, 0x00305848, 0x3039);
 174
 175         /*
 176          * set the accumulator attenuation value, calibration loop1
 177          * (alpha), calibration loop2 (beta), calibration loop3 (gamma) and
 178          * the VCO gain
 179          */
 180         tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) |
 181                 (LUT[ref_freq][LUT_PARAM_ALPHA_BB] << 12) | 0x1;
 182         wl1251_reg_write32(wl, 0x00305854, tmp);
 183
 184         /*
 185          * set the calibration stop time after holdoff time expires and set
 186          * settling time HOLD_OFF_TIME_BB
 187          */
 188         tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] | 0x000A0000;
 189         wl1251_reg_write32(wl, 0x00305858, tmp);
 190
 191         /*
 192          * set BB PLL Loop filter capacitor3- BB_C3[2:0] and set BB PLL
 193          * constant leakage current to linearize PFD to 0uA -
 194          * BB_ILOOPF[7:3]
 195          */
 196         tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] | 0x00000030;
 197         wl1251_reg_write32(wl, 0x003058f8, tmp);
 198
 199         /*
 200          * set regulator output voltage for n divider to
 201          * 1.35-BB_REFDIV[1:0], set charge pump current- BB_CPGAIN[4:2],
 202          * set BB PLL Loop filter capacitor2- BB_C2[7:5], set gain of BB
 203          * PLL auto-call to normal mode- BB_CALGAIN_3DB[8]
 204          */
 205         wl1251_reg_write32(wl, 0x003058f0, 0x29);
 206
 207         /* enable restart wakeup sequence (ELP_CMD[0]) */
 208         wl1251_reg_write32(wl, ELP_CMD, elp_cmd | 0x1);
 209
 210         /* restart sequence completed */
 211         udelay(2000);
 212
 213         return 0;
 214 }
 215
 216 static void wl1251_boot_set_ecpu_ctrl(struct wl1251 *wl, u32 flag)
 217 {
 218         u32 cpu_ctrl;
 219
 220         /* 10.5.0 run the firmware (I) */
 221         cpu_ctrl = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
 222
 223         /* 10.5.1 run the firmware (II) */
 224         cpu_ctrl &= ~flag;
 225         wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
 226 }
 227
 228 int wl1251_boot_run_firmware(struct wl1251 *wl)
 229 {
 230         int loop, ret;
 231         u32 chip_id, interrupt;
 232
 233         wl1251_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
 234
 235         chip_id = wl1251_reg_read32(wl, CHIP_ID_B);
 236
 237         wl1251_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
 238
 239         if (chip_id != wl->chip_id) {
 240                 wl1251_error("chip id doesn't match after firmware boot");
 241                 return -EIO;
 242         }
 243
 244         /* wait for init to complete */
 245         loop = 0;
 246         while (loop++ < INIT_LOOP) {
 247                 udelay(INIT_LOOP_DELAY);
 248                 interrupt = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
 249
 250                 if (interrupt == 0xffffffff) {
 251                         wl1251_error("error reading hardware complete "
 252                                      "init indication");
 253                         return -EIO;
 254                 }
 255                 /* check that ACX_INTR_INIT_COMPLETE is enabled */
 256                 else if (interrupt & WL1251_ACX_INTR_INIT_COMPLETE) {
 257                         wl1251_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
 258                                            WL1251_ACX_INTR_INIT_COMPLETE);
 259                         break;
 260                 }
 261         }
 262
 263         if (loop >= INIT_LOOP) {
 264                 wl1251_error("timeout waiting for the hardware to "
 265                              "complete initialization");
 266                 return -EIO;
 267         }
 268
 269         /* get hardware config command mail box */
 270         wl->cmd_box_addr = wl1251_reg_read32(wl, REG_COMMAND_MAILBOX_PTR);
 271
 272         /* get hardware config event mail box */
 273         wl->event_box_addr = wl1251_reg_read32(wl, REG_EVENT_MAILBOX_PTR);
 274
 275         /* set the working partition to its "running" mode offset */
 276         wl1251_set_partition(wl, WL1251_PART_WORK_MEM_START,
 277                              WL1251_PART_WORK_MEM_SIZE,
 278                              WL1251_PART_WORK_REG_START,
 279                              WL1251_PART_WORK_REG_SIZE);
 280
 281         wl1251_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
 282                      wl->cmd_box_addr, wl->event_box_addr);
 283
 284         wl1251_acx_fw_version(wl, wl->fw_ver, sizeof(wl->fw_ver));
 285
 286         /*
 287          * in case of full asynchronous mode the firmware event must be
 288          * ready to receive event from the command mailbox
 289          */
 290
 291         /* enable gpio interrupts */
 292         wl1251_boot_enable_interrupts(wl);
 293
 294         /* Enable target's interrupts */
 295         wl->intr_mask = WL1251_ACX_INTR_RX0_DATA |
 296                 WL1251_ACX_INTR_RX1_DATA |
 297                 WL1251_ACX_INTR_TX_RESULT |
 298                 WL1251_ACX_INTR_EVENT_A |
 299                 WL1251_ACX_INTR_EVENT_B |
 300                 WL1251_ACX_INTR_INIT_COMPLETE;
 301         wl1251_boot_target_enable_interrupts(wl);
 302
 303         wl->event_mask = SCAN_COMPLETE_EVENT_ID | BSS_LOSE_EVENT_ID |
 304                 SYNCHRONIZATION_TIMEOUT_EVENT_ID |
 305                 ROAMING_TRIGGER_LOW_RSSI_EVENT_ID |
 306                 ROAMING_TRIGGER_REGAINED_RSSI_EVENT_ID |
 307                 REGAINED_BSS_EVENT_ID | BT_PTA_SENSE_EVENT_ID |
 308                 BT_PTA_PREDICTION_EVENT_ID | PS_REPORT_EVENT_ID;
 309
 310         ret = wl1251_event_unmask(wl);
 311         if (ret < 0) {
 312                 wl1251_error("EVENT mask setting failed");
 313                 return ret;
 314         }
 315
 316         wl1251_event_mbox_config(wl);
 317
 318         /* firmware startup completed */
 319         return 0;
 320 }
 321
 322 static int wl1251_boot_upload_firmware(struct wl1251 *wl)
 323 {
 324         int addr, chunk_num, partition_limit;
 325         size_t fw_data_len, len;
 326         u8 *p, *buf;
 327
 328         /* whal_FwCtrl_LoadFwImageSm() */
 329
 330         wl1251_debug(DEBUG_BOOT, "chip id before fw upload: 0x%x",
 331                      wl1251_reg_read32(wl, CHIP_ID_B));
 332
 333         /* 10.0 check firmware length and set partition */
 334         fw_data_len =  (wl->fw[4] << 24) | (wl->fw[5] << 16) |
 335                 (wl->fw[6] << 8) | (wl->fw[7]);
 336
 337         wl1251_debug(DEBUG_BOOT, "fw_data_len %zu chunk_size %d", fw_data_len,
 338                 CHUNK_SIZE);
 339
 340         if ((fw_data_len % 4) != 0) {
 341                 wl1251_error("firmware length not multiple of four");
 342                 return -EIO;
 343         }
 344
 345         buf = kmalloc(CHUNK_SIZE, GFP_KERNEL);
 346         if (!buf) {
 347                 wl1251_error("allocation for firmware upload chunk failed");
 348                 return -ENOMEM;
 349         }
 350
 351         wl1251_set_partition(wl, WL1251_PART_DOWN_MEM_START,
 352                              WL1251_PART_DOWN_MEM_SIZE,
 353                              WL1251_PART_DOWN_REG_START,
 354                              WL1251_PART_DOWN_REG_SIZE);
 355
 356         /* 10.1 set partition limit and chunk num */
 357         chunk_num = 0;
 358         partition_limit = WL1251_PART_DOWN_MEM_SIZE;
 359
 360         while (chunk_num < fw_data_len / CHUNK_SIZE) {
 361                 /* 10.2 update partition, if needed */
 362                 addr = WL1251_PART_DOWN_MEM_START +
 363                         (chunk_num + 2) * CHUNK_SIZE;
 364                 if (addr > partition_limit) {
 365                         addr = WL1251_PART_DOWN_MEM_START +
 366                                 chunk_num * CHUNK_SIZE;
 367                         partition_limit = chunk_num * CHUNK_SIZE +
 368                                 WL1251_PART_DOWN_MEM_SIZE;
 369                         wl1251_set_partition(wl,
 370                                              addr,
 371                                              WL1251_PART_DOWN_MEM_SIZE,
 372                                              WL1251_PART_DOWN_REG_START,
 373                                              WL1251_PART_DOWN_REG_SIZE);
 374                 }
 375
 376                 /* 10.3 upload the chunk */
 377                 addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
 378                 p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
 379                 wl1251_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
 380                              p, addr);
 381
 382                 /* need to copy the chunk for dma */
 383                 len = CHUNK_SIZE;
 384                 memcpy(buf, p, len);
 385                 wl1251_spi_mem_write(wl, addr, buf, len);
 386
 387                 chunk_num++;
 388         }
 389
 390         /* 10.4 upload the last chunk */
 391         addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
 392         p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
 393
 394         /* need to copy the chunk for dma */
 395         len = fw_data_len % CHUNK_SIZE;
 396         memcpy(buf, p, len);
 397
 398         wl1251_debug(DEBUG_BOOT, "uploading fw last chunk (%zu B) 0x%p to 0x%x",
 399                      len, p, addr);
 400         wl1251_spi_mem_write(wl, addr, buf, len);
 401
 402         kfree(buf);
 403
 404         return 0;
 405 }
 406
 407 static int wl1251_boot_upload_nvs(struct wl1251 *wl)
 408 {
 409         size_t nvs_len, nvs_bytes_written, burst_len;
 410         int nvs_start, i;
 411         u32 dest_addr, val;
 412         u8 *nvs_ptr, *nvs;
 413
 414         nvs = wl->nvs;
 415         if (nvs == NULL)
 416                 return -ENODEV;
 417
 418         nvs_ptr = nvs;
 419
 420         nvs_len = wl->nvs_len;
 421         nvs_start = wl->fw_len;
 422
 423         /*
 424          * Layout before the actual NVS tables:
 425          * 1 byte : burst length.
 426          * 2 bytes: destination address.
 427          * n bytes: data to burst copy.
 428          *
 429          * This is ended by a 0 length, then the NVS tables.
 430          */
 431
 432         while (nvs_ptr[0]) {
 433                 burst_len = nvs_ptr[0];
 434                 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
 435
 436                 /* We move our pointer to the data */
 437                 nvs_ptr += 3;
 438
 439                 for (i = 0; i < burst_len; i++) {
 440                         val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
 441                                | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
 442
 443                         wl1251_debug(DEBUG_BOOT,
 444                                      "nvs burst write 0x%x: 0x%x",
 445                                      dest_addr, val);
 446                         wl1251_mem_write32(wl, dest_addr, val);
 447
 448                         nvs_ptr += 4;
 449                         dest_addr += 4;
 450                 }
 451         }
 452
 453         /*
 454          * We've reached the first zero length, the first NVS table
 455          * is 7 bytes further.
 456          */
 457         nvs_ptr += 7;
 458         nvs_len -= nvs_ptr - nvs;
 459         nvs_len = ALIGN(nvs_len, 4);
 460
 461         /* Now we must set the partition correctly */
 462         wl1251_set_partition(wl, nvs_start,
 463                              WL1251_PART_DOWN_MEM_SIZE,
 464                              WL1251_PART_DOWN_REG_START,
 465                              WL1251_PART_DOWN_REG_SIZE);
 466
 467         /* And finally we upload the NVS tables */
 468         nvs_bytes_written = 0;
 469         while (nvs_bytes_written < nvs_len) {
 470                 val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
 471                        | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
 472
 473                 val = cpu_to_le32(val);
 474
 475                 wl1251_debug(DEBUG_BOOT,
 476                              "nvs write table 0x%x: 0x%x",
 477                              nvs_start, val);
 478                 wl1251_mem_write32(wl, nvs_start, val);
 479
 480                 nvs_ptr += 4;
 481                 nvs_bytes_written += 4;
 482                 nvs_start += 4;
 483         }
 484
 485         return 0;
 486 }
 487
 488 int wl1251_boot(struct wl1251 *wl)
 489 {
 490         int ret = 0, minor_minor_e2_ver;
 491         u32 tmp, boot_data;
 492
 493         ret = wl1251_boot_soft_reset(wl);
 494         if (ret < 0)
 495                 goto out;
 496
 497         /* 2. start processing NVS file */
 498         ret = wl1251_boot_upload_nvs(wl);
 499         if (ret < 0)
 500                 goto out;
 501
 502         /* write firmware's last address (ie. it's length) to
 503          * ACX_EEPROMLESS_IND_REG */
 504         wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len);
 505
 506         /* 6. read the EEPROM parameters */
 507         tmp = wl1251_reg_read32(wl, SCR_PAD2);
 508
 509         /* 7. read bootdata */
 510         wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8;
 511         wl->boot_attr.major = (tmp & 0x00FF0000) >> 16;
 512         tmp = wl1251_reg_read32(wl, SCR_PAD3);
 513
 514         /* 8. check bootdata and call restart sequence */
 515         wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16;
 516         minor_minor_e2_ver = (tmp & 0xFF000000) >> 24;
 517
 518         wl1251_debug(DEBUG_BOOT, "radioType 0x%x majorE2Ver 0x%x "
 519                      "minorE2Ver 0x%x minor_minor_e2_ver 0x%x",
 520                      wl->boot_attr.radio_type, wl->boot_attr.major,
 521                      wl->boot_attr.minor, minor_minor_e2_ver);
 522
 523         ret = wl1251_boot_init_seq(wl);
 524         if (ret < 0)
 525                 goto out;
 526
 527         /* 9. NVS processing done */
 528         boot_data = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
 529
 530         wl1251_debug(DEBUG_BOOT, "halt boot_data 0x%x", boot_data);
 531
 532         /* 10. check that ECPU_CONTROL_HALT bits are set in
 533          * pWhalBus->uBootData and start uploading firmware
 534          */
 535         if ((boot_data & ECPU_CONTROL_HALT) == 0) {
 536                 wl1251_error("boot failed, ECPU_CONTROL_HALT not set");
 537                 ret = -EIO;
 538                 goto out;
 539         }
 540
 541         ret = wl1251_boot_upload_firmware(wl);
 542         if (ret < 0)
 543                 goto out;
 544
 545         /* 10.5 start firmware */
 546         ret = wl1251_boot_run_firmware(wl);
 547         if (ret < 0)
 548                 goto out;
 549
 550 out:
 551         return ret;
 552 }