4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #ifdef CONFIG_USER_ONLY
35 #include "qemu_socket.h"
37 /* XXX: these constants may be independent of the host ones even for Unix */
56 typedef struct GDBState {
57 CPUState *env; /* current CPU */
58 enum RSState state; /* parsing state */
62 char last_packet[4100];
64 #ifdef CONFIG_USER_ONLY
72 #ifdef CONFIG_USER_ONLY
73 /* XXX: This is not thread safe. Do we care? */
74 static int gdbserver_fd = -1;
76 /* XXX: remove this hack. */
77 static GDBState gdbserver_state;
79 static int get_char(GDBState *s)
85 ret = recv(s->fd, &ch, 1, 0);
87 if (errno != EINTR && errno != EAGAIN)
89 } else if (ret == 0) {
99 static void put_buffer(GDBState *s, const uint8_t *buf, int len)
101 #ifdef CONFIG_USER_ONLY
105 ret = send(s->fd, buf, len, 0);
107 if (errno != EINTR && errno != EAGAIN)
115 qemu_chr_write(s->chr, buf, len);
119 static inline int fromhex(int v)
121 if (v >= '0' && v <= '9')
123 else if (v >= 'A' && v <= 'F')
125 else if (v >= 'a' && v <= 'f')
131 static inline int tohex(int v)
139 static void memtohex(char *buf, const uint8_t *mem, int len)
144 for(i = 0; i < len; i++) {
146 *q++ = tohex(c >> 4);
147 *q++ = tohex(c & 0xf);
152 static void hextomem(uint8_t *mem, const char *buf, int len)
156 for(i = 0; i < len; i++) {
157 mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
162 /* return -1 if error, 0 if OK */
163 static int put_packet(GDBState *s, char *buf)
169 printf("reply='%s'\n", buf);
179 for(i = 0; i < len; i++) {
183 *(p++) = tohex((csum >> 4) & 0xf);
184 *(p++) = tohex((csum) & 0xf);
186 s->last_packet_len = p - s->last_packet;
187 put_buffer(s, s->last_packet, s->last_packet_len);
189 #ifdef CONFIG_USER_ONLY
202 #if defined(TARGET_I386)
204 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
206 uint32_t *registers = (uint32_t *)mem_buf;
209 for(i = 0; i < 8; i++) {
210 registers[i] = env->regs[i];
212 registers[8] = env->eip;
213 registers[9] = env->eflags;
214 registers[10] = env->segs[R_CS].selector;
215 registers[11] = env->segs[R_SS].selector;
216 registers[12] = env->segs[R_DS].selector;
217 registers[13] = env->segs[R_ES].selector;
218 registers[14] = env->segs[R_FS].selector;
219 registers[15] = env->segs[R_GS].selector;
220 /* XXX: convert floats */
221 for(i = 0; i < 8; i++) {
222 memcpy(mem_buf + 16 * 4 + i * 10, &env->fpregs[i], 10);
224 registers[36] = env->fpuc;
225 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
226 registers[37] = fpus;
227 registers[38] = 0; /* XXX: convert tags */
228 registers[39] = 0; /* fiseg */
229 registers[40] = 0; /* fioff */
230 registers[41] = 0; /* foseg */
231 registers[42] = 0; /* fooff */
232 registers[43] = 0; /* fop */
234 for(i = 0; i < 16; i++)
235 tswapls(®isters[i]);
236 for(i = 36; i < 44; i++)
237 tswapls(®isters[i]);
241 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
243 uint32_t *registers = (uint32_t *)mem_buf;
246 for(i = 0; i < 8; i++) {
247 env->regs[i] = tswapl(registers[i]);
249 env->eip = tswapl(registers[8]);
250 env->eflags = tswapl(registers[9]);
251 #if defined(CONFIG_USER_ONLY)
252 #define LOAD_SEG(index, sreg)\
253 if (tswapl(registers[index]) != env->segs[sreg].selector)\
254 cpu_x86_load_seg(env, sreg, tswapl(registers[index]));
264 #elif defined (TARGET_PPC)
265 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
267 uint32_t *registers = (uint32_t *)mem_buf, tmp;
271 for(i = 0; i < 32; i++) {
272 registers[i] = tswapl(env->gpr[i]);
275 for (i = 0; i < 32; i++) {
276 registers[(i * 2) + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
277 registers[(i * 2) + 33] = tswapl(*((uint32_t *)&env->fpr[i] + 1));
279 /* nip, msr, ccr, lnk, ctr, xer, mq */
280 registers[96] = tswapl(env->nip);
281 registers[97] = tswapl(do_load_msr(env));
283 for (i = 0; i < 8; i++)
284 tmp |= env->crf[i] << (32 - ((i + 1) * 4));
285 registers[98] = tswapl(tmp);
286 registers[99] = tswapl(env->lr);
287 registers[100] = tswapl(env->ctr);
288 registers[101] = tswapl(do_load_xer(env));
294 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
296 uint32_t *registers = (uint32_t *)mem_buf;
300 for (i = 0; i < 32; i++) {
301 env->gpr[i] = tswapl(registers[i]);
304 for (i = 0; i < 32; i++) {
305 *((uint32_t *)&env->fpr[i]) = tswapl(registers[(i * 2) + 32]);
306 *((uint32_t *)&env->fpr[i] + 1) = tswapl(registers[(i * 2) + 33]);
308 /* nip, msr, ccr, lnk, ctr, xer, mq */
309 env->nip = tswapl(registers[96]);
310 do_store_msr(env, tswapl(registers[97]));
311 registers[98] = tswapl(registers[98]);
312 for (i = 0; i < 8; i++)
313 env->crf[i] = (registers[98] >> (32 - ((i + 1) * 4))) & 0xF;
314 env->lr = tswapl(registers[99]);
315 env->ctr = tswapl(registers[100]);
316 do_store_xer(env, tswapl(registers[101]));
318 #elif defined (TARGET_SPARC)
319 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
321 target_ulong *registers = (target_ulong *)mem_buf;
325 for(i = 0; i < 8; i++) {
326 registers[i] = tswapl(env->gregs[i]);
328 /* fill in register window */
329 for(i = 0; i < 24; i++) {
330 registers[i + 8] = tswapl(env->regwptr[i]);
332 #ifndef TARGET_SPARC64
334 for (i = 0; i < 32; i++) {
335 registers[i + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
337 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
338 registers[64] = tswapl(env->y);
343 registers[65] = tswapl(tmp);
345 registers[66] = tswapl(env->wim);
346 registers[67] = tswapl(env->tbr);
347 registers[68] = tswapl(env->pc);
348 registers[69] = tswapl(env->npc);
349 registers[70] = tswapl(env->fsr);
350 registers[71] = 0; /* csr */
352 return 73 * sizeof(target_ulong);
355 for (i = 0; i < 64; i += 2) {
358 tmp = (uint64_t)tswap32(*((uint32_t *)&env->fpr[i])) << 32;
359 tmp |= tswap32(*((uint32_t *)&env->fpr[i + 1]));
360 registers[i/2 + 32] = tmp;
362 registers[64] = tswapl(env->pc);
363 registers[65] = tswapl(env->npc);
364 registers[66] = tswapl(env->tstate[env->tl]);
365 registers[67] = tswapl(env->fsr);
366 registers[68] = tswapl(env->fprs);
367 registers[69] = tswapl(env->y);
368 return 70 * sizeof(target_ulong);
372 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
374 target_ulong *registers = (target_ulong *)mem_buf;
378 for(i = 0; i < 7; i++) {
379 env->gregs[i] = tswapl(registers[i]);
381 /* fill in register window */
382 for(i = 0; i < 24; i++) {
383 env->regwptr[i] = tswapl(registers[i + 8]);
385 #ifndef TARGET_SPARC64
387 for (i = 0; i < 32; i++) {
388 *((uint32_t *)&env->fpr[i]) = tswapl(registers[i + 32]);
390 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
391 env->y = tswapl(registers[64]);
392 PUT_PSR(env, tswapl(registers[65]));
393 env->wim = tswapl(registers[66]);
394 env->tbr = tswapl(registers[67]);
395 env->pc = tswapl(registers[68]);
396 env->npc = tswapl(registers[69]);
397 env->fsr = tswapl(registers[70]);
399 for (i = 0; i < 64; i += 2) {
400 *((uint32_t *)&env->fpr[i]) = tswap32(registers[i/2 + 32] >> 32);
401 *((uint32_t *)&env->fpr[i + 1]) = tswap32(registers[i/2 + 32] & 0xffffffff);
403 env->pc = tswapl(registers[64]);
404 env->npc = tswapl(registers[65]);
405 env->tstate[env->tl] = tswapl(registers[66]);
406 env->fsr = tswapl(registers[67]);
407 env->fprs = tswapl(registers[68]);
408 env->y = tswapl(registers[69]);
411 #elif defined (TARGET_ARM)
412 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
418 /* 16 core integer registers (4 bytes each). */
419 for (i = 0; i < 16; i++)
421 *(uint32_t *)ptr = tswapl(env->regs[i]);
424 /* 8 FPA registers (12 bytes each), FPS (4 bytes).
425 Not yet implemented. */
426 memset (ptr, 0, 8 * 12 + 4);
428 /* CPSR (4 bytes). */
429 *(uint32_t *)ptr = tswapl (cpsr_read(env));
432 return ptr - mem_buf;
435 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
441 /* Core integer registers. */
442 for (i = 0; i < 16; i++)
444 env->regs[i] = tswapl(*(uint32_t *)ptr);
447 /* Ignore FPA regs and scr. */
449 cpsr_write (env, tswapl(*(uint32_t *)ptr), 0xffffffff);
451 #elif defined (TARGET_M68K)
452 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
460 for (i = 0; i < 8; i++) {
461 *(uint32_t *)ptr = tswapl(env->dregs[i]);
465 for (i = 0; i < 8; i++) {
466 *(uint32_t *)ptr = tswapl(env->aregs[i]);
469 *(uint32_t *)ptr = tswapl(env->sr);
471 *(uint32_t *)ptr = tswapl(env->pc);
473 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
474 ColdFire has 8-bit double precision registers. */
475 for (i = 0; i < 8; i++) {
477 *(uint32_t *)ptr = tswap32(u.l.upper);
478 *(uint32_t *)ptr = tswap32(u.l.lower);
480 /* FP control regs (not implemented). */
481 memset (ptr, 0, 3 * 4);
484 return ptr - mem_buf;
487 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
495 for (i = 0; i < 8; i++) {
496 env->dregs[i] = tswapl(*(uint32_t *)ptr);
500 for (i = 0; i < 8; i++) {
501 env->aregs[i] = tswapl(*(uint32_t *)ptr);
504 env->sr = tswapl(*(uint32_t *)ptr);
506 env->pc = tswapl(*(uint32_t *)ptr);
508 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
509 ColdFire has 8-bit double precision registers. */
510 for (i = 0; i < 8; i++) {
511 u.l.upper = tswap32(*(uint32_t *)ptr);
512 u.l.lower = tswap32(*(uint32_t *)ptr);
515 /* FP control regs (not implemented). */
518 #elif defined (TARGET_MIPS)
519 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
525 for (i = 0; i < 32; i++)
527 *(uint32_t *)ptr = tswapl(env->gpr[i]);
531 *(uint32_t *)ptr = tswapl(env->CP0_Status);
534 *(uint32_t *)ptr = tswapl(env->LO);
537 *(uint32_t *)ptr = tswapl(env->HI);
540 *(uint32_t *)ptr = tswapl(env->CP0_BadVAddr);
543 *(uint32_t *)ptr = tswapl(env->CP0_Cause);
546 *(uint32_t *)ptr = tswapl(env->PC);
550 for (i = 0; i < 32; i++)
552 *(uint32_t *)ptr = tswapl(FPR_W (env, i));
556 *(uint32_t *)ptr = tswapl(env->fcr31);
559 *(uint32_t *)ptr = tswapl(env->fcr0);
563 /* 32 FP registers, fsr, fir, fp. Not yet implemented. */
564 /* what's 'fp' mean here? */
566 return ptr - mem_buf;
569 /* convert MIPS rounding mode in FCR31 to IEEE library */
570 static unsigned int ieee_rm[] =
572 float_round_nearest_even,
577 #define RESTORE_ROUNDING_MODE \
578 set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
580 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
586 for (i = 0; i < 32; i++)
588 env->gpr[i] = tswapl(*(uint32_t *)ptr);
592 env->CP0_Status = tswapl(*(uint32_t *)ptr);
595 env->LO = tswapl(*(uint32_t *)ptr);
598 env->HI = tswapl(*(uint32_t *)ptr);
601 env->CP0_BadVAddr = tswapl(*(uint32_t *)ptr);
604 env->CP0_Cause = tswapl(*(uint32_t *)ptr);
607 env->PC = tswapl(*(uint32_t *)ptr);
611 for (i = 0; i < 32; i++)
613 FPR_W (env, i) = tswapl(*(uint32_t *)ptr);
617 env->fcr31 = tswapl(*(uint32_t *)ptr) & 0x0183FFFF;
620 env->fcr0 = tswapl(*(uint32_t *)ptr);
623 /* set rounding mode */
624 RESTORE_ROUNDING_MODE;
626 #ifndef CONFIG_SOFTFLOAT
627 /* no floating point exception for native float */
628 SET_FP_ENABLE(env->fcr31, 0);
632 #elif defined (TARGET_SH4)
633 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
635 uint32_t *ptr = (uint32_t *)mem_buf;
638 #define SAVE(x) *ptr++=tswapl(x)
639 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
640 for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
642 for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
644 for (i = 8; i < 16; i++) SAVE(env->gregs[i]);
652 SAVE (0); /* TICKS */
653 SAVE (0); /* STALLS */
654 SAVE (0); /* CYCLES */
655 SAVE (0); /* INSTS */
658 return ((uint8_t *)ptr - mem_buf);
661 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
663 uint32_t *ptr = (uint32_t *)mem_buf;
666 #define LOAD(x) (x)=*ptr++;
667 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
668 for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
670 for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
672 for (i = 8; i < 16; i++) LOAD(env->gregs[i]);
682 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
687 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
693 static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
696 int ch, reg_size, type;
698 uint8_t mem_buf[2000];
700 target_ulong addr, len;
703 printf("command='%s'\n", line_buf);
709 /* TODO: Make this return the correct value for user-mode. */
710 snprintf(buf, sizeof(buf), "S%02x", SIGTRAP);
715 addr = strtoull(p, (char **)&p, 16);
716 #if defined(TARGET_I386)
718 #elif defined (TARGET_PPC)
720 #elif defined (TARGET_SPARC)
723 #elif defined (TARGET_ARM)
724 env->regs[15] = addr;
725 #elif defined (TARGET_SH4)
729 #ifdef CONFIG_USER_ONLY
730 s->running_state = 1;
737 addr = strtoul(p, (char **)&p, 16);
738 #if defined(TARGET_I386)
740 #elif defined (TARGET_PPC)
742 #elif defined (TARGET_SPARC)
745 #elif defined (TARGET_ARM)
746 env->regs[15] = addr;
747 #elif defined (TARGET_SH4)
751 cpu_single_step(env, 1);
752 #ifdef CONFIG_USER_ONLY
753 s->running_state = 1;
759 reg_size = cpu_gdb_read_registers(env, mem_buf);
760 memtohex(buf, mem_buf, reg_size);
764 registers = (void *)mem_buf;
766 hextomem((uint8_t *)registers, p, len);
767 cpu_gdb_write_registers(env, mem_buf, len);
771 addr = strtoull(p, (char **)&p, 16);
774 len = strtoull(p, NULL, 16);
775 if (cpu_memory_rw_debug(env, addr, mem_buf, len, 0) != 0) {
776 put_packet (s, "E14");
778 memtohex(buf, mem_buf, len);
783 addr = strtoull(p, (char **)&p, 16);
786 len = strtoull(p, (char **)&p, 16);
789 hextomem(mem_buf, p, len);
790 if (cpu_memory_rw_debug(env, addr, mem_buf, len, 1) != 0)
791 put_packet(s, "E14");
796 type = strtoul(p, (char **)&p, 16);
799 addr = strtoull(p, (char **)&p, 16);
802 len = strtoull(p, (char **)&p, 16);
803 if (type == 0 || type == 1) {
804 if (cpu_breakpoint_insert(env, addr) < 0)
805 goto breakpoint_error;
809 put_packet(s, "E22");
813 type = strtoul(p, (char **)&p, 16);
816 addr = strtoull(p, (char **)&p, 16);
819 len = strtoull(p, (char **)&p, 16);
820 if (type == 0 || type == 1) {
821 cpu_breakpoint_remove(env, addr);
824 goto breakpoint_error;
827 #ifdef CONFIG_LINUX_USER
829 if (strncmp(p, "Offsets", 7) == 0) {
830 TaskState *ts = env->opaque;
832 sprintf(buf, "Text=%x;Data=%x;Bss=%x", ts->info->code_offset,
833 ts->info->data_offset, ts->info->data_offset);
841 /* put empty packet */
849 extern void tb_flush(CPUState *env);
851 #ifndef CONFIG_USER_ONLY
852 static void gdb_vm_stopped(void *opaque, int reason)
854 GDBState *s = opaque;
858 /* disable single step if it was enable */
859 cpu_single_step(s->env, 0);
861 if (reason == EXCP_DEBUG) {
864 } else if (reason == EXCP_INTERRUPT) {
869 snprintf(buf, sizeof(buf), "S%02x", ret);
874 static void gdb_read_byte(GDBState *s, int ch)
876 CPUState *env = s->env;
880 #ifndef CONFIG_USER_ONLY
881 if (s->last_packet_len) {
882 /* Waiting for a response to the last packet. If we see the start
883 of a new command then abandon the previous response. */
886 printf("Got NACK, retransmitting\n");
888 put_buffer(s, s->last_packet, s->last_packet_len);
894 printf("Got '%c' when expecting ACK/NACK\n", ch);
896 if (ch == '+' || ch == '$')
897 s->last_packet_len = 0;
902 /* when the CPU is running, we cannot do anything except stop
903 it when receiving a char */
904 vm_stop(EXCP_INTERRUPT);
911 s->line_buf_index = 0;
912 s->state = RS_GETLINE;
917 s->state = RS_CHKSUM1;
918 } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
921 s->line_buf[s->line_buf_index++] = ch;
925 s->line_buf[s->line_buf_index] = '\0';
926 s->line_csum = fromhex(ch) << 4;
927 s->state = RS_CHKSUM2;
930 s->line_csum |= fromhex(ch);
932 for(i = 0; i < s->line_buf_index; i++) {
933 csum += s->line_buf[i];
935 if (s->line_csum != (csum & 0xff)) {
937 put_buffer(s, reply, 1);
941 put_buffer(s, reply, 1);
942 s->state = gdb_handle_packet(s, env, s->line_buf);
949 #ifdef CONFIG_USER_ONLY
951 gdb_handlesig (CPUState *env, int sig)
957 if (gdbserver_fd < 0)
960 s = &gdbserver_state;
962 /* disable single step if it was enabled */
963 cpu_single_step(env, 0);
968 snprintf(buf, sizeof(buf), "S%02x", sig);
974 s->running_state = 0;
975 while (s->running_state == 0) {
976 n = read (s->fd, buf, 256);
981 for (i = 0; i < n; i++)
982 gdb_read_byte (s, buf[i]);
984 else if (n == 0 || errno != EAGAIN)
986 /* XXX: Connection closed. Should probably wait for annother
987 connection before continuing. */
994 /* Tell the remote gdb that the process has exited. */
995 void gdb_exit(CPUState *env, int code)
1000 if (gdbserver_fd < 0)
1003 s = &gdbserver_state;
1005 snprintf(buf, sizeof(buf), "W%02x", code);
1010 static void gdb_accept(void *opaque)
1013 struct sockaddr_in sockaddr;
1018 len = sizeof(sockaddr);
1019 fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
1020 if (fd < 0 && errno != EINTR) {
1023 } else if (fd >= 0) {
1028 /* set short latency */
1030 setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
1032 s = &gdbserver_state;
1033 memset (s, 0, sizeof (GDBState));
1034 s->env = first_cpu; /* XXX: allow to change CPU */
1037 fcntl(fd, F_SETFL, O_NONBLOCK);
1040 static int gdbserver_open(int port)
1042 struct sockaddr_in sockaddr;
1045 fd = socket(PF_INET, SOCK_STREAM, 0);
1051 /* allow fast reuse */
1053 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
1055 sockaddr.sin_family = AF_INET;
1056 sockaddr.sin_port = htons(port);
1057 sockaddr.sin_addr.s_addr = 0;
1058 ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
1063 ret = listen(fd, 0);
1071 int gdbserver_start(int port)
1073 gdbserver_fd = gdbserver_open(port);
1074 if (gdbserver_fd < 0)
1076 /* accept connections */
1081 static int gdb_chr_can_recieve(void *opaque)
1086 static void gdb_chr_recieve(void *opaque, const uint8_t *buf, int size)
1088 GDBState *s = opaque;
1091 for (i = 0; i < size; i++) {
1092 gdb_read_byte(s, buf[i]);
1096 static void gdb_chr_event(void *opaque, int event)
1099 case CHR_EVENT_RESET:
1100 vm_stop(EXCP_INTERRUPT);
1107 int gdbserver_start(CharDriverState *chr)
1114 s = qemu_mallocz(sizeof(GDBState));
1118 s->env = first_cpu; /* XXX: allow to change CPU */
1120 qemu_chr_add_handlers(chr, gdb_chr_can_recieve, gdb_chr_recieve,
1122 qemu_add_vm_stop_handler(gdb_vm_stopped, s);