4 * Copyright (c) 2006 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include "qemu-timer.h"
29 /* i82731AB (PIIX4) compatible power management function */
30 #define PM_FREQ 3579545
32 #define ACPI_DBG_IO_ADDR 0xb044
34 typedef struct PIIX4PMState {
42 int64_t tmr_overflow_time;
54 #define RTC_EN (1 << 10)
55 #define PWRBTN_EN (1 << 8)
56 #define GBL_EN (1 << 5)
57 #define TMROF_EN (1 << 0)
59 #define SCI_EN (1 << 0)
61 #define SUS_EN (1 << 13)
63 #define ACPI_ENABLE 0xf1
64 #define ACPI_DISABLE 0xf0
66 #define SMBHSTSTS 0x00
67 #define SMBHSTCNT 0x02
68 #define SMBHSTCMD 0x03
69 #define SMBHSTADD 0x04
70 #define SMBHSTDAT0 0x05
71 #define SMBHSTDAT1 0x06
72 #define SMBBLKDAT 0x07
74 static uint32_t get_pmtmr(PIIX4PMState *s)
77 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
81 static int get_pmsts(PIIX4PMState *s)
86 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
87 if (d >= s->tmr_overflow_time)
92 static void pm_update_sci(PIIX4PMState *s)
98 sci_level = (((pmsts & s->pmen) &
99 (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
100 qemu_set_irq(s->dev.irq[0], sci_level);
101 /* schedule a timer interruption if needed */
102 if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
103 expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
104 qemu_mod_timer(s->tmr_timer, expire_time);
106 qemu_del_timer(s->tmr_timer);
110 static void pm_tmr_timer(void *opaque)
112 PIIX4PMState *s = opaque;
116 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
118 PIIX4PMState *s = opaque;
125 pmsts = get_pmsts(s);
126 if (pmsts & val & TMROF_EN) {
127 /* if TMRSTS is reset, then compute the new overflow time */
128 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
129 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
142 s->pmcntrl = val & ~(SUS_EN);
144 /* change suspend type */
145 sus_typ = (val >> 10) & 3;
147 case 0: /* soft power off */
148 qemu_system_shutdown_request();
160 printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
164 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
166 PIIX4PMState *s = opaque;
185 printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
190 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
192 // PIIX4PMState *s = opaque;
195 printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
199 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
201 PIIX4PMState *s = opaque;
214 printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
219 static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
221 PIIX4PMState *s = opaque;
224 printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
229 /* ACPI specs 3.0, 4.7.2.5 */
230 if (val == ACPI_ENABLE) {
231 s->pmcntrl |= SCI_EN;
232 } else if (val == ACPI_DISABLE) {
233 s->pmcntrl &= ~SCI_EN;
236 if (s->dev.config[0x5b] & (1 << 1)) {
237 cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
244 static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
246 PIIX4PMState *s = opaque;
256 printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
261 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
264 printf("ACPI: DBG: 0x%08x\n", val);
268 static void smb_transaction(PIIX4PMState *s)
270 uint8_t prot = (s->smb_ctl >> 2) & 0x07;
271 uint8_t read = s->smb_addr & 0x01;
272 uint8_t cmd = s->smb_cmd;
273 uint8_t addr = s->smb_addr >> 1;
274 i2c_bus *bus = s->smbus;
277 printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
281 smbus_quick_command(bus, addr, read);
285 s->smb_data0 = smbus_receive_byte(bus, addr);
287 smbus_send_byte(bus, addr, cmd);
292 s->smb_data0 = smbus_read_byte(bus, addr, cmd);
294 smbus_write_byte(bus, addr, cmd, s->smb_data0);
300 val = smbus_read_word(bus, addr, cmd);
302 s->smb_data1 = val >> 8;
304 smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
309 s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
311 smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
323 static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
325 PIIX4PMState *s = opaque;
328 printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
353 s->smb_data[s->smb_index++] = val;
354 if (s->smb_index > 31)
362 static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
364 PIIX4PMState *s = opaque;
374 val = s->smb_ctl & 0x1f;
389 val = s->smb_data[s->smb_index++];
390 if (s->smb_index > 31)
398 printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
403 static void pm_io_space_update(PIIX4PMState *s)
407 if (s->dev.config[0x80] & 1) {
408 pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
409 pm_io_base &= 0xffc0;
411 /* XXX: need to improve memory and ioport allocation */
413 printf("PM: mapping to 0x%x\n", pm_io_base);
415 register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
416 register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
417 register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
418 register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
422 static void pm_write_config(PCIDevice *d,
423 uint32_t address, uint32_t val, int len)
425 pci_default_write_config(d, address, val, len);
427 pm_io_space_update((PIIX4PMState *)d);
430 static void pm_save(QEMUFile* f,void *opaque)
432 PIIX4PMState *s = opaque;
434 pci_device_save(&s->dev, f);
436 qemu_put_be16s(f, &s->pmsts);
437 qemu_put_be16s(f, &s->pmen);
438 qemu_put_be16s(f, &s->pmcntrl);
439 qemu_put_8s(f, &s->apmc);
440 qemu_put_8s(f, &s->apms);
441 qemu_put_timer(f, s->tmr_timer);
442 qemu_put_be64(f, s->tmr_overflow_time);
445 static int pm_load(QEMUFile* f,void* opaque,int version_id)
447 PIIX4PMState *s = opaque;
453 ret = pci_device_load(&s->dev, f);
457 qemu_get_be16s(f, &s->pmsts);
458 qemu_get_be16s(f, &s->pmen);
459 qemu_get_be16s(f, &s->pmcntrl);
460 qemu_get_8s(f, &s->apmc);
461 qemu_get_8s(f, &s->apms);
462 qemu_get_timer(f, s->tmr_timer);
463 s->tmr_overflow_time=qemu_get_be64(f);
465 pm_io_space_update(s);
470 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
475 s = (PIIX4PMState *)pci_register_device(bus,
476 "PM", sizeof(PIIX4PMState),
477 devfn, NULL, pm_write_config);
478 pci_conf = s->dev.config;
479 pci_conf[0x00] = 0x86;
480 pci_conf[0x01] = 0x80;
481 pci_conf[0x02] = 0x13;
482 pci_conf[0x03] = 0x71;
483 pci_conf[0x06] = 0x80;
484 pci_conf[0x07] = 0x02;
485 pci_conf[0x08] = 0x00; // revision number
486 pci_conf[0x09] = 0x00;
487 pci_conf[0x0a] = 0x80; // other bridge device
488 pci_conf[0x0b] = 0x06; // bridge device
489 pci_conf[0x0e] = 0x00; // header_type
490 pci_conf[0x3d] = 0x01; // interrupt pin 1
492 pci_conf[0x40] = 0x01; /* PM io base read only bit */
494 register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
495 register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
497 register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
499 /* XXX: which specification is used ? The i82731AB has different
501 pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
502 pci_conf[0x63] = 0x60;
503 pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
504 (serial_hds[1] != NULL ? 0x90 : 0);
506 pci_conf[0x90] = smb_io_base | 1;
507 pci_conf[0x91] = smb_io_base >> 8;
508 pci_conf[0xd2] = 0x09;
509 register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
510 register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
512 s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
514 register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
516 s->smbus = i2c_init_bus();