4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
22 #include "qemu-timer.h"
23 #include "host-utils.h"
27 /* APIC Local Vector Table */
28 #define APIC_LVT_TIMER 0
29 #define APIC_LVT_THERMAL 1
30 #define APIC_LVT_PERFORM 2
31 #define APIC_LVT_LINT0 3
32 #define APIC_LVT_LINT1 4
33 #define APIC_LVT_ERROR 5
36 /* APIC delivery modes */
37 #define APIC_DM_FIXED 0
38 #define APIC_DM_LOWPRI 1
41 #define APIC_DM_INIT 5
42 #define APIC_DM_SIPI 6
43 #define APIC_DM_EXTINT 7
45 /* APIC destination mode */
46 #define APIC_DESTMODE_FLAT 0xf
47 #define APIC_DESTMODE_CLUSTER 1
49 #define APIC_TRIGGER_EDGE 0
50 #define APIC_TRIGGER_LEVEL 1
52 #define APIC_LVT_TIMER_PERIODIC (1<<17)
53 #define APIC_LVT_MASKED (1<<16)
54 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
55 #define APIC_LVT_REMOTE_IRR (1<<14)
56 #define APIC_INPUT_POLARITY (1<<13)
57 #define APIC_SEND_PENDING (1<<12)
59 #define ESR_ILLEGAL_ADDRESS (1 << 7)
61 #define APIC_SV_ENABLE (1 << 8)
64 #define MAX_APIC_WORDS 8
66 typedef struct APICState {
72 uint32_t spurious_vec;
75 uint32_t isr[8]; /* in service register */
76 uint32_t tmr[8]; /* trigger mode register */
77 uint32_t irr[8]; /* interrupt request register */
78 uint32_t lvt[APIC_LVT_NB];
79 uint32_t esr; /* error register */
84 uint32_t initial_count;
85 int64_t initial_count_load_time, next_time;
89 static int apic_io_memory;
90 static APICState *local_apics[MAX_APICS + 1];
91 static int last_apic_id = 0;
92 static int apic_irq_delivered;
95 static void apic_init_ipi(APICState *s);
96 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
97 static void apic_update_irq(APICState *s);
98 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
99 uint8_t dest, uint8_t dest_mode);
101 /* Find first bit starting from msb */
102 static int fls_bit(uint32_t value)
104 return 31 - clz32(value);
107 /* Find first bit starting from lsb */
108 static int ffs_bit(uint32_t value)
113 static inline void set_bit(uint32_t *tab, int index)
117 mask = 1 << (index & 0x1f);
121 static inline void reset_bit(uint32_t *tab, int index)
125 mask = 1 << (index & 0x1f);
129 static inline int get_bit(uint32_t *tab, int index)
133 mask = 1 << (index & 0x1f);
134 return !!(tab[i] & mask);
137 static void apic_local_deliver(CPUState *env, int vector)
139 APICState *s = env->apic_state;
140 uint32_t lvt = s->lvt[vector];
143 if (lvt & APIC_LVT_MASKED)
146 switch ((lvt >> 8) & 7) {
148 cpu_interrupt(env, CPU_INTERRUPT_SMI);
152 cpu_interrupt(env, CPU_INTERRUPT_NMI);
156 cpu_interrupt(env, CPU_INTERRUPT_HARD);
160 trigger_mode = APIC_TRIGGER_EDGE;
161 if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
162 (lvt & APIC_LVT_LEVEL_TRIGGER))
163 trigger_mode = APIC_TRIGGER_LEVEL;
164 apic_set_irq(s, lvt & 0xff, trigger_mode);
168 void apic_deliver_pic_intr(CPUState *env, int level)
171 apic_local_deliver(env, APIC_LVT_LINT0);
173 APICState *s = env->apic_state;
174 uint32_t lvt = s->lvt[APIC_LVT_LINT0];
176 switch ((lvt >> 8) & 7) {
178 if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
180 reset_bit(s->irr, lvt & 0xff);
183 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
189 #define foreach_apic(apic, deliver_bitmask, code) \
191 int __i, __j, __mask;\
192 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
193 __mask = deliver_bitmask[__i];\
195 for(__j = 0; __j < 32; __j++) {\
196 if (__mask & (1 << __j)) {\
197 apic = local_apics[__i * 32 + __j];\
207 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
208 uint8_t delivery_mode,
209 uint8_t vector_num, uint8_t polarity,
210 uint8_t trigger_mode)
212 APICState *apic_iter;
214 switch (delivery_mode) {
216 /* XXX: search for focus processor, arbitration */
220 for(i = 0; i < MAX_APIC_WORDS; i++) {
221 if (deliver_bitmask[i]) {
222 d = i * 32 + ffs_bit(deliver_bitmask[i]);
227 apic_iter = local_apics[d];
229 apic_set_irq(apic_iter, vector_num, trigger_mode);
239 foreach_apic(apic_iter, deliver_bitmask,
240 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
244 foreach_apic(apic_iter, deliver_bitmask,
245 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
249 /* normal INIT IPI sent to processors */
250 foreach_apic(apic_iter, deliver_bitmask,
251 apic_init_ipi(apic_iter) );
255 /* handled in I/O APIC code */
262 foreach_apic(apic_iter, deliver_bitmask,
263 apic_set_irq(apic_iter, vector_num, trigger_mode) );
266 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
267 uint8_t delivery_mode, uint8_t vector_num,
268 uint8_t polarity, uint8_t trigger_mode)
270 uint32_t deliver_bitmask[MAX_APIC_WORDS];
272 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
273 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
277 void cpu_set_apic_base(CPUState *env, uint64_t val)
279 APICState *s = env->apic_state;
281 printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
283 s->apicbase = (val & 0xfffff000) |
284 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
285 /* if disabled, cannot be enabled again */
286 if (!(val & MSR_IA32_APICBASE_ENABLE)) {
287 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
288 env->cpuid_features &= ~CPUID_APIC;
289 s->spurious_vec &= ~APIC_SV_ENABLE;
293 uint64_t cpu_get_apic_base(CPUState *env)
295 APICState *s = env->apic_state;
297 printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase);
302 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
304 APICState *s = env->apic_state;
305 s->tpr = (val & 0x0f) << 4;
309 uint8_t cpu_get_apic_tpr(CPUX86State *env)
311 APICState *s = env->apic_state;
315 /* return -1 if no bit is set */
316 static int get_highest_priority_int(uint32_t *tab)
319 for(i = 7; i >= 0; i--) {
321 return i * 32 + fls_bit(tab[i]);
327 static int apic_get_ppr(APICState *s)
332 isrv = get_highest_priority_int(s->isr);
343 static int apic_get_arb_pri(APICState *s)
345 /* XXX: arbitration */
349 /* signal the CPU if an irq is pending */
350 static void apic_update_irq(APICState *s)
353 if (!(s->spurious_vec & APIC_SV_ENABLE))
355 irrv = get_highest_priority_int(s->irr);
358 ppr = apic_get_ppr(s);
359 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
361 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
364 void apic_reset_irq_delivered(void)
366 apic_irq_delivered = 0;
369 int apic_get_irq_delivered(void)
371 return apic_irq_delivered;
374 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
376 apic_irq_delivered += !get_bit(s->irr, vector_num);
378 set_bit(s->irr, vector_num);
380 set_bit(s->tmr, vector_num);
382 reset_bit(s->tmr, vector_num);
386 static void apic_eoi(APICState *s)
389 isrv = get_highest_priority_int(s->isr);
392 reset_bit(s->isr, isrv);
393 /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
394 set the remote IRR bit for level triggered interrupts. */
398 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
399 uint8_t dest, uint8_t dest_mode)
401 APICState *apic_iter;
404 if (dest_mode == 0) {
406 memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
408 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
409 set_bit(deliver_bitmask, dest);
412 /* XXX: cluster mode */
413 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
414 for(i = 0; i < MAX_APICS; i++) {
415 apic_iter = local_apics[i];
417 if (apic_iter->dest_mode == 0xf) {
418 if (dest & apic_iter->log_dest)
419 set_bit(deliver_bitmask, i);
420 } else if (apic_iter->dest_mode == 0x0) {
421 if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
422 (dest & apic_iter->log_dest & 0x0f)) {
423 set_bit(deliver_bitmask, i);
432 static void apic_init_ipi(APICState *s)
437 s->spurious_vec = 0xff;
440 memset(s->isr, 0, sizeof(s->isr));
441 memset(s->tmr, 0, sizeof(s->tmr));
442 memset(s->irr, 0, sizeof(s->irr));
443 for(i = 0; i < APIC_LVT_NB; i++)
444 s->lvt[i] = 1 << 16; /* mask LVT */
446 memset(s->icr, 0, sizeof(s->icr));
449 s->initial_count = 0;
450 s->initial_count_load_time = 0;
453 cpu_reset(s->cpu_env);
455 if (!(s->apicbase & MSR_IA32_APICBASE_BSP))
456 s->cpu_env->halted = 1;
459 /* send a SIPI message to the CPU to start it */
460 static void apic_startup(APICState *s, int vector_num)
462 CPUState *env = s->cpu_env;
466 cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
471 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
472 uint8_t delivery_mode, uint8_t vector_num,
473 uint8_t polarity, uint8_t trigger_mode)
475 uint32_t deliver_bitmask[MAX_APIC_WORDS];
476 int dest_shorthand = (s->icr[0] >> 18) & 3;
477 APICState *apic_iter;
479 switch (dest_shorthand) {
481 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
484 memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
485 set_bit(deliver_bitmask, s->id);
488 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
491 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
492 reset_bit(deliver_bitmask, s->id);
496 switch (delivery_mode) {
499 int trig_mode = (s->icr[0] >> 15) & 1;
500 int level = (s->icr[0] >> 14) & 1;
501 if (level == 0 && trig_mode == 1) {
502 foreach_apic(apic_iter, deliver_bitmask,
503 apic_iter->arb_id = apic_iter->id );
510 foreach_apic(apic_iter, deliver_bitmask,
511 apic_startup(apic_iter, vector_num) );
515 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
519 int apic_get_interrupt(CPUState *env)
521 APICState *s = env->apic_state;
524 /* if the APIC is installed or enabled, we let the 8259 handle the
528 if (!(s->spurious_vec & APIC_SV_ENABLE))
531 /* XXX: spurious IRQ handling */
532 intno = get_highest_priority_int(s->irr);
535 if (s->tpr && intno <= s->tpr)
536 return s->spurious_vec & 0xff;
537 reset_bit(s->irr, intno);
538 set_bit(s->isr, intno);
543 int apic_accept_pic_intr(CPUState *env)
545 APICState *s = env->apic_state;
551 lvt0 = s->lvt[APIC_LVT_LINT0];
553 if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
554 (lvt0 & APIC_LVT_MASKED) == 0)
560 static uint32_t apic_get_current_count(APICState *s)
564 d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
566 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
568 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
570 if (d >= s->initial_count)
573 val = s->initial_count - d;
578 static void apic_timer_update(APICState *s, int64_t current_time)
580 int64_t next_time, d;
582 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
583 d = (current_time - s->initial_count_load_time) >>
585 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
586 if (!s->initial_count)
588 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
590 if (d >= s->initial_count)
592 d = (uint64_t)s->initial_count + 1;
594 next_time = s->initial_count_load_time + (d << s->count_shift);
595 qemu_mod_timer(s->timer, next_time);
596 s->next_time = next_time;
599 qemu_del_timer(s->timer);
603 static void apic_timer(void *opaque)
605 APICState *s = opaque;
607 apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
608 apic_timer_update(s, s->next_time);
611 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
616 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
621 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
625 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
629 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
636 env = cpu_single_env;
641 index = (addr >> 4) & 0xff;
646 case 0x03: /* version */
647 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
653 val = apic_get_arb_pri(s);
657 val = apic_get_ppr(s);
663 val = s->log_dest << 24;
666 val = s->dest_mode << 28;
669 val = s->spurious_vec;
672 val = s->isr[index & 7];
675 val = s->tmr[index & 7];
678 val = s->irr[index & 7];
685 val = s->icr[index & 1];
688 val = s->lvt[index - 0x32];
691 val = s->initial_count;
694 val = apic_get_current_count(s);
697 val = s->divide_conf;
700 s->esr |= ESR_ILLEGAL_ADDRESS;
705 printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
710 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
716 env = cpu_single_env;
722 printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
725 index = (addr >> 4) & 0xff;
743 s->log_dest = val >> 24;
746 s->dest_mode = val >> 28;
749 s->spurious_vec = val & 0x1ff;
759 apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
760 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
761 (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
768 int n = index - 0x32;
770 if (n == APIC_LVT_TIMER)
771 apic_timer_update(s, qemu_get_clock(vm_clock));
775 s->initial_count = val;
776 s->initial_count_load_time = qemu_get_clock(vm_clock);
777 apic_timer_update(s, s->initial_count_load_time);
784 s->divide_conf = val & 0xb;
785 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
786 s->count_shift = (v + 1) & 7;
790 s->esr |= ESR_ILLEGAL_ADDRESS;
795 static void apic_save(QEMUFile *f, void *opaque)
797 APICState *s = opaque;
800 qemu_put_be32s(f, &s->apicbase);
801 qemu_put_8s(f, &s->id);
802 qemu_put_8s(f, &s->arb_id);
803 qemu_put_8s(f, &s->tpr);
804 qemu_put_be32s(f, &s->spurious_vec);
805 qemu_put_8s(f, &s->log_dest);
806 qemu_put_8s(f, &s->dest_mode);
807 for (i = 0; i < 8; i++) {
808 qemu_put_be32s(f, &s->isr[i]);
809 qemu_put_be32s(f, &s->tmr[i]);
810 qemu_put_be32s(f, &s->irr[i]);
812 for (i = 0; i < APIC_LVT_NB; i++) {
813 qemu_put_be32s(f, &s->lvt[i]);
815 qemu_put_be32s(f, &s->esr);
816 qemu_put_be32s(f, &s->icr[0]);
817 qemu_put_be32s(f, &s->icr[1]);
818 qemu_put_be32s(f, &s->divide_conf);
819 qemu_put_be32(f, s->count_shift);
820 qemu_put_be32s(f, &s->initial_count);
821 qemu_put_be64(f, s->initial_count_load_time);
822 qemu_put_be64(f, s->next_time);
824 qemu_put_timer(f, s->timer);
827 static int apic_load(QEMUFile *f, void *opaque, int version_id)
829 APICState *s = opaque;
835 /* XXX: what if the base changes? (registered memory regions) */
836 qemu_get_be32s(f, &s->apicbase);
837 qemu_get_8s(f, &s->id);
838 qemu_get_8s(f, &s->arb_id);
839 qemu_get_8s(f, &s->tpr);
840 qemu_get_be32s(f, &s->spurious_vec);
841 qemu_get_8s(f, &s->log_dest);
842 qemu_get_8s(f, &s->dest_mode);
843 for (i = 0; i < 8; i++) {
844 qemu_get_be32s(f, &s->isr[i]);
845 qemu_get_be32s(f, &s->tmr[i]);
846 qemu_get_be32s(f, &s->irr[i]);
848 for (i = 0; i < APIC_LVT_NB; i++) {
849 qemu_get_be32s(f, &s->lvt[i]);
851 qemu_get_be32s(f, &s->esr);
852 qemu_get_be32s(f, &s->icr[0]);
853 qemu_get_be32s(f, &s->icr[1]);
854 qemu_get_be32s(f, &s->divide_conf);
855 s->count_shift=qemu_get_be32(f);
856 qemu_get_be32s(f, &s->initial_count);
857 s->initial_count_load_time=qemu_get_be64(f);
858 s->next_time=qemu_get_be64(f);
861 qemu_get_timer(f, s->timer);
865 static void apic_reset(void *opaque)
867 APICState *s = opaque;
869 s->apicbase = 0xfee00000 |
870 (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
876 * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
877 * time typically by BIOS, so PIC interrupt can be delivered to the
878 * processor when local APIC is enabled.
880 s->lvt[APIC_LVT_LINT0] = 0x700;
884 static CPUReadMemoryFunc *apic_mem_read[3] = {
890 static CPUWriteMemoryFunc *apic_mem_write[3] = {
896 int apic_init(CPUState *env)
900 if (last_apic_id >= MAX_APICS)
902 s = qemu_mallocz(sizeof(APICState));
904 s->id = last_apic_id++;
905 env->cpuid_apic_id = s->id;
910 /* XXX: mapping more APICs at the same memory location */
911 if (apic_io_memory == 0) {
912 /* NOTE: the APIC is directly connected to the CPU - it is not
913 on the global memory bus. */
914 apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
915 apic_mem_write, NULL);
916 cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
919 s->timer = qemu_new_timer(vm_clock, apic_timer, s);
921 register_savevm("apic", s->id, 2, apic_save, apic_load, s);
922 qemu_register_reset(apic_reset, s);
924 local_apics[s->id] = s;