4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 //#define DEBUG_IOAPIC
25 /* APIC Local Vector Table */
26 #define APIC_LVT_TIMER 0
27 #define APIC_LVT_THERMAL 1
28 #define APIC_LVT_PERFORM 2
29 #define APIC_LVT_LINT0 3
30 #define APIC_LVT_LINT1 4
31 #define APIC_LVT_ERROR 5
34 /* APIC delivery modes */
35 #define APIC_DM_FIXED 0
36 #define APIC_DM_LOWPRI 1
39 #define APIC_DM_INIT 5
40 #define APIC_DM_SIPI 6
41 #define APIC_DM_EXTINT 7
43 /* APIC destination mode */
44 #define APIC_DESTMODE_FLAT 0xf
45 #define APIC_DESTMODE_CLUSTER 1
47 #define APIC_TRIGGER_EDGE 0
48 #define APIC_TRIGGER_LEVEL 1
50 #define APIC_LVT_TIMER_PERIODIC (1<<17)
51 #define APIC_LVT_MASKED (1<<16)
52 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
53 #define APIC_LVT_REMOTE_IRR (1<<14)
54 #define APIC_INPUT_POLARITY (1<<13)
55 #define APIC_SEND_PENDING (1<<12)
57 #define IOAPIC_NUM_PINS 0x18
59 #define ESR_ILLEGAL_ADDRESS (1 << 7)
61 #define APIC_SV_ENABLE (1 << 8)
64 #define MAX_APIC_WORDS 8
66 typedef struct APICState {
72 uint32_t spurious_vec;
75 uint32_t isr[8]; /* in service register */
76 uint32_t tmr[8]; /* trigger mode register */
77 uint32_t irr[8]; /* interrupt request register */
78 uint32_t lvt[APIC_LVT_NB];
79 uint32_t esr; /* error register */
84 uint32_t initial_count;
85 int64_t initial_count_load_time, next_time;
94 uint64_t ioredtbl[IOAPIC_NUM_PINS];
97 static int apic_io_memory;
98 static APICState *local_apics[MAX_APICS + 1];
99 static int last_apic_id = 0;
101 static void apic_init_ipi(APICState *s);
102 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
103 static void apic_update_irq(APICState *s);
105 /* Find first bit starting from msb. Return 0 if value = 0 */
106 static int fls_bit(uint32_t value)
108 unsigned int ret = 0;
110 #if defined(HOST_I386)
111 __asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
115 value >>= 16, ret = 16;
117 value >>= 8, ret += 8;
119 value >>= 4, ret += 4;
121 value >>= 2, ret += 2;
122 return ret + (value >> 1);
126 /* Find first bit starting from lsb. Return 0 if value = 0 */
127 static int ffs_bit(uint32_t value)
129 unsigned int ret = 0;
131 #if defined(HOST_I386)
132 __asm__ __volatile__ ("bsf %1, %0\n" : "+r" (ret) : "rm" (value));
137 if (!(value & 0xffff))
138 value >>= 16, ret = 16;
140 value >>= 8, ret += 8;
142 value >>= 4, ret += 4;
144 value >>= 2, ret += 2;
151 static inline void set_bit(uint32_t *tab, int index)
155 mask = 1 << (index & 0x1f);
159 static inline void reset_bit(uint32_t *tab, int index)
163 mask = 1 << (index & 0x1f);
167 #define foreach_apic(apic, deliver_bitmask, code) \
169 int __i, __j, __mask;\
170 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
171 __mask = deliver_bitmask[__i];\
173 for(__j = 0; __j < 32; __j++) {\
174 if (__mask & (1 << __j)) {\
175 apic = local_apics[__i * 32 + __j];\
185 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
186 uint8_t delivery_mode,
187 uint8_t vector_num, uint8_t polarity,
188 uint8_t trigger_mode)
190 APICState *apic_iter;
192 switch (delivery_mode) {
194 /* XXX: search for focus processor, arbitration */
198 for(i = 0; i < MAX_APIC_WORDS; i++) {
199 if (deliver_bitmask[i]) {
200 d = i * 32 + ffs_bit(deliver_bitmask[i]);
205 apic_iter = local_apics[d];
207 apic_set_irq(apic_iter, vector_num, trigger_mode);
221 /* normal INIT IPI sent to processors */
222 foreach_apic(apic_iter, deliver_bitmask,
223 apic_init_ipi(apic_iter) );
227 /* handled in I/O APIC code */
234 foreach_apic(apic_iter, deliver_bitmask,
235 apic_set_irq(apic_iter, vector_num, trigger_mode) );
238 void cpu_set_apic_base(CPUState *env, uint64_t val)
240 APICState *s = env->apic_state;
242 printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
244 s->apicbase = (val & 0xfffff000) |
245 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
246 /* if disabled, cannot be enabled again */
247 if (!(val & MSR_IA32_APICBASE_ENABLE)) {
248 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
249 env->cpuid_features &= ~CPUID_APIC;
250 s->spurious_vec &= ~APIC_SV_ENABLE;
254 uint64_t cpu_get_apic_base(CPUState *env)
256 APICState *s = env->apic_state;
258 printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase);
263 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
265 APICState *s = env->apic_state;
266 s->tpr = (val & 0x0f) << 4;
270 uint8_t cpu_get_apic_tpr(CPUX86State *env)
272 APICState *s = env->apic_state;
276 /* return -1 if no bit is set */
277 static int get_highest_priority_int(uint32_t *tab)
280 for(i = 7; i >= 0; i--) {
282 return i * 32 + fls_bit(tab[i]);
288 static int apic_get_ppr(APICState *s)
293 isrv = get_highest_priority_int(s->isr);
304 static int apic_get_arb_pri(APICState *s)
306 /* XXX: arbitration */
310 /* signal the CPU if an irq is pending */
311 static void apic_update_irq(APICState *s)
314 if (!(s->spurious_vec & APIC_SV_ENABLE))
316 irrv = get_highest_priority_int(s->irr);
319 ppr = apic_get_ppr(s);
320 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
322 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
325 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
327 set_bit(s->irr, vector_num);
329 set_bit(s->tmr, vector_num);
331 reset_bit(s->tmr, vector_num);
335 static void apic_eoi(APICState *s)
338 isrv = get_highest_priority_int(s->isr);
341 reset_bit(s->isr, isrv);
342 /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
343 set the remote IRR bit for level triggered interrupts. */
347 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
348 uint8_t dest, uint8_t dest_mode)
350 APICState *apic_iter;
353 if (dest_mode == 0) {
355 memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
357 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
358 set_bit(deliver_bitmask, dest);
361 /* XXX: cluster mode */
362 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
363 for(i = 0; i < MAX_APICS; i++) {
364 apic_iter = local_apics[i];
366 if (apic_iter->dest_mode == 0xf) {
367 if (dest & apic_iter->log_dest)
368 set_bit(deliver_bitmask, i);
369 } else if (apic_iter->dest_mode == 0x0) {
370 if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
371 (dest & apic_iter->log_dest & 0x0f)) {
372 set_bit(deliver_bitmask, i);
381 static void apic_init_ipi(APICState *s)
385 for(i = 0; i < APIC_LVT_NB; i++)
386 s->lvt[i] = 1 << 16; /* mask LVT */
388 s->spurious_vec = 0xff;
391 memset(s->isr, 0, sizeof(s->isr));
392 memset(s->tmr, 0, sizeof(s->tmr));
393 memset(s->irr, 0, sizeof(s->irr));
394 memset(s->lvt, 0, sizeof(s->lvt));
396 memset(s->icr, 0, sizeof(s->icr));
399 s->initial_count = 0;
400 s->initial_count_load_time = 0;
404 /* send a SIPI message to the CPU to start it */
405 static void apic_startup(APICState *s, int vector_num)
407 CPUState *env = s->cpu_env;
408 if (!(env->hflags & HF_HALTED_MASK))
411 cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
413 env->hflags &= ~HF_HALTED_MASK;
416 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
417 uint8_t delivery_mode, uint8_t vector_num,
418 uint8_t polarity, uint8_t trigger_mode)
420 uint32_t deliver_bitmask[MAX_APIC_WORDS];
421 int dest_shorthand = (s->icr[0] >> 18) & 3;
422 APICState *apic_iter;
424 switch (dest_shorthand) {
426 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
429 memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
430 set_bit(deliver_bitmask, s->id);
433 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
436 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
437 reset_bit(deliver_bitmask, s->id);
441 switch (delivery_mode) {
444 int trig_mode = (s->icr[0] >> 15) & 1;
445 int level = (s->icr[0] >> 14) & 1;
446 if (level == 0 && trig_mode == 1) {
447 foreach_apic(apic_iter, deliver_bitmask,
448 apic_iter->arb_id = apic_iter->id );
455 foreach_apic(apic_iter, deliver_bitmask,
456 apic_startup(apic_iter, vector_num) );
460 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
464 int apic_get_interrupt(CPUState *env)
466 APICState *s = env->apic_state;
469 /* if the APIC is installed or enabled, we let the 8259 handle the
473 if (!(s->spurious_vec & APIC_SV_ENABLE))
476 /* XXX: spurious IRQ handling */
477 intno = get_highest_priority_int(s->irr);
480 reset_bit(s->irr, intno);
481 if (s->tpr && intno <= s->tpr)
482 return s->spurious_vec & 0xff;
483 set_bit(s->isr, intno);
488 static uint32_t apic_get_current_count(APICState *s)
492 d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
494 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
496 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
498 if (d >= s->initial_count)
501 val = s->initial_count - d;
506 static void apic_timer_update(APICState *s, int64_t current_time)
508 int64_t next_time, d;
510 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
511 d = (current_time - s->initial_count_load_time) >>
513 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
514 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
516 if (d >= s->initial_count)
518 d = (uint64_t)s->initial_count + 1;
520 next_time = s->initial_count_load_time + (d << s->count_shift);
521 qemu_mod_timer(s->timer, next_time);
522 s->next_time = next_time;
525 qemu_del_timer(s->timer);
529 static void apic_timer(void *opaque)
531 APICState *s = opaque;
533 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
534 apic_set_irq(s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
536 apic_timer_update(s, s->next_time);
539 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
544 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
549 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
553 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
557 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
564 env = cpu_single_env;
569 index = (addr >> 4) & 0xff;
574 case 0x03: /* version */
575 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
581 val = apic_get_arb_pri(s);
585 val = apic_get_ppr(s);
588 val = s->log_dest << 24;
591 val = s->dest_mode << 28;
594 val = s->spurious_vec;
597 val = s->isr[index & 7];
600 val = s->tmr[index & 7];
603 val = s->irr[index & 7];
610 val = s->icr[index & 1];
613 val = s->lvt[index - 0x32];
616 val = s->initial_count;
619 val = apic_get_current_count(s);
622 val = s->divide_conf;
625 s->esr |= ESR_ILLEGAL_ADDRESS;
630 printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
635 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
641 env = cpu_single_env;
647 printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
650 index = (addr >> 4) & 0xff;
668 s->log_dest = val >> 24;
671 s->dest_mode = val >> 28;
674 s->spurious_vec = val & 0x1ff;
684 apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
685 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
686 (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
693 int n = index - 0x32;
695 if (n == APIC_LVT_TIMER)
696 apic_timer_update(s, qemu_get_clock(vm_clock));
700 s->initial_count = val;
701 s->initial_count_load_time = qemu_get_clock(vm_clock);
702 apic_timer_update(s, s->initial_count_load_time);
709 s->divide_conf = val & 0xb;
710 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
711 s->count_shift = (v + 1) & 7;
715 s->esr |= ESR_ILLEGAL_ADDRESS;
720 static void apic_save(QEMUFile *f, void *opaque)
722 APICState *s = opaque;
725 qemu_put_be32s(f, &s->apicbase);
726 qemu_put_8s(f, &s->id);
727 qemu_put_8s(f, &s->arb_id);
728 qemu_put_8s(f, &s->tpr);
729 qemu_put_be32s(f, &s->spurious_vec);
730 qemu_put_8s(f, &s->log_dest);
731 qemu_put_8s(f, &s->dest_mode);
732 for (i = 0; i < 8; i++) {
733 qemu_put_be32s(f, &s->isr[i]);
734 qemu_put_be32s(f, &s->tmr[i]);
735 qemu_put_be32s(f, &s->irr[i]);
737 for (i = 0; i < APIC_LVT_NB; i++) {
738 qemu_put_be32s(f, &s->lvt[i]);
740 qemu_put_be32s(f, &s->esr);
741 qemu_put_be32s(f, &s->icr[0]);
742 qemu_put_be32s(f, &s->icr[1]);
743 qemu_put_be32s(f, &s->divide_conf);
744 qemu_put_be32s(f, &s->count_shift);
745 qemu_put_be32s(f, &s->initial_count);
746 qemu_put_be64s(f, &s->initial_count_load_time);
747 qemu_put_be64s(f, &s->next_time);
750 static int apic_load(QEMUFile *f, void *opaque, int version_id)
752 APICState *s = opaque;
758 /* XXX: what if the base changes? (registered memory regions) */
759 qemu_get_be32s(f, &s->apicbase);
760 qemu_get_8s(f, &s->id);
761 qemu_get_8s(f, &s->arb_id);
762 qemu_get_8s(f, &s->tpr);
763 qemu_get_be32s(f, &s->spurious_vec);
764 qemu_get_8s(f, &s->log_dest);
765 qemu_get_8s(f, &s->dest_mode);
766 for (i = 0; i < 8; i++) {
767 qemu_get_be32s(f, &s->isr[i]);
768 qemu_get_be32s(f, &s->tmr[i]);
769 qemu_get_be32s(f, &s->irr[i]);
771 for (i = 0; i < APIC_LVT_NB; i++) {
772 qemu_get_be32s(f, &s->lvt[i]);
774 qemu_get_be32s(f, &s->esr);
775 qemu_get_be32s(f, &s->icr[0]);
776 qemu_get_be32s(f, &s->icr[1]);
777 qemu_get_be32s(f, &s->divide_conf);
778 qemu_get_be32s(f, &s->count_shift);
779 qemu_get_be32s(f, &s->initial_count);
780 qemu_get_be64s(f, &s->initial_count_load_time);
781 qemu_get_be64s(f, &s->next_time);
785 static void apic_reset(void *opaque)
787 APICState *s = opaque;
791 static CPUReadMemoryFunc *apic_mem_read[3] = {
797 static CPUWriteMemoryFunc *apic_mem_write[3] = {
803 int apic_init(CPUState *env)
807 if (last_apic_id >= MAX_APICS)
809 s = qemu_mallocz(sizeof(APICState));
814 s->id = last_apic_id++;
816 s->apicbase = 0xfee00000 |
817 (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
819 /* XXX: mapping more APICs at the same memory location */
820 if (apic_io_memory == 0) {
821 /* NOTE: the APIC is directly connected to the CPU - it is not
822 on the global memory bus. */
823 apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
824 apic_mem_write, NULL);
825 cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
828 s->timer = qemu_new_timer(vm_clock, apic_timer, s);
830 register_savevm("apic", 0, 1, apic_save, apic_load, s);
831 qemu_register_reset(apic_reset, s);
833 local_apics[s->id] = s;
837 static void ioapic_service(IOAPICState *s)
842 uint8_t delivery_mode;
848 uint32_t deliver_bitmask[MAX_APIC_WORDS];
850 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
853 entry = s->ioredtbl[i];
854 if (!(entry & APIC_LVT_MASKED)) {
855 trig_mode = ((entry >> 15) & 1);
857 dest_mode = (entry >> 11) & 1;
858 delivery_mode = (entry >> 8) & 7;
859 polarity = (entry >> 13) & 1;
860 if (trig_mode == APIC_TRIGGER_EDGE)
862 if (delivery_mode == APIC_DM_EXTINT)
863 vector = pic_read_irq(isa_pic);
865 vector = entry & 0xff;
867 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
868 apic_bus_deliver(deliver_bitmask, delivery_mode,
869 vector, polarity, trig_mode);
875 void ioapic_set_irq(void *opaque, int vector, int level)
877 IOAPICState *s = opaque;
879 if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
880 uint32_t mask = 1 << vector;
881 uint64_t entry = s->ioredtbl[vector];
883 if ((entry >> 15) & 1) {
884 /* level triggered */
901 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
903 IOAPICState *s = opaque;
910 } else if (addr == 0x10) {
911 switch (s->ioregsel) {
916 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
922 index = (s->ioregsel - 0x10) >> 1;
923 if (index >= 0 && index < IOAPIC_NUM_PINS) {
925 val = s->ioredtbl[index] >> 32;
927 val = s->ioredtbl[index] & 0xffffffff;
931 printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
937 static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
939 IOAPICState *s = opaque;
946 } else if (addr == 0x10) {
948 printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
950 switch (s->ioregsel) {
952 s->id = (val >> 24) & 0xff;
958 index = (s->ioregsel - 0x10) >> 1;
959 if (index >= 0 && index < IOAPIC_NUM_PINS) {
960 if (s->ioregsel & 1) {
961 s->ioredtbl[index] &= 0xffffffff;
962 s->ioredtbl[index] |= (uint64_t)val << 32;
964 s->ioredtbl[index] &= ~0xffffffffULL;
965 s->ioredtbl[index] |= val;
973 static void ioapic_save(QEMUFile *f, void *opaque)
975 IOAPICState *s = opaque;
978 qemu_put_8s(f, &s->id);
979 qemu_put_8s(f, &s->ioregsel);
980 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
981 qemu_put_be64s(f, &s->ioredtbl[i]);
985 static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
987 IOAPICState *s = opaque;
993 qemu_get_8s(f, &s->id);
994 qemu_get_8s(f, &s->ioregsel);
995 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
996 qemu_get_be64s(f, &s->ioredtbl[i]);
1001 static void ioapic_reset(void *opaque)
1003 IOAPICState *s = opaque;
1006 memset(s, 0, sizeof(*s));
1007 for(i = 0; i < IOAPIC_NUM_PINS; i++)
1008 s->ioredtbl[i] = 1 << 16; /* mask LVT */
1011 static CPUReadMemoryFunc *ioapic_mem_read[3] = {
1017 static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
1023 IOAPICState *ioapic_init(void)
1028 s = qemu_mallocz(sizeof(IOAPICState));
1032 s->id = last_apic_id++;
1034 io_memory = cpu_register_io_memory(0, ioapic_mem_read,
1035 ioapic_mem_write, s);
1036 cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
1038 register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
1039 qemu_register_reset(ioapic_reset, s);