4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
22 #include "qemu-timer.h"
23 #include "host-utils.h"
27 /* APIC Local Vector Table */
28 #define APIC_LVT_TIMER 0
29 #define APIC_LVT_THERMAL 1
30 #define APIC_LVT_PERFORM 2
31 #define APIC_LVT_LINT0 3
32 #define APIC_LVT_LINT1 4
33 #define APIC_LVT_ERROR 5
36 /* APIC delivery modes */
37 #define APIC_DM_FIXED 0
38 #define APIC_DM_LOWPRI 1
41 #define APIC_DM_INIT 5
42 #define APIC_DM_SIPI 6
43 #define APIC_DM_EXTINT 7
45 /* APIC destination mode */
46 #define APIC_DESTMODE_FLAT 0xf
47 #define APIC_DESTMODE_CLUSTER 1
49 #define APIC_TRIGGER_EDGE 0
50 #define APIC_TRIGGER_LEVEL 1
52 #define APIC_LVT_TIMER_PERIODIC (1<<17)
53 #define APIC_LVT_MASKED (1<<16)
54 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
55 #define APIC_LVT_REMOTE_IRR (1<<14)
56 #define APIC_INPUT_POLARITY (1<<13)
57 #define APIC_SEND_PENDING (1<<12)
59 #define ESR_ILLEGAL_ADDRESS (1 << 7)
61 #define APIC_SV_ENABLE (1 << 8)
64 #define MAX_APIC_WORDS 8
66 typedef struct APICState {
72 uint32_t spurious_vec;
75 uint32_t isr[8]; /* in service register */
76 uint32_t tmr[8]; /* trigger mode register */
77 uint32_t irr[8]; /* interrupt request register */
78 uint32_t lvt[APIC_LVT_NB];
79 uint32_t esr; /* error register */
84 uint32_t initial_count;
85 int64_t initial_count_load_time, next_time;
90 static int apic_io_memory;
91 static APICState *local_apics[MAX_APICS + 1];
92 static int last_apic_idx = 0;
93 static int apic_irq_delivered;
96 static void apic_init_ipi(APICState *s);
97 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
98 static void apic_update_irq(APICState *s);
99 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
100 uint8_t dest, uint8_t dest_mode);
102 /* Find first bit starting from msb */
103 static int fls_bit(uint32_t value)
105 return 31 - clz32(value);
108 /* Find first bit starting from lsb */
109 static int ffs_bit(uint32_t value)
114 static inline void set_bit(uint32_t *tab, int index)
118 mask = 1 << (index & 0x1f);
122 static inline void reset_bit(uint32_t *tab, int index)
126 mask = 1 << (index & 0x1f);
130 static inline int get_bit(uint32_t *tab, int index)
134 mask = 1 << (index & 0x1f);
135 return !!(tab[i] & mask);
138 static void apic_local_deliver(CPUState *env, int vector)
140 APICState *s = env->apic_state;
141 uint32_t lvt = s->lvt[vector];
144 if (lvt & APIC_LVT_MASKED)
147 switch ((lvt >> 8) & 7) {
149 cpu_interrupt(env, CPU_INTERRUPT_SMI);
153 cpu_interrupt(env, CPU_INTERRUPT_NMI);
157 cpu_interrupt(env, CPU_INTERRUPT_HARD);
161 trigger_mode = APIC_TRIGGER_EDGE;
162 if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
163 (lvt & APIC_LVT_LEVEL_TRIGGER))
164 trigger_mode = APIC_TRIGGER_LEVEL;
165 apic_set_irq(s, lvt & 0xff, trigger_mode);
169 void apic_deliver_pic_intr(CPUState *env, int level)
172 apic_local_deliver(env, APIC_LVT_LINT0);
174 APICState *s = env->apic_state;
175 uint32_t lvt = s->lvt[APIC_LVT_LINT0];
177 switch ((lvt >> 8) & 7) {
179 if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
181 reset_bit(s->irr, lvt & 0xff);
184 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
190 #define foreach_apic(apic, deliver_bitmask, code) \
192 int __i, __j, __mask;\
193 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
194 __mask = deliver_bitmask[__i];\
196 for(__j = 0; __j < 32; __j++) {\
197 if (__mask & (1 << __j)) {\
198 apic = local_apics[__i * 32 + __j];\
208 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
209 uint8_t delivery_mode,
210 uint8_t vector_num, uint8_t polarity,
211 uint8_t trigger_mode)
213 APICState *apic_iter;
215 switch (delivery_mode) {
217 /* XXX: search for focus processor, arbitration */
221 for(i = 0; i < MAX_APIC_WORDS; i++) {
222 if (deliver_bitmask[i]) {
223 d = i * 32 + ffs_bit(deliver_bitmask[i]);
228 apic_iter = local_apics[d];
230 apic_set_irq(apic_iter, vector_num, trigger_mode);
240 foreach_apic(apic_iter, deliver_bitmask,
241 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
245 foreach_apic(apic_iter, deliver_bitmask,
246 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
250 /* normal INIT IPI sent to processors */
251 foreach_apic(apic_iter, deliver_bitmask,
252 apic_init_ipi(apic_iter) );
256 /* handled in I/O APIC code */
263 foreach_apic(apic_iter, deliver_bitmask,
264 apic_set_irq(apic_iter, vector_num, trigger_mode) );
267 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
268 uint8_t delivery_mode, uint8_t vector_num,
269 uint8_t polarity, uint8_t trigger_mode)
271 uint32_t deliver_bitmask[MAX_APIC_WORDS];
273 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
274 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
278 void cpu_set_apic_base(CPUState *env, uint64_t val)
280 APICState *s = env->apic_state;
282 printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
286 s->apicbase = (val & 0xfffff000) |
287 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
288 /* if disabled, cannot be enabled again */
289 if (!(val & MSR_IA32_APICBASE_ENABLE)) {
290 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
291 env->cpuid_features &= ~CPUID_APIC;
292 s->spurious_vec &= ~APIC_SV_ENABLE;
296 uint64_t cpu_get_apic_base(CPUState *env)
298 APICState *s = env->apic_state;
300 printf("cpu_get_apic_base: %016" PRIx64 "\n",
301 s ? (uint64_t)s->apicbase: 0);
303 return s ? s->apicbase : 0;
306 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
308 APICState *s = env->apic_state;
311 s->tpr = (val & 0x0f) << 4;
315 uint8_t cpu_get_apic_tpr(CPUX86State *env)
317 APICState *s = env->apic_state;
318 return s ? s->tpr >> 4 : 0;
321 /* return -1 if no bit is set */
322 static int get_highest_priority_int(uint32_t *tab)
325 for(i = 7; i >= 0; i--) {
327 return i * 32 + fls_bit(tab[i]);
333 static int apic_get_ppr(APICState *s)
338 isrv = get_highest_priority_int(s->isr);
349 static int apic_get_arb_pri(APICState *s)
351 /* XXX: arbitration */
355 /* signal the CPU if an irq is pending */
356 static void apic_update_irq(APICState *s)
359 if (!(s->spurious_vec & APIC_SV_ENABLE))
361 irrv = get_highest_priority_int(s->irr);
364 ppr = apic_get_ppr(s);
365 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
367 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
370 void apic_reset_irq_delivered(void)
372 apic_irq_delivered = 0;
375 int apic_get_irq_delivered(void)
377 return apic_irq_delivered;
380 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
382 apic_irq_delivered += !get_bit(s->irr, vector_num);
384 set_bit(s->irr, vector_num);
386 set_bit(s->tmr, vector_num);
388 reset_bit(s->tmr, vector_num);
392 static void apic_eoi(APICState *s)
395 isrv = get_highest_priority_int(s->isr);
398 reset_bit(s->isr, isrv);
399 /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
400 set the remote IRR bit for level triggered interrupts. */
404 static int apic_find_dest(uint8_t dest)
406 APICState *apic = local_apics[dest];
409 if (apic && apic->id == dest)
410 return dest; /* shortcut in case apic->id == apic->idx */
412 for (i = 0; i < MAX_APICS; i++) {
413 apic = local_apics[i];
414 if (apic && apic->id == dest)
421 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
422 uint8_t dest, uint8_t dest_mode)
424 APICState *apic_iter;
427 if (dest_mode == 0) {
429 memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
431 int idx = apic_find_dest(dest);
432 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
434 set_bit(deliver_bitmask, idx);
437 /* XXX: cluster mode */
438 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
439 for(i = 0; i < MAX_APICS; i++) {
440 apic_iter = local_apics[i];
442 if (apic_iter->dest_mode == 0xf) {
443 if (dest & apic_iter->log_dest)
444 set_bit(deliver_bitmask, i);
445 } else if (apic_iter->dest_mode == 0x0) {
446 if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
447 (dest & apic_iter->log_dest & 0x0f)) {
448 set_bit(deliver_bitmask, i);
457 static void apic_init_ipi(APICState *s)
462 s->spurious_vec = 0xff;
465 memset(s->isr, 0, sizeof(s->isr));
466 memset(s->tmr, 0, sizeof(s->tmr));
467 memset(s->irr, 0, sizeof(s->irr));
468 for(i = 0; i < APIC_LVT_NB; i++)
469 s->lvt[i] = 1 << 16; /* mask LVT */
471 memset(s->icr, 0, sizeof(s->icr));
474 s->initial_count = 0;
475 s->initial_count_load_time = 0;
478 cpu_reset(s->cpu_env);
480 s->cpu_env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP);
483 /* send a SIPI message to the CPU to start it */
484 static void apic_startup(APICState *s, int vector_num)
486 CPUState *env = s->cpu_env;
490 cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
495 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
496 uint8_t delivery_mode, uint8_t vector_num,
497 uint8_t polarity, uint8_t trigger_mode)
499 uint32_t deliver_bitmask[MAX_APIC_WORDS];
500 int dest_shorthand = (s->icr[0] >> 18) & 3;
501 APICState *apic_iter;
503 switch (dest_shorthand) {
505 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
508 memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
509 set_bit(deliver_bitmask, s->idx);
512 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
515 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
516 reset_bit(deliver_bitmask, s->idx);
520 switch (delivery_mode) {
523 int trig_mode = (s->icr[0] >> 15) & 1;
524 int level = (s->icr[0] >> 14) & 1;
525 if (level == 0 && trig_mode == 1) {
526 foreach_apic(apic_iter, deliver_bitmask,
527 apic_iter->arb_id = apic_iter->id );
534 foreach_apic(apic_iter, deliver_bitmask,
535 apic_startup(apic_iter, vector_num) );
539 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
543 int apic_get_interrupt(CPUState *env)
545 APICState *s = env->apic_state;
548 /* if the APIC is installed or enabled, we let the 8259 handle the
552 if (!(s->spurious_vec & APIC_SV_ENABLE))
555 /* XXX: spurious IRQ handling */
556 intno = get_highest_priority_int(s->irr);
559 if (s->tpr && intno <= s->tpr)
560 return s->spurious_vec & 0xff;
561 reset_bit(s->irr, intno);
562 set_bit(s->isr, intno);
567 int apic_accept_pic_intr(CPUState *env)
569 APICState *s = env->apic_state;
575 lvt0 = s->lvt[APIC_LVT_LINT0];
577 if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
578 (lvt0 & APIC_LVT_MASKED) == 0)
584 static uint32_t apic_get_current_count(APICState *s)
588 d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
590 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
592 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
594 if (d >= s->initial_count)
597 val = s->initial_count - d;
602 static void apic_timer_update(APICState *s, int64_t current_time)
604 int64_t next_time, d;
606 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
607 d = (current_time - s->initial_count_load_time) >>
609 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
610 if (!s->initial_count)
612 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
614 if (d >= s->initial_count)
616 d = (uint64_t)s->initial_count + 1;
618 next_time = s->initial_count_load_time + (d << s->count_shift);
619 qemu_mod_timer(s->timer, next_time);
620 s->next_time = next_time;
623 qemu_del_timer(s->timer);
627 static void apic_timer(void *opaque)
629 APICState *s = opaque;
631 apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
632 apic_timer_update(s, s->next_time);
635 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
640 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
645 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
649 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
653 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
660 env = cpu_single_env;
665 index = (addr >> 4) & 0xff;
670 case 0x03: /* version */
671 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
677 val = apic_get_arb_pri(s);
681 val = apic_get_ppr(s);
687 val = s->log_dest << 24;
690 val = s->dest_mode << 28;
693 val = s->spurious_vec;
696 val = s->isr[index & 7];
699 val = s->tmr[index & 7];
702 val = s->irr[index & 7];
709 val = s->icr[index & 1];
712 val = s->lvt[index - 0x32];
715 val = s->initial_count;
718 val = apic_get_current_count(s);
721 val = s->divide_conf;
724 s->esr |= ESR_ILLEGAL_ADDRESS;
729 printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
734 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
740 env = cpu_single_env;
746 printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
749 index = (addr >> 4) & 0xff;
767 s->log_dest = val >> 24;
770 s->dest_mode = val >> 28;
773 s->spurious_vec = val & 0x1ff;
783 apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
784 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
785 (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
792 int n = index - 0x32;
794 if (n == APIC_LVT_TIMER)
795 apic_timer_update(s, qemu_get_clock(vm_clock));
799 s->initial_count = val;
800 s->initial_count_load_time = qemu_get_clock(vm_clock);
801 apic_timer_update(s, s->initial_count_load_time);
808 s->divide_conf = val & 0xb;
809 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
810 s->count_shift = (v + 1) & 7;
814 s->esr |= ESR_ILLEGAL_ADDRESS;
819 static void apic_save(QEMUFile *f, void *opaque)
821 APICState *s = opaque;
824 qemu_put_be32s(f, &s->apicbase);
825 qemu_put_8s(f, &s->id);
826 qemu_put_8s(f, &s->arb_id);
827 qemu_put_8s(f, &s->tpr);
828 qemu_put_be32s(f, &s->spurious_vec);
829 qemu_put_8s(f, &s->log_dest);
830 qemu_put_8s(f, &s->dest_mode);
831 for (i = 0; i < 8; i++) {
832 qemu_put_be32s(f, &s->isr[i]);
833 qemu_put_be32s(f, &s->tmr[i]);
834 qemu_put_be32s(f, &s->irr[i]);
836 for (i = 0; i < APIC_LVT_NB; i++) {
837 qemu_put_be32s(f, &s->lvt[i]);
839 qemu_put_be32s(f, &s->esr);
840 qemu_put_be32s(f, &s->icr[0]);
841 qemu_put_be32s(f, &s->icr[1]);
842 qemu_put_be32s(f, &s->divide_conf);
843 qemu_put_be32(f, s->count_shift);
844 qemu_put_be32s(f, &s->initial_count);
845 qemu_put_be64(f, s->initial_count_load_time);
846 qemu_put_be64(f, s->next_time);
848 qemu_put_timer(f, s->timer);
851 static int apic_load(QEMUFile *f, void *opaque, int version_id)
853 APICState *s = opaque;
859 /* XXX: what if the base changes? (registered memory regions) */
860 qemu_get_be32s(f, &s->apicbase);
861 qemu_get_8s(f, &s->id);
862 qemu_get_8s(f, &s->arb_id);
863 qemu_get_8s(f, &s->tpr);
864 qemu_get_be32s(f, &s->spurious_vec);
865 qemu_get_8s(f, &s->log_dest);
866 qemu_get_8s(f, &s->dest_mode);
867 for (i = 0; i < 8; i++) {
868 qemu_get_be32s(f, &s->isr[i]);
869 qemu_get_be32s(f, &s->tmr[i]);
870 qemu_get_be32s(f, &s->irr[i]);
872 for (i = 0; i < APIC_LVT_NB; i++) {
873 qemu_get_be32s(f, &s->lvt[i]);
875 qemu_get_be32s(f, &s->esr);
876 qemu_get_be32s(f, &s->icr[0]);
877 qemu_get_be32s(f, &s->icr[1]);
878 qemu_get_be32s(f, &s->divide_conf);
879 s->count_shift=qemu_get_be32(f);
880 qemu_get_be32s(f, &s->initial_count);
881 s->initial_count_load_time=qemu_get_be64(f);
882 s->next_time=qemu_get_be64(f);
885 qemu_get_timer(f, s->timer);
889 static void apic_reset(void *opaque)
891 APICState *s = opaque;
892 int bsp = cpu_is_bsp(s->cpu_env);
894 s->apicbase = 0xfee00000 |
895 (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
901 * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
902 * time typically by BIOS, so PIC interrupt can be delivered to the
903 * processor when local APIC is enabled.
905 s->lvt[APIC_LVT_LINT0] = 0x700;
909 static CPUReadMemoryFunc *apic_mem_read[3] = {
915 static CPUWriteMemoryFunc *apic_mem_write[3] = {
921 int apic_init(CPUState *env)
925 if (last_apic_idx >= MAX_APICS)
927 s = qemu_mallocz(sizeof(APICState));
929 s->idx = last_apic_idx++;
930 s->id = env->cpuid_apic_id;
935 /* XXX: mapping more APICs at the same memory location */
936 if (apic_io_memory == 0) {
937 /* NOTE: the APIC is directly connected to the CPU - it is not
938 on the global memory bus. */
939 apic_io_memory = cpu_register_io_memory(apic_mem_read,
940 apic_mem_write, NULL);
941 cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
944 s->timer = qemu_new_timer(vm_clock, apic_timer, s);
946 register_savevm("apic", s->idx, 2, apic_save, apic_load, s);
947 qemu_register_reset(apic_reset, 0, s);
949 local_apics[s->idx] = s;