2 * QEMU i8255x (PRO100) emulation
4 * Copyright (c) 2006-2007 Stefan Weil
6 * Portions of the code are copies from grub / etherboot eepro100.c
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
22 * Tested features (i82559):
23 * PXE boot (i386) no valid link
24 * Linux networking (i386) ok
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
36 #if defined(TARGET_I386)
37 # warning "PXE boot still not working!"
40 #include <stddef.h> /* offsetof */
45 #include "eeprom93xx.h"
47 /* Common declarations for all PCI devices. */
49 #define PCI_CONFIG_8(offset, value) \
50 (pci_conf[offset] = (value))
51 #define PCI_CONFIG_16(offset, value) \
52 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
53 #define PCI_CONFIG_32(offset, value) \
54 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
58 /* debug EEPRO100 card */
59 //~ #define DEBUG_EEPRO100
62 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
64 #define logout(fmt, ...) ((void)0)
67 /* Set flags to 0 to disable debug output. */
70 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
72 #define missing(text) assert(!"feature is missing in this emulation: " text)
74 #define MAX_ETH_FRAME_SIZE 1514
76 /* This driver supports several different devices which are declared here. */
77 #define i82551 0x82551
78 #define i82557B 0x82557b
79 #define i82557C 0x82557c
80 #define i82558B 0x82558b
81 #define i82559C 0x82559c
82 #define i82559ER 0x82559e
83 #define i82562 0x82562
85 #define EEPROM_SIZE 64
87 #define PCI_MEM_SIZE (4 * KiB)
88 #define PCI_IO_SIZE 64
89 #define PCI_FLASH_SIZE (128 * KiB)
91 #define BIT(n) (1 << (n))
92 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
94 /* The SCB accepts the following controls for the Tx and Rx units: */
95 #define CU_NOP 0x0000 /* No operation. */
96 #define CU_START 0x0010 /* CU start. */
97 #define CU_RESUME 0x0020 /* CU resume. */
98 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
99 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
100 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
101 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
102 #define CU_SRESUME 0x00a0 /* CU static resume. */
104 #define RU_NOP 0x0000
105 #define RX_START 0x0001
106 #define RX_RESUME 0x0002
107 #define RX_ABORT 0x0004
108 #define RX_ADDR_LOAD 0x0006
109 #define RX_RESUMENR 0x0007
110 #define INT_MASK 0x0100
111 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
113 /* Offsets to the various registers.
114 All accesses need not be longword aligned. */
115 enum speedo_offsets {
118 SCBCmd = 2, /* Rx/Command Unit command and status. */
120 SCBPointer = 4, /* General purpose pointer. */
121 SCBPort = 8, /* Misc. commands and operands. */
122 SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */
123 SCBCtrlMDI = 16, /* MDI interface control. */
124 SCBEarlyRx = 20, /* Early receive byte count. */
128 /* A speedo3 transmit buffer descriptor with two buffers... */
132 uint32_t link; /* void * */
133 uint32_t tx_desc_addr; /* transmit buffer decsriptor array address. */
134 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
135 uint8_t tx_threshold; /* transmit threshold */
136 uint8_t tbd_count; /* TBD number */
137 //~ /* This constitutes two "TBD" entries: hdr and data */
138 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
139 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
140 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
141 //~ int32_t tx_buf_size1; /* Length of Tx data. */
144 /* Receive frame descriptor. */
148 uint32_t link; /* struct RxFD * */
149 uint32_t rx_buf_addr; /* void * */
152 char packet[MAX_ETH_FRAME_SIZE + 4];
156 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
157 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
158 tx_multiple_collisions, tx_total_collisions;
159 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
160 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
161 rx_short_frame_errors;
162 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
163 uint16_t xmt_tco_frames, rcv_tco_frames;
199 uint8_t phys[6]; /* mac address */
201 uint8_t mult[8]; /* multicast mask array */
205 uint8_t scb_stat; /* SCB stat/ack byte */
206 uint8_t int_stat; /* PCI interrupt status */
207 uint32_t region[3]; /* PCI region addresses */
209 uint32_t statcounter[19];
212 uint32_t device; /* device variant */
214 /* (cu_base + cu_offset) address the next command block in the command block list. */
215 uint32_t cu_base; /* CU base address */
216 uint32_t cu_offset; /* CU address offset */
217 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
218 uint32_t ru_base; /* RU base address */
219 uint32_t ru_offset; /* RU address offset */
220 uint32_t statsaddr; /* pointer to eepro100_stats_t */
221 eepro100_stats_t statistics; /* statistical counters */
226 /* Configuration bytes. */
227 uint8_t configuration[22];
229 /* Data in mem is always in the byte order of the controller (le). */
230 uint8_t mem[PCI_MEM_SIZE];
233 /* Default values for MDI (PHY) registers */
234 static const uint16_t eepro100_mdi_default[] = {
235 /* MDI Registers 0 - 6, 7 */
236 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
237 /* MDI Registers 8 - 15 */
238 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
239 /* MDI Registers 16 - 31 */
240 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
241 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
244 /* Readonly mask for MDI (PHY) registers */
245 static const uint16_t eepro100_mdi_mask[] = {
246 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
247 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
248 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
249 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
252 #define POLYNOMIAL 0x04c11db6
256 static int compute_mcast_idx(const uint8_t * ep)
263 for (i = 0; i < 6; i++) {
265 for (j = 0; j < 8; j++) {
266 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
270 crc = ((crc ^ POLYNOMIAL) | carry);
276 #if defined(DEBUG_EEPRO100)
277 static const char *nic_dump(const uint8_t * buf, unsigned size)
279 static char dump[3 * 16 + 1];
284 p += sprintf(p, " %02x", *buf++);
288 #endif /* DEBUG_EEPRO100 */
291 stat_ack_not_ours = 0x00,
292 stat_ack_sw_gen = 0x04,
294 stat_ack_cu_idle = 0x20,
295 stat_ack_frame_rx = 0x40,
296 stat_ack_cu_cmd_done = 0x80,
297 stat_ack_not_present = 0xFF,
298 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
299 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
302 static void disable_interrupt(EEPRO100State * s)
305 logout("interrupt disabled\n");
306 qemu_irq_lower(s->dev.irq[0]);
311 static void enable_interrupt(EEPRO100State * s)
314 logout("interrupt enabled\n");
315 qemu_irq_raise(s->dev.irq[0]);
320 static void eepro100_acknowledge(EEPRO100State * s)
322 s->scb_stat &= ~s->mem[SCBAck];
323 s->mem[SCBAck] = s->scb_stat;
324 if (s->scb_stat == 0) {
325 disable_interrupt(s);
329 static void eepro100_interrupt(EEPRO100State * s, uint8_t stat)
331 uint8_t mask = ~s->mem[SCBIntmask];
332 s->mem[SCBAck] |= stat;
333 stat = s->scb_stat = s->mem[SCBAck];
334 stat &= (mask | 0x0f);
335 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
336 if (stat && (mask & 0x01)) {
337 /* SCB mask and SCB Bit M do not disable interrupt. */
339 } else if (s->int_stat) {
340 disable_interrupt(s);
344 static void eepro100_cx_interrupt(EEPRO100State * s)
346 /* CU completed action command. */
347 /* Transmit not ok (82557 only, not in emulation). */
348 eepro100_interrupt(s, 0x80);
351 static void eepro100_cna_interrupt(EEPRO100State * s)
353 /* CU left the active state. */
354 eepro100_interrupt(s, 0x20);
357 static void eepro100_fr_interrupt(EEPRO100State * s)
359 /* RU received a complete frame. */
360 eepro100_interrupt(s, 0x40);
364 static void eepro100_rnr_interrupt(EEPRO100State * s)
366 /* RU is not ready. */
367 eepro100_interrupt(s, 0x10);
371 static void eepro100_mdi_interrupt(EEPRO100State * s)
373 /* MDI completed read or write cycle. */
374 eepro100_interrupt(s, 0x08);
377 static void eepro100_swi_interrupt(EEPRO100State * s)
379 /* Software has requested an interrupt. */
380 eepro100_interrupt(s, 0x04);
384 static void eepro100_fcp_interrupt(EEPRO100State * s)
386 /* Flow control pause interrupt (82558 and later). */
387 eepro100_interrupt(s, 0x01);
391 static void pci_reset(EEPRO100State * s)
393 uint32_t device = s->device;
394 uint8_t *pci_conf = s->dev.config;
399 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
401 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
403 PCI_CONFIG_16(PCI_COMMAND, 0x0000);
405 PCI_CONFIG_16(PCI_STATUS, 0x2800);
406 /* PCI Revision ID */
407 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
409 PCI_CONFIG_8(0x09, 0x00);
410 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
411 /* PCI Cache Line Size */
412 /* check cache line size!!! */
413 //~ PCI_CONFIG_8(0x0c, 0x00);
414 /* PCI Latency Timer */
415 PCI_CONFIG_8(0x0d, 0x20); // latency timer = 32 clocks
416 /* PCI Header Type */
417 /* BIST (built-in self test) */
418 #if defined(TARGET_I386)
419 // !!! workaround for buggy bios
420 //~ #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0
423 /* PCI Base Address Registers */
424 /* CSR Memory Mapped Base Address */
425 PCI_CONFIG_32(PCI_BASE_ADDRESS_0,
426 PCI_ADDRESS_SPACE_MEM | PCI_ADDRESS_SPACE_MEM_PREFETCH);
427 /* CSR I/O Mapped Base Address */
428 PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_ADDRESS_SPACE_IO);
430 /* Flash Memory Mapped Base Address */
431 PCI_CONFIG_32(PCI_BASE_ADDRESS_2, 0xfffe0000 | PCI_ADDRESS_SPACE_MEM);
434 /* Expansion ROM Base Address (depends on boot disable!!!) */
435 PCI_CONFIG_32(0x30, 0x00000000);
436 /* Capability Pointer */
437 PCI_CONFIG_8(0x34, 0xdc);
439 PCI_CONFIG_8(0x3d, 1); // interrupt pin 0
441 PCI_CONFIG_8(0x3e, 0x08);
442 /* Maximum Latency */
443 PCI_CONFIG_8(0x3f, 0x18);
444 /* Power Management Capabilities / Next Item Pointer / Capability ID */
445 PCI_CONFIG_32(0xdc, 0x7e210001);
449 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1209);
450 PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
453 PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
454 PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
457 PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
458 PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
461 PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
462 PCI_CONFIG_16(PCI_STATUS, 0x2810);
463 PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
466 PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
467 PCI_CONFIG_16(PCI_STATUS, 0x2810);
468 //~ PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
471 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1209);
472 PCI_CONFIG_16(PCI_STATUS, 0x2810);
473 PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
475 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1029);
476 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1030); /* 82559 InBusiness 10/100 */
478 logout("Device %X is undefined!\n", device);
481 if (device == i82557C || device == i82558B || device == i82559C) {
482 logout("Get device id and revision from EEPROM!!!\n");
486 static void nic_selective_reset(EEPRO100State * s)
489 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
490 //~ eeprom93xx_reset(s->eeprom);
491 memcpy(eeprom_contents, s->macaddr, 6);
492 eeprom_contents[0xa] = 0x4000;
494 for (i = 0; i < EEPROM_SIZE - 1; i++) {
495 sum += eeprom_contents[i];
497 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
499 memset(s->mem, 0, sizeof(s->mem));
500 uint32_t val = BIT(21);
501 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
503 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
504 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
507 static void nic_reset(void *opaque)
509 EEPRO100State *s = opaque;
515 nic_selective_reset(s);
518 #if defined(DEBUG_EEPRO100)
519 static const char *reg[PCI_IO_SIZE / 4] = {
523 "EEPROM/Flash Control",
525 "Receive DMA Byte Count",
526 "Flow control register",
527 "General Status/Control"
530 static char *regname(uint32_t addr)
533 if (addr < PCI_IO_SIZE) {
534 const char *r = reg[addr / 4];
536 sprintf(buf, "%s+%u", r, addr % 4);
538 sprintf(buf, "0x%02x", addr);
541 sprintf(buf, "??? 0x%08x", addr);
545 #endif /* DEBUG_EEPRO100 */
548 static uint16_t eepro100_read_status(EEPRO100State * s)
550 uint16_t val = s->status;
551 logout("val=0x%04x\n", val);
555 static void eepro100_write_status(EEPRO100State * s, uint16_t val)
557 logout("val=0x%04x\n", val);
562 /*****************************************************************************
566 ****************************************************************************/
569 static uint16_t eepro100_read_command(EEPRO100State * s)
571 uint16_t val = 0xffff;
572 //~ logout("val=0x%04x\n", val);
577 /* Commands that can be put in a command list entry. */
582 CmdMulticastList = 3,
584 CmdTDR = 5, /* load microcode */
588 /* And some extra flags: */
589 CmdSuspend = 0x4000, /* Suspend after completion. */
590 CmdIntr = 0x2000, /* Interrupt after completion. */
591 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
594 static cu_state_t get_cu_state(EEPRO100State * s)
596 return ((s->mem[SCBStatus] >> 6) & 0x03);
599 static void set_cu_state(EEPRO100State * s, cu_state_t state)
601 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6);
604 static ru_state_t get_ru_state(EEPRO100State * s)
606 return ((s->mem[SCBStatus] >> 2) & 0x0f);
609 static void set_ru_state(EEPRO100State * s, ru_state_t state)
611 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2);
614 static void dump_statistics(EEPRO100State * s)
616 /* Dump statistical data. Most data is never changed by the emulation
617 * and always 0, so we first just copy the whole block and then those
618 * values which really matter.
619 * Number of data should check configuration!!!
621 cpu_physical_memory_write(s->statsaddr, (uint8_t *) & s->statistics, 64);
622 stl_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
623 stl_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
624 stl_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
625 stl_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
626 //~ stw_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
627 //~ stw_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
628 //~ missing("CU dump statistical counters");
631 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
640 if (get_cu_state(s) != cu_idle) {
641 /* Intel documentation says that CU must be idle for the CU
642 * start command. Intel driver for Linux also starts the CU
643 * from suspended state. */
644 logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
645 //~ assert(!"wrong CU state");
647 set_cu_state(s, cu_active);
648 s->cu_offset = s->pointer;
650 cb_address = s->cu_base + s->cu_offset;
651 cpu_physical_memory_read(cb_address, (uint8_t *) & tx, sizeof(tx));
652 uint16_t status = le16_to_cpu(tx.status);
653 uint16_t command = le16_to_cpu(tx.command);
655 ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
656 val, status, command, tx.link);
657 bool bit_el = ((command & 0x8000) != 0);
658 bool bit_s = ((command & 0x4000) != 0);
659 bool bit_i = ((command & 0x2000) != 0);
660 bool bit_nc = ((command & 0x0010) != 0);
661 //~ bool bit_sf = ((command & 0x0008) != 0);
662 uint16_t cmd = command & 0x0007;
663 s->cu_offset = le32_to_cpu(tx.link);
669 cpu_physical_memory_read(cb_address + 8, &s->macaddr[0], 6);
670 logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6));
673 cpu_physical_memory_read(cb_address + 8, &s->configuration[0],
674 sizeof(s->configuration));
675 logout("configuration: %s\n", nic_dump(&s->configuration[0], 16));
677 case CmdMulticastList:
678 //~ missing("multicast list");
682 uint32_t tbd_array = le32_to_cpu(tx.tx_desc_addr);
683 uint16_t tcb_bytes = (le16_to_cpu(tx.tcb_bytes) & 0x3fff);
685 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
686 tbd_array, tcb_bytes, tx.tbd_count);
689 assert(tcb_bytes <= 2600);
690 /* Next assertion fails for local configuration. */
691 //~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff));
692 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
694 ("illegal values of TBD array address and TCB byte count!\n");
696 // sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes
699 uint32_t tbd_address = cb_address + 0x10;
700 assert(tcb_bytes <= sizeof(buf));
701 while (size < tcb_bytes) {
702 uint32_t tx_buffer_address = ldl_phys(tbd_address);
703 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
704 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
707 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
708 tx_buffer_address, tx_buffer_size);
709 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
710 cpu_physical_memory_read(tx_buffer_address, &buf[size],
712 size += tx_buffer_size;
714 if (tbd_array == 0xffffffff) {
715 /* Simplified mode. Was already handled by code above. */
718 uint8_t tbd_count = 0;
719 if ((s->device >= i82558B) && !(s->configuration[6] & BIT(4))) {
720 /* Extended Flexible TCB. */
721 assert(tcb_bytes == 0);
722 for (; tbd_count < 2; tbd_count++) {
723 uint32_t tx_buffer_address = ldl_phys(tbd_address);
724 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
725 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
728 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
729 tx_buffer_address, tx_buffer_size);
730 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
731 cpu_physical_memory_read(tx_buffer_address, &buf[size],
733 size += tx_buffer_size;
734 if (tx_buffer_el & 1) {
739 tbd_address = tbd_array;
740 for (; tbd_count < tx.tbd_count; tbd_count++) {
741 uint32_t tx_buffer_address = ldl_phys(tbd_address);
742 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
743 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
746 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
747 tx_buffer_address, tx_buffer_size);
748 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
749 cpu_physical_memory_read(tx_buffer_address, &buf[size],
751 size += tx_buffer_size;
752 if (tx_buffer_el & 1) {
757 qemu_send_packet(s->vc, buf, size);
758 s->statistics.tx_good_frames++;
759 /* Transmit with bad status would raise an CX/TNO interrupt.
760 * (82557 only). Emulation never has bad status. */
761 //~ eepro100_cx_interrupt(s);
764 logout("load microcode\n");
765 /* Starting with offset 8, the command contains
766 * 64 dwords microcode which we just ignore here. */
769 missing("undefined command");
771 /* Write new status (success). */
772 stw_phys(cb_address, status | 0x8000 | 0x2000);
774 /* CU completed action. */
775 eepro100_cx_interrupt(s);
778 /* CU becomes idle. */
779 set_cu_state(s, cu_idle);
780 eepro100_cna_interrupt(s);
782 /* CU becomes suspended. */
783 set_cu_state(s, cu_suspended);
784 eepro100_cna_interrupt(s);
786 /* More entries in list. */
787 logout("CU list with at least one more entry\n");
790 logout("CU list empty\n");
791 /* List is empty. Now CU is idle or suspended. */
794 if (get_cu_state(s) != cu_suspended) {
795 logout("bad CU resume from CU state %u\n", get_cu_state(s));
796 /* Workaround for bad Linux eepro100 driver which resumes
797 * from idle state. */
798 //~ missing("cu resume");
799 set_cu_state(s, cu_suspended);
801 if (get_cu_state(s) == cu_suspended) {
802 logout("CU resuming\n");
803 set_cu_state(s, cu_active);
808 /* Load dump counters address. */
809 s->statsaddr = s->pointer;
810 logout("val=0x%02x (status address)\n", val);
813 /* Dump statistical counters. */
818 logout("val=0x%02x (CU base address)\n", val);
819 s->cu_base = s->pointer;
822 /* Dump and reset statistical counters. */
824 memset(&s->statistics, 0, sizeof(s->statistics));
827 /* CU static resume. */
828 missing("CU static resume");
831 missing("Undefined CU command");
835 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
843 if (get_ru_state(s) != ru_idle) {
844 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
845 //~ assert(!"wrong RU state");
847 set_ru_state(s, ru_ready);
848 s->ru_offset = s->pointer;
849 logout("val=0x%02x (rx start)\n", val);
853 if (get_ru_state(s) != ru_suspended) {
854 logout("RU state is %u, should be %u\n", get_ru_state(s),
856 //~ assert(!"wrong RU state");
858 set_ru_state(s, ru_ready);
862 logout("val=0x%02x (RU base address)\n", val);
863 s->ru_base = s->pointer;
866 logout("val=0x%02x (undefined RU command)\n", val);
867 missing("Undefined SU command");
871 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
873 eepro100_ru_command(s, val & 0x0f);
874 eepro100_cu_command(s, val & 0xf0);
876 logout("val=0x%02x\n", val);
878 /* Clear command byte after command was accepted. */
882 /*****************************************************************************
886 ****************************************************************************/
888 #define EEPROM_CS 0x02
889 #define EEPROM_SK 0x01
890 #define EEPROM_DI 0x04
891 #define EEPROM_DO 0x08
893 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
896 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
897 if (eeprom93xx_read(s->eeprom)) {
905 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
907 logout("write val=0x%02x\n", val);
909 /* mask unwriteable bits */
910 //~ val = SET_MASKED(val, 0x31, eeprom->value);
912 int eecs = ((val & EEPROM_CS) != 0);
913 int eesk = ((val & EEPROM_SK) != 0);
914 int eedi = ((val & EEPROM_DI) != 0);
915 eeprom93xx_write(eeprom, eecs, eesk, eedi);
918 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
920 s->pointer = le32_to_cpu(val);
921 logout("val=0x%08x\n", val);
924 /*****************************************************************************
928 ****************************************************************************/
930 #if defined(DEBUG_EEPRO100)
931 static const char *mdi_op_name[] = {
938 static const char *mdi_reg_name[] = {
941 "PHY Identification (Word 1)",
942 "PHY Identification (Word 2)",
943 "Auto-Negotiation Advertisement",
944 "Auto-Negotiation Link Partner Ability",
945 "Auto-Negotiation Expansion"
947 #endif /* DEBUG_EEPRO100 */
949 static uint32_t eepro100_read_mdi(EEPRO100State * s)
952 memcpy(&val, &s->mem[0x10], sizeof(val));
954 #ifdef DEBUG_EEPRO100
955 uint8_t raiseint = (val & BIT(29)) >> 29;
956 uint8_t opcode = (val & BITS(27, 26)) >> 26;
957 uint8_t phy = (val & BITS(25, 21)) >> 21;
958 uint8_t reg = (val & BITS(20, 16)) >> 16;
959 uint16_t data = (val & BITS(15, 0));
961 /* Emulation takes no time to finish MDI transaction. */
963 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
964 val, raiseint, mdi_op_name[opcode], phy,
965 mdi_reg_name[reg], data));
969 //~ #define BITS(val, upper, lower) (val & ???)
970 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
972 uint8_t raiseint = (val & BIT(29)) >> 29;
973 uint8_t opcode = (val & BITS(27, 26)) >> 26;
974 uint8_t phy = (val & BITS(25, 21)) >> 21;
975 uint8_t reg = (val & BITS(20, 16)) >> 16;
976 uint16_t data = (val & BITS(15, 0));
978 /* Unsupported PHY address. */
979 //~ logout("phy must be 1 but is %u\n", phy);
981 } else if (opcode != 1 && opcode != 2) {
982 /* Unsupported opcode. */
983 logout("opcode must be 1 or 2 but is %u\n", opcode);
985 } else if (reg > 6) {
986 /* Unsupported register. */
987 logout("register must be 0...6 but is %u\n", reg);
990 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
991 val, raiseint, mdi_op_name[opcode], phy,
992 mdi_reg_name[reg], data));
996 case 0: /* Control Register */
998 /* Reset status and control registers to default. */
999 s->mdimem[0] = eepro100_mdi_default[0];
1000 s->mdimem[1] = eepro100_mdi_default[1];
1001 data = s->mdimem[reg];
1003 /* Restart Auto Configuration = Normal Operation */
1007 case 1: /* Status Register */
1008 missing("not writable");
1009 data = s->mdimem[reg];
1011 case 2: /* PHY Identification Register (Word 1) */
1012 case 3: /* PHY Identification Register (Word 2) */
1013 missing("not implemented");
1015 case 4: /* Auto-Negotiation Advertisement Register */
1016 case 5: /* Auto-Negotiation Link Partner Ability Register */
1018 case 6: /* Auto-Negotiation Expansion Register */
1020 missing("not implemented");
1022 s->mdimem[reg] = data;
1023 } else if (opcode == 2) {
1026 case 0: /* Control Register */
1027 if (data & 0x8000) {
1028 /* Reset status and control registers to default. */
1029 s->mdimem[0] = eepro100_mdi_default[0];
1030 s->mdimem[1] = eepro100_mdi_default[1];
1033 case 1: /* Status Register */
1034 s->mdimem[reg] |= 0x0020;
1036 case 2: /* PHY Identification Register (Word 1) */
1037 case 3: /* PHY Identification Register (Word 2) */
1038 case 4: /* Auto-Negotiation Advertisement Register */
1040 case 5: /* Auto-Negotiation Link Partner Ability Register */
1041 s->mdimem[reg] = 0x41fe;
1043 case 6: /* Auto-Negotiation Expansion Register */
1044 s->mdimem[reg] = 0x0001;
1047 data = s->mdimem[reg];
1049 /* Emulation takes no time to finish MDI transaction.
1050 * Set MDI bit in SCB status register. */
1051 s->mem[SCBAck] |= 0x08;
1054 eepro100_mdi_interrupt(s);
1057 val = (val & 0xffff0000) + data;
1058 memcpy(&s->mem[0x10], &val, sizeof(val));
1061 /*****************************************************************************
1065 ****************************************************************************/
1067 #define PORT_SOFTWARE_RESET 0
1068 #define PORT_SELFTEST 1
1069 #define PORT_SELECTIVE_RESET 2
1071 #define PORT_SELECTION_MASK 3
1074 uint32_t st_sign; /* Self Test Signature */
1075 uint32_t st_result; /* Self Test Results */
1076 } eepro100_selftest_t;
1078 static uint32_t eepro100_read_port(EEPRO100State * s)
1083 static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1085 val = le32_to_cpu(val);
1086 uint32_t address = (val & ~PORT_SELECTION_MASK);
1087 uint8_t selection = (val & PORT_SELECTION_MASK);
1088 switch (selection) {
1089 case PORT_SOFTWARE_RESET:
1093 logout("selftest address=0x%08x\n", address);
1094 eepro100_selftest_t data;
1095 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1096 data.st_sign = 0xffffffff;
1098 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1100 case PORT_SELECTIVE_RESET:
1101 logout("selective reset, selftest address=0x%08x\n", address);
1102 nic_selective_reset(s);
1105 logout("val=0x%08x\n", val);
1106 missing("unknown port selection");
1110 /*****************************************************************************
1112 * General hardware emulation.
1114 ****************************************************************************/
1116 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1119 if (addr <= sizeof(s->mem) - sizeof(val)) {
1120 memcpy(&val, &s->mem[addr], sizeof(val));
1125 //~ val = eepro100_read_status(s);
1126 logout("addr=%s val=0x%02x\n", regname(addr), val);
1129 //~ val = eepro100_read_status(s);
1130 logout("addr=%s val=0x%02x\n", regname(addr), val);
1133 logout("addr=%s val=0x%02x\n", regname(addr), val);
1134 //~ val = eepro100_read_command(s);
1137 logout("addr=%s val=0x%02x\n", regname(addr), val);
1140 logout("addr=%s val=0x%02x\n", regname(addr), val);
1143 val = eepro100_read_eeprom(s);
1145 case 0x1b: /* PMDR (power management driver register) */
1147 logout("addr=%s val=0x%02x\n", regname(addr), val);
1149 case 0x1d: /* general status register */
1150 /* 100 Mbps full duplex, valid link */
1152 logout("addr=General Status val=%02x\n", val);
1155 logout("addr=%s val=0x%02x\n", regname(addr), val);
1156 missing("unknown byte read");
1161 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1164 if (addr <= sizeof(s->mem) - sizeof(val)) {
1165 memcpy(&val, &s->mem[addr], sizeof(val));
1168 logout("addr=%s val=0x%04x\n", regname(addr), val);
1172 //~ val = eepro100_read_status(s);
1175 val = eepro100_read_eeprom(s);
1178 logout("addr=%s val=0x%04x\n", regname(addr), val);
1179 missing("unknown word read");
1184 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1187 if (addr <= sizeof(s->mem) - sizeof(val)) {
1188 memcpy(&val, &s->mem[addr], sizeof(val));
1193 //~ val = eepro100_read_status(s);
1194 logout("addr=%s val=0x%08x\n", regname(addr), val);
1197 //~ val = eepro100_read_pointer(s);
1198 logout("addr=%s val=0x%08x\n", regname(addr), val);
1201 val = eepro100_read_port(s);
1202 logout("addr=%s val=0x%08x\n", regname(addr), val);
1205 val = eepro100_read_mdi(s);
1208 logout("addr=%s val=0x%08x\n", regname(addr), val);
1209 missing("unknown longword read");
1214 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1216 if (addr <= sizeof(s->mem) - sizeof(val)) {
1217 memcpy(&s->mem[addr], &val, sizeof(val));
1220 logout("addr=%s val=0x%02x\n", regname(addr), val);
1224 //~ eepro100_write_status(s, val);
1227 eepro100_acknowledge(s);
1230 eepro100_write_command(s, val);
1234 eepro100_swi_interrupt(s);
1236 eepro100_interrupt(s, 0);
1243 logout("addr=%s val=0x%02x\n", regname(addr), val);
1246 eepro100_write_eeprom(s->eeprom, val);
1249 logout("addr=%s val=0x%02x\n", regname(addr), val);
1250 missing("unknown byte write");
1254 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1256 if (addr <= sizeof(s->mem) - sizeof(val)) {
1257 memcpy(&s->mem[addr], &val, sizeof(val));
1260 logout("addr=%s val=0x%04x\n", regname(addr), val);
1264 //~ eepro100_write_status(s, val);
1265 eepro100_acknowledge(s);
1268 eepro100_write_command(s, val);
1269 eepro100_write1(s, SCBIntmask, val >> 8);
1272 eepro100_write_eeprom(s->eeprom, val);
1275 logout("addr=%s val=0x%04x\n", regname(addr), val);
1276 missing("unknown word write");
1280 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1282 if (addr <= sizeof(s->mem) - sizeof(val)) {
1283 memcpy(&s->mem[addr], &val, sizeof(val));
1288 eepro100_write_pointer(s, val);
1291 logout("addr=%s val=0x%08x\n", regname(addr), val);
1292 eepro100_write_port(s, val);
1295 eepro100_write_mdi(s, val);
1298 logout("addr=%s val=0x%08x\n", regname(addr), val);
1299 missing("unknown longword write");
1303 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1305 EEPRO100State *s = opaque;
1306 //~ logout("addr=%s\n", regname(addr));
1307 return eepro100_read1(s, addr - s->region[1]);
1310 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1312 EEPRO100State *s = opaque;
1313 return eepro100_read2(s, addr - s->region[1]);
1316 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1318 EEPRO100State *s = opaque;
1319 return eepro100_read4(s, addr - s->region[1]);
1322 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1324 EEPRO100State *s = opaque;
1325 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1326 eepro100_write1(s, addr - s->region[1], val);
1329 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1331 EEPRO100State *s = opaque;
1332 eepro100_write2(s, addr - s->region[1], val);
1335 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1337 EEPRO100State *s = opaque;
1338 eepro100_write4(s, addr - s->region[1], val);
1341 /***********************************************************/
1342 /* PCI EEPRO100 definitions */
1344 static void pci_map(PCIDevice * pci_dev, int region_num,
1345 uint32_t addr, uint32_t size, int type)
1347 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1349 logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1350 region_num, addr, size, type);
1352 assert(region_num == 1);
1353 register_ioport_write(addr, size, 1, ioport_write1, s);
1354 register_ioport_read(addr, size, 1, ioport_read1, s);
1355 register_ioport_write(addr, size, 2, ioport_write2, s);
1356 register_ioport_read(addr, size, 2, ioport_read2, s);
1357 register_ioport_write(addr, size, 4, ioport_write4, s);
1358 register_ioport_read(addr, size, 4, ioport_read4, s);
1360 s->region[region_num] = addr;
1363 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1365 EEPRO100State *s = opaque;
1366 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1367 eepro100_write1(s, addr, val);
1370 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1372 EEPRO100State *s = opaque;
1373 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1374 eepro100_write2(s, addr, val);
1377 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1379 EEPRO100State *s = opaque;
1380 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1381 eepro100_write4(s, addr, val);
1384 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1386 EEPRO100State *s = opaque;
1387 //~ logout("addr=%s\n", regname(addr));
1388 return eepro100_read1(s, addr);
1391 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1393 EEPRO100State *s = opaque;
1394 //~ logout("addr=%s\n", regname(addr));
1395 return eepro100_read2(s, addr);
1398 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1400 EEPRO100State *s = opaque;
1401 //~ logout("addr=%s\n", regname(addr));
1402 return eepro100_read4(s, addr);
1405 static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1411 static CPUReadMemoryFunc * const pci_mmio_read[] = {
1417 static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1418 uint32_t addr, uint32_t size, int type)
1420 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1422 logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1423 region_num, addr, size, type);
1425 if (region_num == 0) {
1426 /* Map control / status registers. */
1427 cpu_register_physical_memory(addr, size, s->mmio_index);
1428 s->region[region_num] = addr;
1432 static int nic_can_receive(VLANClientState *vc)
1434 EEPRO100State *s = vc->opaque;
1436 return get_ru_state(s) == ru_ready;
1437 //~ return !eepro100_buffer_full(s);
1440 static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size)
1443 * - Magic packets should set bit 30 in power management driver register.
1444 * - Interesting packets should set bit 29 in power management driver register.
1446 EEPRO100State *s = vc->opaque;
1447 uint16_t rfd_status = 0xa000;
1448 static const uint8_t broadcast_macaddr[6] =
1449 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1451 /* TODO: check multiple IA bit. */
1452 assert(!(s->configuration[20] & BIT(6)));
1454 if (s->configuration[8] & 0x80) {
1455 /* CSMA is disabled. */
1456 logout("%p received while CSMA is disabled\n", s);
1458 } else if (size < 64 && (s->configuration[7] & 1)) {
1459 /* Short frame and configuration byte 7/0 (discard short receive) set:
1460 * Short frame is discarded */
1461 logout("%p received short frame (%d byte)\n", s, size);
1462 s->statistics.rx_short_frame_errors++;
1464 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) {
1465 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1466 * Long frames are discarded. */
1467 logout("%p received long frame (%d byte), ignored\n", s, size);
1469 } else if (memcmp(buf, s->macaddr, 6) == 0) { // !!!
1470 /* Frame matches individual address. */
1471 /* TODO: check configuration byte 15/4 (ignore U/L). */
1472 logout("%p received frame for me, len=%d\n", s, size);
1473 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1474 /* Broadcast frame. */
1475 logout("%p received broadcast, len=%d\n", s, size);
1476 rfd_status |= 0x0002;
1477 } else if (buf[0] & 0x01) { // !!!
1478 /* Multicast frame. */
1479 logout("%p received multicast, len=%d\n", s, size);
1480 /* TODO: check multicast all bit. */
1481 assert(!(s->configuration[21] & BIT(3)));
1482 int mcast_idx = compute_mcast_idx(buf);
1483 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) {
1486 rfd_status |= 0x0002;
1487 } else if (s->configuration[15] & 1) {
1488 /* Promiscuous: receive all. */
1489 logout("%p received frame in promiscuous mode, len=%d\n", s, size);
1490 rfd_status |= 0x0004;
1492 logout("%p received frame, ignored, len=%d,%s\n", s, size,
1493 nic_dump(buf, size));
1497 if (get_ru_state(s) != ru_ready) {
1498 /* No ressources available. */
1499 logout("no ressources, state=%u\n", get_ru_state(s));
1500 s->statistics.rx_resource_errors++;
1501 //~ assert(!"no ressources");
1505 //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
1507 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
1508 offsetof(eepro100_rx_t, packet));
1509 uint16_t rfd_command = le16_to_cpu(rx.command);
1510 uint16_t rfd_size = le16_to_cpu(rx.size);
1511 assert(size <= rfd_size);
1513 rfd_status |= 0x0080;
1515 logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", rfd_command,
1516 rx.link, rx.rx_buf_addr, rfd_size);
1517 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1519 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1520 /* Early receive interrupt not supported. */
1521 //~ eepro100_er_interrupt(s);
1522 /* Receive CRC Transfer not supported. */
1523 assert(!(s->configuration[18] & 4));
1524 /* TODO: check stripping enable bit. */
1525 //~ assert(!(s->configuration[17] & 1));
1526 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1527 offsetof(eepro100_rx_t, packet), buf, size);
1528 s->statistics.rx_good_frames++;
1529 eepro100_fr_interrupt(s);
1530 s->ru_offset = le32_to_cpu(rx.link);
1531 if (rfd_command & 0x8000) {
1532 /* EL bit is set, so this was the last frame. */
1535 if (rfd_command & 0x4000) {
1537 set_ru_state(s, ru_suspended);
1542 static int nic_load(QEMUFile * f, void *opaque, int version_id)
1544 EEPRO100State *s = opaque;
1551 if (version_id >= 3) {
1552 ret = pci_device_load(&s->dev, f);
1557 if (version_id >= 2) {
1558 qemu_get_8s(f, &s->rxcr);
1563 qemu_get_8s(f, &s->cmd);
1564 qemu_get_be32s(f, &s->start);
1565 qemu_get_be32s(f, &s->stop);
1566 qemu_get_8s(f, &s->boundary);
1567 qemu_get_8s(f, &s->tsr);
1568 qemu_get_8s(f, &s->tpsr);
1569 qemu_get_be16s(f, &s->tcnt);
1570 qemu_get_be16s(f, &s->rcnt);
1571 qemu_get_be32s(f, &s->rsar);
1572 qemu_get_8s(f, &s->rsr);
1573 qemu_get_8s(f, &s->isr);
1574 qemu_get_8s(f, &s->dcfg);
1575 qemu_get_8s(f, &s->imr);
1576 qemu_get_buffer(f, s->phys, 6);
1577 qemu_get_8s(f, &s->curpag);
1578 qemu_get_buffer(f, s->mult, 8);
1579 qemu_get_buffer(f, s->mem, sizeof(s->mem));
1581 /* Restore all members of struct between scv_stat and mem */
1582 qemu_get_8s(f, &s->scb_stat);
1583 qemu_get_8s(f, &s->int_stat);
1584 for (i = 0; i < 3; i++)
1585 qemu_get_be32s(f, &s->region[i]);
1586 qemu_get_buffer(f, s->macaddr, 6);
1587 for (i = 0; i < 19; i++)
1588 qemu_get_be32s(f, &s->statcounter[i]);
1589 for (i = 0; i < 32; i++)
1590 qemu_get_be16s(f, &s->mdimem[i]);
1591 /* The eeprom should be saved and restored by its own routines */
1592 qemu_get_be32s(f, &s->device);
1593 qemu_get_be32s(f, &s->pointer);
1594 qemu_get_be32s(f, &s->cu_base);
1595 qemu_get_be32s(f, &s->cu_offset);
1596 qemu_get_be32s(f, &s->ru_base);
1597 qemu_get_be32s(f, &s->ru_offset);
1598 qemu_get_be32s(f, &s->statsaddr);
1599 /* Restore epro100_stats_t statistics */
1600 qemu_get_be32s(f, &s->statistics.tx_good_frames);
1601 qemu_get_be32s(f, &s->statistics.tx_max_collisions);
1602 qemu_get_be32s(f, &s->statistics.tx_late_collisions);
1603 qemu_get_be32s(f, &s->statistics.tx_underruns);
1604 qemu_get_be32s(f, &s->statistics.tx_lost_crs);
1605 qemu_get_be32s(f, &s->statistics.tx_deferred);
1606 qemu_get_be32s(f, &s->statistics.tx_single_collisions);
1607 qemu_get_be32s(f, &s->statistics.tx_multiple_collisions);
1608 qemu_get_be32s(f, &s->statistics.tx_total_collisions);
1609 qemu_get_be32s(f, &s->statistics.rx_good_frames);
1610 qemu_get_be32s(f, &s->statistics.rx_crc_errors);
1611 qemu_get_be32s(f, &s->statistics.rx_alignment_errors);
1612 qemu_get_be32s(f, &s->statistics.rx_resource_errors);
1613 qemu_get_be32s(f, &s->statistics.rx_overrun_errors);
1614 qemu_get_be32s(f, &s->statistics.rx_cdt_errors);
1615 qemu_get_be32s(f, &s->statistics.rx_short_frame_errors);
1616 qemu_get_be32s(f, &s->statistics.fc_xmt_pause);
1617 qemu_get_be32s(f, &s->statistics.fc_rcv_pause);
1618 qemu_get_be32s(f, &s->statistics.fc_rcv_unsupported);
1619 qemu_get_be16s(f, &s->statistics.xmt_tco_frames);
1620 qemu_get_be16s(f, &s->statistics.rcv_tco_frames);
1621 qemu_get_be32s(f, &s->statistics.complete);
1623 qemu_get_be16s(f, &s->status);
1626 /* Configuration bytes. */
1627 qemu_get_buffer(f, s->configuration, sizeof(s->configuration));
1632 static void nic_save(QEMUFile * f, void *opaque)
1634 EEPRO100State *s = opaque;
1637 pci_device_save(&s->dev, f);
1639 qemu_put_8s(f, &s->rxcr);
1641 qemu_put_8s(f, &s->cmd);
1642 qemu_put_be32s(f, &s->start);
1643 qemu_put_be32s(f, &s->stop);
1644 qemu_put_8s(f, &s->boundary);
1645 qemu_put_8s(f, &s->tsr);
1646 qemu_put_8s(f, &s->tpsr);
1647 qemu_put_be16s(f, &s->tcnt);
1648 qemu_put_be16s(f, &s->rcnt);
1649 qemu_put_be32s(f, &s->rsar);
1650 qemu_put_8s(f, &s->rsr);
1651 qemu_put_8s(f, &s->isr);
1652 qemu_put_8s(f, &s->dcfg);
1653 qemu_put_8s(f, &s->imr);
1654 qemu_put_buffer(f, s->phys, 6);
1655 qemu_put_8s(f, &s->curpag);
1656 qemu_put_buffer(f, s->mult, 8);
1657 qemu_put_buffer(f, s->mem, sizeof(s->mem));
1659 /* Save all members of struct between scv_stat and mem */
1660 qemu_put_8s(f, &s->scb_stat);
1661 qemu_put_8s(f, &s->int_stat);
1662 for (i = 0; i < 3; i++)
1663 qemu_put_be32s(f, &s->region[i]);
1664 qemu_put_buffer(f, s->macaddr, 6);
1665 for (i = 0; i < 19; i++)
1666 qemu_put_be32s(f, &s->statcounter[i]);
1667 for (i = 0; i < 32; i++)
1668 qemu_put_be16s(f, &s->mdimem[i]);
1669 /* The eeprom should be saved and restored by its own routines */
1670 qemu_put_be32s(f, &s->device);
1671 qemu_put_be32s(f, &s->pointer);
1672 qemu_put_be32s(f, &s->cu_base);
1673 qemu_put_be32s(f, &s->cu_offset);
1674 qemu_put_be32s(f, &s->ru_base);
1675 qemu_put_be32s(f, &s->ru_offset);
1676 qemu_put_be32s(f, &s->statsaddr);
1677 /* Save epro100_stats_t statistics */
1678 qemu_put_be32s(f, &s->statistics.tx_good_frames);
1679 qemu_put_be32s(f, &s->statistics.tx_max_collisions);
1680 qemu_put_be32s(f, &s->statistics.tx_late_collisions);
1681 qemu_put_be32s(f, &s->statistics.tx_underruns);
1682 qemu_put_be32s(f, &s->statistics.tx_lost_crs);
1683 qemu_put_be32s(f, &s->statistics.tx_deferred);
1684 qemu_put_be32s(f, &s->statistics.tx_single_collisions);
1685 qemu_put_be32s(f, &s->statistics.tx_multiple_collisions);
1686 qemu_put_be32s(f, &s->statistics.tx_total_collisions);
1687 qemu_put_be32s(f, &s->statistics.rx_good_frames);
1688 qemu_put_be32s(f, &s->statistics.rx_crc_errors);
1689 qemu_put_be32s(f, &s->statistics.rx_alignment_errors);
1690 qemu_put_be32s(f, &s->statistics.rx_resource_errors);
1691 qemu_put_be32s(f, &s->statistics.rx_overrun_errors);
1692 qemu_put_be32s(f, &s->statistics.rx_cdt_errors);
1693 qemu_put_be32s(f, &s->statistics.rx_short_frame_errors);
1694 qemu_put_be32s(f, &s->statistics.fc_xmt_pause);
1695 qemu_put_be32s(f, &s->statistics.fc_rcv_pause);
1696 qemu_put_be32s(f, &s->statistics.fc_rcv_unsupported);
1697 qemu_put_be16s(f, &s->statistics.xmt_tco_frames);
1698 qemu_put_be16s(f, &s->statistics.rcv_tco_frames);
1699 qemu_put_be32s(f, &s->statistics.complete);
1701 qemu_put_be16s(f, &s->status);
1704 /* Configuration bytes. */
1705 qemu_put_buffer(f, s->configuration, sizeof(s->configuration));
1708 static void nic_cleanup(VLANClientState *vc)
1710 EEPRO100State *s = vc->opaque;
1712 unregister_savevm(vc->model, s);
1714 eeprom93xx_free(s->eeprom);
1717 static int pci_nic_uninit(PCIDevice *dev)
1719 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, dev);
1721 cpu_unregister_io_memory(s->mmio_index);
1726 static int nic_init(PCIDevice *pci_dev, uint32_t device)
1728 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1732 s->dev.unregister = pci_nic_uninit;
1738 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1739 * i82559 and later support 64 or 256 word EEPROM. */
1740 s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1742 /* Handler for memory-mapped I/O */
1744 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
1746 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
1747 PCI_ADDRESS_SPACE_MEM |
1748 PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_mmio_map);
1749 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_ADDRESS_SPACE_IO,
1751 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_ADDRESS_SPACE_MEM,
1754 qdev_get_macaddr(&s->dev.qdev, s->macaddr);
1755 logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6));
1756 assert(s->region[1] == 0);
1760 s->vc = qdev_get_vlan_client(&s->dev.qdev,
1761 nic_can_receive, nic_receive, NULL,
1764 qemu_format_nic_info_str(s->vc, s->macaddr);
1766 qemu_register_reset(nic_reset, s);
1768 register_savevm(s->vc->model, -1, 3, nic_save, nic_load, s);
1772 static int pci_i82551_init(PCIDevice *dev)
1774 return nic_init(dev, i82551);
1777 static int pci_i82557b_init(PCIDevice *dev)
1779 return nic_init(dev, i82557B);
1782 static int pci_i82559er_init(PCIDevice *dev)
1784 return nic_init(dev, i82559ER);
1787 static PCIDeviceInfo eepro100_info[] = {
1789 .qdev.name = "i82551",
1790 .qdev.size = sizeof(EEPRO100State),
1791 .init = pci_i82551_init,
1793 .qdev.name = "i82557b",
1794 .qdev.size = sizeof(EEPRO100State),
1795 .init = pci_i82557b_init,
1797 .qdev.name = "i82559er",
1798 .qdev.size = sizeof(EEPRO100State),
1799 .init = pci_i82559er_init,
1805 static void eepro100_register_devices(void)
1807 pci_qdev_register_many(eepro100_info);
1810 device_init(eepro100_register_devices)