4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #define DPRINTF(fmt, args...) \
31 do { printf("ESP: " fmt , ##args); } while (0)
33 #define DPRINTF(fmt, args...)
37 #define ESPDMA_MAXADDR (ESPDMA_REGS * 4 - 1)
38 #define ESP_MAXREG 0x3f
40 typedef struct ESPState {
41 BlockDriverState **bd;
42 uint8_t regs[ESP_MAXREG];
44 uint32_t espdmaregs[ESPDMA_REGS];
47 static void esp_reset(void *opaque)
50 memset(s->regs, 0, ESP_MAXREG);
51 s->regs[0x0e] = 0x4; // Indicate fas100a
52 memset(s->espdmaregs, 0, ESPDMA_REGS * 4);
55 static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
60 saddr = (addr & ESP_MAXREG) >> 2;
65 DPRINTF("esp: read reg[%d]: 0x%2.2x\n", saddr, s->regs[saddr]);
66 return s->regs[saddr];
69 static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
74 saddr = (addr & ESP_MAXREG) >> 2;
75 DPRINTF("esp: write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->regs[saddr], val);
81 DPRINTF("esp: NOP (%2.2x)\n", val);
84 DPRINTF("esp: Chip reset (%2.2x)\n", val);
88 DPRINTF("esp: Bus reset (%2.2x)\n", val);
91 DPRINTF("esp: Set ATN (%2.2x)\n", val);
94 DPRINTF("esp: Select with ATN (%2.2x)\n", val);
95 s->regs[4] = 0x1a; // Status: TCNT | TDONE | CMD
96 s->regs[5] = 0x20; // Intr: Disconnect, nobody there
97 s->regs[6] = 0x4; // Seq: Cmd done
98 pic_set_irq(s->irq, 1);
106 s->regs[saddr] = val;
111 static CPUReadMemoryFunc *esp_mem_read[3] = {
117 static CPUWriteMemoryFunc *esp_mem_write[3] = {
123 static uint32_t espdma_mem_readl(void *opaque, target_phys_addr_t addr)
125 ESPState *s = opaque;
128 saddr = (addr & ESPDMA_MAXADDR) >> 2;
129 return s->espdmaregs[saddr];
132 static void espdma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
134 ESPState *s = opaque;
137 saddr = (addr & ESPDMA_MAXADDR) >> 2;
138 s->espdmaregs[saddr] = val;
141 static CPUReadMemoryFunc *espdma_mem_read[3] = {
147 static CPUWriteMemoryFunc *espdma_mem_write[3] = {
153 static void esp_save(QEMUFile *f, void *opaque)
155 ESPState *s = opaque;
159 static int esp_load(QEMUFile *f, void *opaque, int version_id)
161 ESPState *s = opaque;
169 void esp_init(BlockDriverState **bd, int irq, uint32_t espaddr, uint32_t espdaddr)
172 int esp_io_memory, espdma_io_memory;
174 s = qemu_mallocz(sizeof(ESPState));
181 esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
182 cpu_register_physical_memory(espaddr, ESP_MAXREG*4, esp_io_memory);
184 espdma_io_memory = cpu_register_io_memory(0, espdma_mem_read, espdma_mem_write, s);
185 cpu_register_physical_memory(espdaddr, 16, espdma_io_memory);
189 register_savevm("esp", espaddr, 1, esp_save, esp_load, s);
190 qemu_register_reset(esp_reset, s);