git.maemo.org Git - qemu/blob - hw/etraxfs_dma.c

   1 /*
   2  * QEMU ETRAX DMA Controller.
   3  *
   4  * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include <stdio.h>
  25 #include <sys/time.h>
  26 #include "hw.h"
  27 #include "qemu-common.h"
  28 #include "sysemu.h"
  29
  30 #include "etraxfs_dma.h"
  31
  32 #define D(x)
  33
  34 #define RW_DATA           0x0
  35 #define RW_SAVED_DATA     0x58
  36 #define RW_SAVED_DATA_BUF 0x5c
  37 #define RW_GROUP          0x60
  38 #define RW_GROUP_DOWN     0x7c
  39 #define RW_CMD            0x80
  40 #define RW_CFG            0x84
  41 #define RW_STAT           0x88
  42 #define RW_INTR_MASK      0x8c
  43 #define RW_ACK_INTR       0x90
  44 #define R_INTR            0x94
  45 #define R_MASKED_INTR     0x98
  46 #define RW_STREAM_CMD     0x9c
  47
  48 #define DMA_REG_MAX   0x100
  49
  50 /* descriptors */
  51
  52 // ------------------------------------------------------------ dma_descr_group
  53 typedef struct dma_descr_group {
  54   struct dma_descr_group       *next;
  55   unsigned                      eol        : 1;
  56   unsigned                      tol        : 1;
  57   unsigned                      bol        : 1;
  58   unsigned                                 : 1;
  59   unsigned                      intr       : 1;
  60   unsigned                                 : 2;
  61   unsigned                      en         : 1;
  62   unsigned                                 : 7;
  63   unsigned                      dis        : 1;
  64   unsigned                      md         : 16;
  65   struct dma_descr_group       *up;
  66   union {
  67     struct dma_descr_context   *context;
  68     struct dma_descr_group     *group;
  69   }                             down;
  70 } dma_descr_group;
  71
  72 // ---------------------------------------------------------- dma_descr_context
  73 typedef struct dma_descr_context {
  74   struct dma_descr_context     *next;
  75   unsigned                      eol        : 1;
  76   unsigned                                 : 3;
  77   unsigned                      intr       : 1;
  78   unsigned                                 : 1;
  79   unsigned                      store_mode : 1;
  80   unsigned                      en         : 1;
  81   unsigned                                 : 7;
  82   unsigned                      dis        : 1;
  83   unsigned                      md0        : 16;
  84   unsigned                      md1;
  85   unsigned                      md2;
  86   unsigned                      md3;
  87   unsigned                      md4;
  88   struct dma_descr_data        *saved_data;
  89   char                         *saved_data_buf;
  90 } dma_descr_context;
  91
  92 // ------------------------------------------------------------- dma_descr_data
  93 typedef struct dma_descr_data {
  94   struct dma_descr_data        *next;
  95   char                         *buf;
  96   unsigned                      eol        : 1;
  97   unsigned                                 : 2;
  98   unsigned                      out_eop    : 1;
  99   unsigned                      intr       : 1;
 100   unsigned                      wait       : 1;
 101   unsigned                                 : 2;
 102   unsigned                                 : 3;
 103   unsigned                      in_eop     : 1;
 104   unsigned                                 : 4;
 105   unsigned                      md         : 16;
 106   char                         *after;
 107 } dma_descr_data;
 108
 109 /* Constants */
 110 enum {
 111   regk_dma_ack_pkt                         = 0x00000100,
 112   regk_dma_anytime                         = 0x00000001,
 113   regk_dma_array                           = 0x00000008,
 114   regk_dma_burst                           = 0x00000020,
 115   regk_dma_client                          = 0x00000002,
 116   regk_dma_copy_next                       = 0x00000010,
 117   regk_dma_copy_up                         = 0x00000020,
 118   regk_dma_data_at_eol                     = 0x00000001,
 119   regk_dma_dis_c                           = 0x00000010,
 120   regk_dma_dis_g                           = 0x00000020,
 121   regk_dma_idle                            = 0x00000001,
 122   regk_dma_intern                          = 0x00000004,
 123   regk_dma_load_c                          = 0x00000200,
 124   regk_dma_load_c_n                        = 0x00000280,
 125   regk_dma_load_c_next                     = 0x00000240,
 126   regk_dma_load_d                          = 0x00000140,
 127   regk_dma_load_g                          = 0x00000300,
 128   regk_dma_load_g_down                     = 0x000003c0,
 129   regk_dma_load_g_next                     = 0x00000340,
 130   regk_dma_load_g_up                       = 0x00000380,
 131   regk_dma_next_en                         = 0x00000010,
 132   regk_dma_next_pkt                        = 0x00000010,
 133   regk_dma_no                              = 0x00000000,
 134   regk_dma_only_at_wait                    = 0x00000000,
 135   regk_dma_restore                         = 0x00000020,
 136   regk_dma_rst                             = 0x00000001,
 137   regk_dma_running                         = 0x00000004,
 138   regk_dma_rw_cfg_default                  = 0x00000000,
 139   regk_dma_rw_cmd_default                  = 0x00000000,
 140   regk_dma_rw_intr_mask_default            = 0x00000000,
 141   regk_dma_rw_stat_default                 = 0x00000101,
 142   regk_dma_rw_stream_cmd_default           = 0x00000000,
 143   regk_dma_save_down                       = 0x00000020,
 144   regk_dma_save_up                         = 0x00000020,
 145   regk_dma_set_reg                         = 0x00000050,
 146   regk_dma_set_w_size1                     = 0x00000190,
 147   regk_dma_set_w_size2                     = 0x000001a0,
 148   regk_dma_set_w_size4                     = 0x000001c0,
 149   regk_dma_stopped                         = 0x00000002,
 150   regk_dma_store_c                         = 0x00000002,
 151   regk_dma_store_descr                     = 0x00000000,
 152   regk_dma_store_g                         = 0x00000004,
 153   regk_dma_store_md                        = 0x00000001,
 154   regk_dma_sw                              = 0x00000008,
 155   regk_dma_update_down                     = 0x00000020,
 156   regk_dma_yes                             = 0x00000001
 157 };
 158
 159 enum dma_ch_state
 160 {
 161         RST = 1,
 162         STOPPED = 2,
 163         RUNNING = 4
 164 };
 165
 166 struct fs_dma_channel
 167 {
 168         int regmap;
 169         qemu_irq *irq;
 170         struct etraxfs_dma_client *client;
 171
 172
 173         /* Internal status.  */
 174         int stream_cmd_src;
 175         enum dma_ch_state state;
 176
 177         unsigned int input : 1;
 178         unsigned int eol : 1;
 179
 180         struct dma_descr_group current_g;
 181         struct dma_descr_context current_c;
 182         struct dma_descr_data current_d;
 183
 184         /* Controll registers.  */
 185         uint32_t regs[DMA_REG_MAX];
 186 };
 187
 188 struct fs_dma_ctrl
 189 {
 190         CPUState *env;
 191         target_phys_addr_t base;
 192
 193         int nr_channels;
 194         struct fs_dma_channel *channels;
 195
 196         QEMUBH *bh;
 197 };
 198
 199 static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg)
 200 {
 201         return ctrl->channels[c].regs[reg];
 202 }
 203
 204 static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c)
 205 {
 206         return channel_reg(ctrl, c, RW_CFG) & 2;
 207 }
 208
 209 static inline int channel_en(struct fs_dma_ctrl *ctrl, int c)
 210 {
 211         return (channel_reg(ctrl, c, RW_CFG) & 1)
 212                 && ctrl->channels[c].client;
 213 }
 214
 215 static inline int fs_channel(target_phys_addr_t base, target_phys_addr_t addr)
 216 {
 217         /* Every channel has a 0x2000 ctrl register map.  */
 218         return (addr - base) >> 13;
 219 }
 220
 221 #ifdef USE_THIS_DEAD_CODE
 222 static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
 223 {
 224         target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
 225
 226         /* Load and decode. FIXME: handle endianness.  */
 227         cpu_physical_memory_read (addr,
 228                                   (void *) &ctrl->channels[c].current_g,
 229                                   sizeof ctrl->channels[c].current_g);
 230 }
 231
 232 static void dump_c(int ch, struct dma_descr_context *c)
 233 {
 234         printf("%s ch=%d\n", __func__, ch);
 235         printf("next=%p\n", c->next);
 236         printf("saved_data=%p\n", c->saved_data);
 237         printf("saved_data_buf=%p\n", c->saved_data_buf);
 238         printf("eol=%x\n", (uint32_t) c->eol);
 239 }
 240
 241 static void dump_d(int ch, struct dma_descr_data *d)
 242 {
 243         printf("%s ch=%d\n", __func__, ch);
 244         printf("next=%p\n", d->next);
 245         printf("buf=%p\n", d->buf);
 246         printf("after=%p\n", d->after);
 247         printf("intr=%x\n", (uint32_t) d->intr);
 248         printf("out_eop=%x\n", (uint32_t) d->out_eop);
 249         printf("in_eop=%x\n", (uint32_t) d->in_eop);
 250         printf("eol=%x\n", (uint32_t) d->eol);
 251 }
 252 #endif
 253
 254 static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
 255 {
 256         target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
 257
 258         /* Load and decode. FIXME: handle endianness.  */
 259         cpu_physical_memory_read (addr,
 260                                   (void *) &ctrl->channels[c].current_c,
 261                                   sizeof ctrl->channels[c].current_c);
 262
 263         D(dump_c(c, &ctrl->channels[c].current_c));
 264         /* I guess this should update the current pos.  */
 265         ctrl->channels[c].regs[RW_SAVED_DATA] =
 266                 (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data;
 267         ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
 268                 (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data_buf;
 269 }
 270
 271 static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
 272 {
 273         target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
 274
 275         /* Load and decode. FIXME: handle endianness.  */
 276         D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
 277         cpu_physical_memory_read (addr,
 278                                   (void *) &ctrl->channels[c].current_d,
 279                                   sizeof ctrl->channels[c].current_d);
 280
 281         D(dump_d(c, &ctrl->channels[c].current_d));
 282         ctrl->channels[c].regs[RW_DATA] = addr;
 283 }
 284
 285 static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
 286 {
 287         target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
 288
 289         /* Encode and store. FIXME: handle endianness.  */
 290         D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
 291         D(dump_d(c, &ctrl->channels[c].current_d));
 292         cpu_physical_memory_write (addr,
 293                                   (void *) &ctrl->channels[c].current_c,
 294                                   sizeof ctrl->channels[c].current_c);
 295 }
 296
 297 static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
 298 {
 299         target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
 300
 301         /* Encode and store. FIXME: handle endianness.  */
 302         D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
 303         cpu_physical_memory_write (addr,
 304                                   (void *) &ctrl->channels[c].current_d,
 305                                   sizeof ctrl->channels[c].current_d);
 306 }
 307
 308 static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c)
 309 {
 310         /* FIXME:  */
 311 }
 312
 313 static inline void channel_start(struct fs_dma_ctrl *ctrl, int c)
 314 {
 315         if (ctrl->channels[c].client)
 316         {
 317                 ctrl->channels[c].eol = 0;
 318                 ctrl->channels[c].state = RUNNING;
 319         } else
 320                 printf("WARNING: starting DMA ch %d with no client\n", c);
 321
 322         qemu_bh_schedule_idle(ctrl->bh);
 323 }
 324
 325 static void channel_continue(struct fs_dma_ctrl *ctrl, int c)
 326 {
 327         if (!channel_en(ctrl, c)
 328             || channel_stopped(ctrl, c)
 329             || ctrl->channels[c].state != RUNNING
 330             /* Only reload the current data descriptor if it has eol set.  */
 331             || !ctrl->channels[c].current_d.eol) {
 332                 D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n",
 333                          c, ctrl->channels[c].state,
 334                          channel_stopped(ctrl, c),
 335                          channel_en(ctrl,c),
 336                          ctrl->channels[c].eol));
 337                 D(dump_d(c, &ctrl->channels[c].current_d));
 338                 return;
 339         }
 340
 341         /* Reload the current descriptor.  */
 342         channel_load_d(ctrl, c);
 343
 344         /* If the current descriptor cleared the eol flag and we had already
 345            reached eol state, do the continue.  */
 346         if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
 347                 D(printf("continue %d ok %p\n", c,
 348                          ctrl->channels[c].current_d.next));
 349                 ctrl->channels[c].regs[RW_SAVED_DATA] =
 350                         (uint32_t)(unsigned long)ctrl->channels[c].current_d.next;
 351                 channel_load_d(ctrl, c);
 352                 channel_start(ctrl, c);
 353         }
 354         ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
 355                 (uint32_t)(unsigned long)ctrl->channels[c].current_d.buf;
 356 }
 357
 358 static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v)
 359 {
 360         unsigned int cmd = v & ((1 << 10) - 1);
 361
 362         D(printf("%s ch=%d cmd=%x\n",
 363                  __func__, c, cmd));
 364         if (cmd & regk_dma_load_d) {
 365                 channel_load_d(ctrl, c);
 366                 if (cmd & regk_dma_burst)
 367                         channel_start(ctrl, c);
 368         }
 369
 370         if (cmd & regk_dma_load_c) {
 371                 channel_load_c(ctrl, c);
 372                 channel_start(ctrl, c);
 373         }
 374 }
 375
 376 static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c)
 377 {
 378         D(printf("%s %d\n", __func__, c));
 379         ctrl->channels[c].regs[R_INTR] &=
 380                 ~(ctrl->channels[c].regs[RW_ACK_INTR]);
 381
 382         ctrl->channels[c].regs[R_MASKED_INTR] =
 383                 ctrl->channels[c].regs[R_INTR]
 384                 & ctrl->channels[c].regs[RW_INTR_MASK];
 385
 386         D(printf("%s: chan=%d masked_intr=%x\n", __func__,
 387                  c,
 388                  ctrl->channels[c].regs[R_MASKED_INTR]));
 389
 390         if (ctrl->channels[c].regs[R_MASKED_INTR])
 391                 qemu_irq_raise(ctrl->channels[c].irq[0]);
 392         else
 393                 qemu_irq_lower(ctrl->channels[c].irq[0]);
 394 }
 395
 396 static int channel_out_run(struct fs_dma_ctrl *ctrl, int c)
 397 {
 398         uint32_t len;
 399         uint32_t saved_data_buf;
 400         unsigned char buf[2 * 1024];
 401
 402         if (ctrl->channels[c].eol)
 403                 return 0;
 404
 405         do {
 406                 saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
 407
 408                 D(printf("ch=%d buf=%x after=%x saved_data_buf=%x\n",
 409                          c,
 410                          (uint32_t)ctrl->channels[c].current_d.buf,
 411                          (uint32_t)ctrl->channels[c].current_d.after,
 412                          saved_data_buf));
 413
 414                 len = (uint32_t)(unsigned long)
 415                         ctrl->channels[c].current_d.after;
 416                 len -= saved_data_buf;
 417
 418                 if (len > sizeof buf)
 419                         len = sizeof buf;
 420                 cpu_physical_memory_read (saved_data_buf, buf, len);
 421
 422                 D(printf("channel %d pushes %x %u bytes\n", c,
 423                          saved_data_buf, len));
 424
 425                 if (ctrl->channels[c].client->client.push)
 426                         ctrl->channels[c].client->client.push(
 427                                 ctrl->channels[c].client->client.opaque,
 428                                 buf, len);
 429                 else
 430                         printf("WARNING: DMA ch%d dataloss,"
 431                                " no attached client.\n", c);
 432
 433                 saved_data_buf += len;
 434
 435                 if (saved_data_buf == (uint32_t)(unsigned long)
 436                                 ctrl->channels[c].current_d.after) {
 437                         /* Done. Step to next.  */
 438                         if (ctrl->channels[c].current_d.out_eop) {
 439                                 /* TODO: signal eop to the client.  */
 440                                 D(printf("signal eop\n"));
 441                         }
 442                         if (ctrl->channels[c].current_d.intr) {
 443                                 /* TODO: signal eop to the client.  */
 444                                 /* data intr.  */
 445                                 D(printf("signal intr\n"));
 446                                 ctrl->channels[c].regs[R_INTR] |= (1 << 2);
 447                                 channel_update_irq(ctrl, c);
 448                         }
 449                         if (ctrl->channels[c].current_d.eol) {
 450                                 D(printf("channel %d EOL\n", c));
 451                                 ctrl->channels[c].eol = 1;
 452
 453                                 /* Mark the context as disabled.  */
 454                                 ctrl->channels[c].current_c.dis = 1;
 455                                 channel_store_c(ctrl, c);
 456
 457                                 channel_stop(ctrl, c);
 458                         } else {
 459                                 ctrl->channels[c].regs[RW_SAVED_DATA] =
 460                                         (uint32_t)(unsigned long)ctrl->
 461                                                 channels[c].current_d.next;
 462                                 /* Load new descriptor.  */
 463                                 channel_load_d(ctrl, c);
 464                                 saved_data_buf = (uint32_t)(unsigned long)
 465                                         ctrl->channels[c].current_d.buf;
 466                         }
 467
 468                         channel_store_d(ctrl, c);
 469                         ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
 470                                                         saved_data_buf;
 471                         D(dump_d(c, &ctrl->channels[c].current_d));
 472                 }
 473                 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
 474         } while (!ctrl->channels[c].eol);
 475         return 1;
 476 }
 477
 478 static int channel_in_process(struct fs_dma_ctrl *ctrl, int c,
 479                               unsigned char *buf, int buflen, int eop)
 480 {
 481         uint32_t len;
 482         uint32_t saved_data_buf;
 483
 484         if (ctrl->channels[c].eol == 1)
 485                 return 0;
 486
 487         saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
 488         len = (uint32_t)(unsigned long)ctrl->channels[c].current_d.after;
 489         len -= saved_data_buf;
 490
 491         if (len > buflen)
 492                 len = buflen;
 493
 494         cpu_physical_memory_write (saved_data_buf, buf, len);
 495         saved_data_buf += len;
 496
 497         if (saved_data_buf ==
 498             (uint32_t)(unsigned long)ctrl->channels[c].current_d.after
 499             || eop) {
 500                 uint32_t r_intr = ctrl->channels[c].regs[R_INTR];
 501
 502                 D(printf("in dscr end len=%d\n",
 503                          ctrl->channels[c].current_d.after
 504                          - ctrl->channels[c].current_d.buf));
 505                 ctrl->channels[c].current_d.after =
 506                         (void *)(unsigned long) saved_data_buf;
 507
 508                 /* Done. Step to next.  */
 509                 if (ctrl->channels[c].current_d.intr) {
 510                         /* TODO: signal eop to the client.  */
 511                         /* data intr.  */
 512                         ctrl->channels[c].regs[R_INTR] |= 3;
 513                 }
 514                 if (eop) {
 515                         ctrl->channels[c].current_d.in_eop = 1;
 516                         ctrl->channels[c].regs[R_INTR] |= 8;
 517                 }
 518                 if (r_intr != ctrl->channels[c].regs[R_INTR])
 519                         channel_update_irq(ctrl, c);
 520
 521                 channel_store_d(ctrl, c);
 522                 D(dump_d(c, &ctrl->channels[c].current_d));
 523
 524                 if (ctrl->channels[c].current_d.eol) {
 525                         D(printf("channel %d EOL\n", c));
 526                         ctrl->channels[c].eol = 1;
 527
 528                         /* Mark the context as disabled.  */
 529                         ctrl->channels[c].current_c.dis = 1;
 530                         channel_store_c(ctrl, c);
 531
 532                         channel_stop(ctrl, c);
 533                 } else {
 534                         ctrl->channels[c].regs[RW_SAVED_DATA] =
 535                                 (uint32_t)(unsigned long)ctrl->
 536                                         channels[c].current_d.next;
 537                         /* Load new descriptor.  */
 538                         channel_load_d(ctrl, c);
 539                         saved_data_buf = (uint32_t)(unsigned long)
 540                                 ctrl->channels[c].current_d.buf;
 541                 }
 542         }
 543
 544         ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
 545         return len;
 546 }
 547
 548 static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c)
 549 {
 550         if (ctrl->channels[c].client->client.pull) {
 551                 ctrl->channels[c].client->client.pull(
 552                         ctrl->channels[c].client->client.opaque);
 553                 return 1;
 554         } else
 555                 return 0;
 556 }
 557
 558 static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
 559 {
 560         struct fs_dma_ctrl *ctrl = opaque;
 561         CPUState *env = ctrl->env;
 562         cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
 563                   addr);
 564         return 0;
 565 }
 566
 567 static uint32_t
 568 dma_readl (void *opaque, target_phys_addr_t addr)
 569 {
 570         struct fs_dma_ctrl *ctrl = opaque;
 571         int c;
 572         uint32_t r = 0;
 573
 574         /* Make addr relative to this instances base.  */
 575         c = fs_channel(ctrl->base, addr);
 576         addr &= 0x1fff;
 577         switch (addr)
 578         {
 579                 case RW_STAT:
 580                         r = ctrl->channels[c].state & 7;
 581                         r |= ctrl->channels[c].eol << 5;
 582                         r |= ctrl->channels[c].stream_cmd_src << 8;
 583                         break;
 584
 585                 default:
 586                         r = ctrl->channels[c].regs[addr];
 587                         D(printf ("%s c=%d addr=%x\n",
 588                                   __func__, c, addr));
 589                         break;
 590         }
 591         return r;
 592 }
 593
 594 static void
 595 dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
 596 {
 597         struct fs_dma_ctrl *ctrl = opaque;
 598         CPUState *env = ctrl->env;
 599         cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
 600                   addr);
 601 }
 602
 603 static void
 604 dma_update_state(struct fs_dma_ctrl *ctrl, int c)
 605 {
 606         if ((ctrl->channels[c].regs[RW_CFG] & 1) != 3) {
 607                 if (ctrl->channels[c].regs[RW_CFG] & 2)
 608                         ctrl->channels[c].state = STOPPED;
 609                 if (!(ctrl->channels[c].regs[RW_CFG] & 1))
 610                         ctrl->channels[c].state = RST;
 611         }
 612 }
 613
 614 static void
 615 dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 616 {
 617         struct fs_dma_ctrl *ctrl = opaque;
 618         int c;
 619
 620         /* Make addr relative to this instances base.  */
 621         c = fs_channel(ctrl->base, addr);
 622         addr &= 0x1fff;
 623         switch (addr)
 624         {
 625                 case RW_DATA:
 626                         ctrl->channels[c].regs[addr] = value;
 627                         break;
 628
 629                 case RW_CFG:
 630                         ctrl->channels[c].regs[addr] = value;
 631                         dma_update_state(ctrl, c);
 632                         break;
 633                 case RW_CMD:
 634                         /* continue.  */
 635                         if (value & ~1)
 636                                 printf("Invalid store to ch=%d RW_CMD %x\n",
 637                                        c, value);
 638                         ctrl->channels[c].regs[addr] = value;
 639                         channel_continue(ctrl, c);
 640                         break;
 641
 642                 case RW_SAVED_DATA:
 643                 case RW_SAVED_DATA_BUF:
 644                 case RW_GROUP:
 645                 case RW_GROUP_DOWN:
 646                         ctrl->channels[c].regs[addr] = value;
 647                         break;
 648
 649                 case RW_ACK_INTR:
 650                 case RW_INTR_MASK:
 651                         ctrl->channels[c].regs[addr] = value;
 652                         channel_update_irq(ctrl, c);
 653                         if (addr == RW_ACK_INTR)
 654                                 ctrl->channels[c].regs[RW_ACK_INTR] = 0;
 655                         break;
 656
 657                 case RW_STREAM_CMD:
 658                         if (value & ~1023)
 659                                 printf("Invalid store to ch=%d "
 660                                        "RW_STREAMCMD %x\n",
 661                                        c, value);
 662                         ctrl->channels[c].regs[addr] = value;
 663                         D(printf("stream_cmd ch=%d\n", c));
 664                         channel_stream_cmd(ctrl, c, value);
 665                         break;
 666
 667                 default:
 668                         D(printf ("%s c=%d %x %x\n", __func__, c, addr));
 669                         break;
 670         }
 671 }
 672
 673 static CPUReadMemoryFunc *dma_read[] = {
 674         &dma_rinvalid,
 675         &dma_rinvalid,
 676         &dma_readl,
 677 };
 678
 679 static CPUWriteMemoryFunc *dma_write[] = {
 680         &dma_winvalid,
 681         &dma_winvalid,
 682         &dma_writel,
 683 };
 684
 685 static int etraxfs_dmac_run(void *opaque)
 686 {
 687         struct fs_dma_ctrl *ctrl = opaque;
 688         int i;
 689         int p = 0;
 690
 691         for (i = 0;
 692              i < ctrl->nr_channels;
 693              i++)
 694         {
 695                 if (ctrl->channels[i].state == RUNNING)
 696                 {
 697                         if (ctrl->channels[i].input) {
 698                                 p += channel_in_run(ctrl, i);
 699                         } else {
 700                                 p += channel_out_run(ctrl, i);
 701                         }
 702                 }
 703         }
 704         return p;
 705 }
 706
 707 int etraxfs_dmac_input(struct etraxfs_dma_client *client,
 708                        void *buf, int len, int eop)
 709 {
 710         return channel_in_process(client->ctrl, client->channel,
 711                                   buf, len, eop);
 712 }
 713
 714 /* Connect an IRQ line with a channel.  */
 715 void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input)
 716 {
 717         struct fs_dma_ctrl *ctrl = opaque;
 718         ctrl->channels[c].irq = line;
 719         ctrl->channels[c].input = input;
 720 }
 721
 722 void etraxfs_dmac_connect_client(void *opaque, int c,
 723                                  struct etraxfs_dma_client *cl)
 724 {
 725         struct fs_dma_ctrl *ctrl = opaque;
 726         cl->ctrl = ctrl;
 727         cl->channel = c;
 728         ctrl->channels[c].client = cl;
 729 }
 730
 731
 732 static void DMA_run(void *opaque)
 733 {
 734     struct fs_dma_ctrl *etraxfs_dmac = opaque;
 735     int p = 1;
 736
 737     if (vm_running)
 738         p = etraxfs_dmac_run(etraxfs_dmac);
 739
 740     if (p)
 741         qemu_bh_schedule_idle(etraxfs_dmac->bh);
 742 }
 743
 744 void *etraxfs_dmac_init(CPUState *env,
 745                         target_phys_addr_t base, int nr_channels)
 746 {
 747         struct fs_dma_ctrl *ctrl = NULL;
 748         int i;
 749
 750         ctrl = qemu_mallocz(sizeof *ctrl);
 751         if (!ctrl)
 752                 return NULL;
 753
 754         ctrl->bh = qemu_bh_new(DMA_run, ctrl);
 755
 756         ctrl->base = base;
 757         ctrl->env = env;
 758         ctrl->nr_channels = nr_channels;
 759         ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
 760         if (!ctrl->channels)
 761                 goto err;
 762
 763         for (i = 0; i < nr_channels; i++)
 764         {
 765                 ctrl->channels[i].regmap = cpu_register_io_memory(0,
 766                                                                   dma_read,
 767                                                                   dma_write,
 768                                                                   ctrl);
 769                 cpu_register_physical_memory (base + i * 0x2000,
 770                                               sizeof ctrl->channels[i].regs,
 771                                               ctrl->channels[i].regmap);
 772         }
 773
 774         return ctrl;
 775   err:
 776         qemu_free(ctrl->channels);
 777         qemu_free(ctrl);
 778         return NULL;
 779 }