git.maemo.org Git - qemu/blob - hw/etraxfs_dma.c

   1 /*
   2  * QEMU ETRAX DMA Controller.
   3  *
   4  * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include <stdio.h>
  25 #include <sys/time.h>
  26 #include "hw.h"
  27
  28 #include "etraxfs_dma.h"
  29
  30 #define D(x)
  31
  32 #define RW_DATA           0x0
  33 #define RW_SAVED_DATA     0x58
  34 #define RW_SAVED_DATA_BUF 0x5c
  35 #define RW_GROUP          0x60
  36 #define RW_GROUP_DOWN     0x7c
  37 #define RW_CMD            0x80
  38 #define RW_CFG            0x84
  39 #define RW_STAT           0x88
  40 #define RW_INTR_MASK      0x8c
  41 #define RW_ACK_INTR       0x90
  42 #define R_INTR            0x94
  43 #define R_MASKED_INTR     0x98
  44 #define RW_STREAM_CMD     0x9c
  45
  46 #define DMA_REG_MAX   0x100
  47
  48 /* descriptors */
  49
  50 // ------------------------------------------------------------ dma_descr_group
  51 typedef struct dma_descr_group {
  52   struct dma_descr_group       *next;
  53   unsigned                      eol        : 1;
  54   unsigned                      tol        : 1;
  55   unsigned                      bol        : 1;
  56   unsigned                                 : 1;
  57   unsigned                      intr       : 1;
  58   unsigned                                 : 2;
  59   unsigned                      en         : 1;
  60   unsigned                                 : 7;
  61   unsigned                      dis        : 1;
  62   unsigned                      md         : 16;
  63   struct dma_descr_group       *up;
  64   union {
  65     struct dma_descr_context   *context;
  66     struct dma_descr_group     *group;
  67   }                             down;
  68 } dma_descr_group;
  69
  70 // ---------------------------------------------------------- dma_descr_context
  71 typedef struct dma_descr_context {
  72   struct dma_descr_context     *next;
  73   unsigned                      eol        : 1;
  74   unsigned                                 : 3;
  75   unsigned                      intr       : 1;
  76   unsigned                                 : 1;
  77   unsigned                      store_mode : 1;
  78   unsigned                      en         : 1;
  79   unsigned                                 : 7;
  80   unsigned                      dis        : 1;
  81   unsigned                      md0        : 16;
  82   unsigned                      md1;
  83   unsigned                      md2;
  84   unsigned                      md3;
  85   unsigned                      md4;
  86   struct dma_descr_data        *saved_data;
  87   char                         *saved_data_buf;
  88 } dma_descr_context;
  89
  90 // ------------------------------------------------------------- dma_descr_data
  91 typedef struct dma_descr_data {
  92   struct dma_descr_data        *next;
  93   char                         *buf;
  94   unsigned                      eol        : 1;
  95   unsigned                                 : 2;
  96   unsigned                      out_eop    : 1;
  97   unsigned                      intr       : 1;
  98   unsigned                      wait       : 1;
  99   unsigned                                 : 2;
 100   unsigned                                 : 3;
 101   unsigned                      in_eop     : 1;
 102   unsigned                                 : 4;
 103   unsigned                      md         : 16;
 104   char                         *after;
 105 } dma_descr_data;
 106
 107 /* Constants */
 108 enum {
 109   regk_dma_ack_pkt                         = 0x00000100,
 110   regk_dma_anytime                         = 0x00000001,
 111   regk_dma_array                           = 0x00000008,
 112   regk_dma_burst                           = 0x00000020,
 113   regk_dma_client                          = 0x00000002,
 114   regk_dma_copy_next                       = 0x00000010,
 115   regk_dma_copy_up                         = 0x00000020,
 116   regk_dma_data_at_eol                     = 0x00000001,
 117   regk_dma_dis_c                           = 0x00000010,
 118   regk_dma_dis_g                           = 0x00000020,
 119   regk_dma_idle                            = 0x00000001,
 120   regk_dma_intern                          = 0x00000004,
 121   regk_dma_load_c                          = 0x00000200,
 122   regk_dma_load_c_n                        = 0x00000280,
 123   regk_dma_load_c_next                     = 0x00000240,
 124   regk_dma_load_d                          = 0x00000140,
 125   regk_dma_load_g                          = 0x00000300,
 126   regk_dma_load_g_down                     = 0x000003c0,
 127   regk_dma_load_g_next                     = 0x00000340,
 128   regk_dma_load_g_up                       = 0x00000380,
 129   regk_dma_next_en                         = 0x00000010,
 130   regk_dma_next_pkt                        = 0x00000010,
 131   regk_dma_no                              = 0x00000000,
 132   regk_dma_only_at_wait                    = 0x00000000,
 133   regk_dma_restore                         = 0x00000020,
 134   regk_dma_rst                             = 0x00000001,
 135   regk_dma_running                         = 0x00000004,
 136   regk_dma_rw_cfg_default                  = 0x00000000,
 137   regk_dma_rw_cmd_default                  = 0x00000000,
 138   regk_dma_rw_intr_mask_default            = 0x00000000,
 139   regk_dma_rw_stat_default                 = 0x00000101,
 140   regk_dma_rw_stream_cmd_default           = 0x00000000,
 141   regk_dma_save_down                       = 0x00000020,
 142   regk_dma_save_up                         = 0x00000020,
 143   regk_dma_set_reg                         = 0x00000050,
 144   regk_dma_set_w_size1                     = 0x00000190,
 145   regk_dma_set_w_size2                     = 0x000001a0,
 146   regk_dma_set_w_size4                     = 0x000001c0,
 147   regk_dma_stopped                         = 0x00000002,
 148   regk_dma_store_c                         = 0x00000002,
 149   regk_dma_store_descr                     = 0x00000000,
 150   regk_dma_store_g                         = 0x00000004,
 151   regk_dma_store_md                        = 0x00000001,
 152   regk_dma_sw                              = 0x00000008,
 153   regk_dma_update_down                     = 0x00000020,
 154   regk_dma_yes                             = 0x00000001
 155 };
 156
 157 enum dma_ch_state
 158 {
 159         RST = 0,
 160         STOPPED = 2,
 161         RUNNING = 4
 162 };
 163
 164 struct fs_dma_channel
 165 {
 166         int regmap;
 167         qemu_irq *irq;
 168         struct etraxfs_dma_client *client;
 169
 170
 171         /* Internal status.  */
 172         int stream_cmd_src;
 173         enum dma_ch_state state;
 174
 175         unsigned int input : 1;
 176         unsigned int eol : 1;
 177
 178         struct dma_descr_group current_g;
 179         struct dma_descr_context current_c;
 180         struct dma_descr_data current_d;
 181
 182         /* Controll registers.  */
 183         uint32_t regs[DMA_REG_MAX];
 184 };
 185
 186 struct fs_dma_ctrl
 187 {
 188         CPUState *env;
 189         target_phys_addr_t base;
 190
 191         int nr_channels;
 192         struct fs_dma_channel *channels;
 193 };
 194
 195 static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg)
 196 {
 197         return ctrl->channels[c].regs[reg];
 198 }
 199
 200 static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c)
 201 {
 202         return channel_reg(ctrl, c, RW_CFG) & 2;
 203 }
 204
 205 static inline int channel_en(struct fs_dma_ctrl *ctrl, int c)
 206 {
 207         return (channel_reg(ctrl, c, RW_CFG) & 1)
 208                 && ctrl->channels[c].client;
 209 }
 210
 211 static inline int fs_channel(target_phys_addr_t base, target_phys_addr_t addr)
 212 {
 213         /* Every channel has a 0x2000 ctrl register map.  */
 214         return (addr - base) >> 13;
 215 }
 216
 217 static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
 218 {
 219         target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
 220
 221         /* Load and decode. FIXME: handle endianness.  */
 222         cpu_physical_memory_read (addr,
 223                                   (void *) &ctrl->channels[c].current_g,
 224                                   sizeof ctrl->channels[c].current_g);
 225 }
 226
 227 static void dump_c(int ch, struct dma_descr_context *c)
 228 {
 229         printf("%s ch=%d\n", __func__, ch);
 230         printf("next=%x\n", (uint32_t) c->next);
 231         printf("saved_data=%x\n", (uint32_t) c->saved_data);
 232         printf("saved_data_buf=%x\n", (uint32_t) c->saved_data_buf);
 233         printf("eol=%x\n", (uint32_t) c->eol);
 234 }
 235
 236 static void dump_d(int ch, struct dma_descr_data *d)
 237 {
 238         printf("%s ch=%d\n", __func__, ch);
 239         printf("next=%x\n", (uint32_t) d->next);
 240         printf("buf=%x\n", (uint32_t) d->buf);
 241         printf("after=%x\n", (uint32_t) d->after);
 242         printf("intr=%x\n", (uint32_t) d->intr);
 243         printf("out_eop=%x\n", (uint32_t) d->out_eop);
 244         printf("in_eop=%x\n", (uint32_t) d->in_eop);
 245         printf("eol=%x\n", (uint32_t) d->eol);
 246 }
 247
 248 static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
 249 {
 250         target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
 251
 252         /* Load and decode. FIXME: handle endianness.  */
 253         cpu_physical_memory_read (addr,
 254                                   (void *) &ctrl->channels[c].current_c,
 255                                   sizeof ctrl->channels[c].current_c);
 256
 257         D(dump_c(c, &ctrl->channels[c].current_c));
 258         /* I guess this should update the current pos.  */
 259         ctrl->channels[c].regs[RW_SAVED_DATA] =
 260                 (uint32_t)ctrl->channels[c].current_c.saved_data;
 261         ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
 262                 (uint32_t)ctrl->channels[c].current_c.saved_data_buf;
 263 }
 264
 265 static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
 266 {
 267         target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
 268
 269         /* Load and decode. FIXME: handle endianness.  */
 270         D(printf("%s addr=%x\n", __func__, addr));
 271         cpu_physical_memory_read (addr,
 272                                   (void *) &ctrl->channels[c].current_d,
 273                                   sizeof ctrl->channels[c].current_d);
 274
 275         D(dump_d(c, &ctrl->channels[c].current_d));
 276         ctrl->channels[c].regs[RW_DATA] = addr;
 277         ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
 278                 (uint32_t)ctrl->channels[c].current_d.buf;
 279 }
 280
 281 static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
 282 {
 283         target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
 284
 285         /* Load and decode. FIXME: handle endianness.  */
 286         D(printf("%s addr=%x\n", __func__, addr));
 287         cpu_physical_memory_write (addr,
 288                                   (void *) &ctrl->channels[c].current_d,
 289                                   sizeof ctrl->channels[c].current_d);
 290 }
 291
 292 static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c)
 293 {
 294         /* FIXME:  */
 295 }
 296
 297 static inline void channel_start(struct fs_dma_ctrl *ctrl, int c)
 298 {
 299         if (ctrl->channels[c].client)
 300         {
 301                 ctrl->channels[c].eol = 0;
 302                 ctrl->channels[c].state = RUNNING;
 303         } else
 304                 printf("WARNING: starting DMA ch %d with no client\n", c);
 305 }
 306
 307 static void channel_continue(struct fs_dma_ctrl *ctrl, int c)
 308 {
 309         if (!channel_en(ctrl, c)
 310             || channel_stopped(ctrl, c)
 311             || ctrl->channels[c].state != RUNNING
 312             /* Only reload the current data descriptor if it has eol set.  */
 313             || !ctrl->channels[c].current_d.eol) {
 314                 D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n",
 315                          c, ctrl->channels[c].state,
 316                          channel_stopped(ctrl, c),
 317                          channel_en(ctrl,c),
 318                          ctrl->channels[c].eol));
 319                 D(dump_d(c, &ctrl->channels[c].current_d));
 320                 return;
 321         }
 322
 323         /* Reload the current descriptor.  */
 324         channel_load_d(ctrl, c);
 325
 326         /* If the current descriptor cleared the eol flag and we had already
 327            reached eol state, do the continue.  */
 328         if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
 329                 D(printf("continue %d ok %x\n", c,
 330                          ctrl->channels[c].current_d.next));
 331                 ctrl->channels[c].regs[RW_SAVED_DATA] =
 332                         (uint32_t) ctrl->channels[c].current_d.next;
 333                 channel_load_d(ctrl, c);
 334                 channel_start(ctrl, c);
 335         }
 336 }
 337
 338 static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v)
 339 {
 340         unsigned int cmd = v & ((1 << 10) - 1);
 341
 342         D(printf("%s cmd=%x\n", __func__, cmd));
 343         if (cmd & regk_dma_load_d) {
 344                 channel_load_d(ctrl, c);
 345                 if (cmd & regk_dma_burst)
 346                         channel_start(ctrl, c);
 347         }
 348
 349         if (cmd & regk_dma_load_c) {
 350                 channel_load_c(ctrl, c);
 351         }
 352 }
 353
 354 static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c)
 355 {
 356         D(printf("%s %d\n", __func__, c));
 357         ctrl->channels[c].regs[R_INTR] &=
 358                 ~(ctrl->channels[c].regs[RW_ACK_INTR]);
 359
 360         ctrl->channels[c].regs[R_MASKED_INTR] =
 361                 ctrl->channels[c].regs[R_INTR]
 362                 & ctrl->channels[c].regs[RW_INTR_MASK];
 363
 364         D(printf("%s: chan=%d masked_intr=%x\n", __func__,
 365                  c,
 366                  ctrl->channels[c].regs[R_MASKED_INTR]));
 367
 368         if (ctrl->channels[c].regs[R_MASKED_INTR])
 369                 qemu_irq_raise(ctrl->channels[c].irq[0]);
 370         else
 371                 qemu_irq_lower(ctrl->channels[c].irq[0]);
 372 }
 373
 374 static void channel_out_run(struct fs_dma_ctrl *ctrl, int c)
 375 {
 376         uint32_t len;
 377         uint32_t saved_data_buf;
 378         unsigned char buf[2 * 1024];
 379
 380         if (ctrl->channels[c].eol == 1)
 381                 return;
 382
 383         saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
 384
 385         D(printf("buf=%x after=%x saved_data_buf=%x\n",
 386                  (uint32_t)ctrl->channels[c].current_d.buf,
 387                  (uint32_t)ctrl->channels[c].current_d.after,
 388                  saved_data_buf));
 389
 390         if (saved_data_buf == (uint32_t)ctrl->channels[c].current_d.after) {
 391                 /* Done. Step to next.  */
 392                 if (ctrl->channels[c].current_d.out_eop) {
 393                         /* TODO: signal eop to the client.  */
 394                         D(printf("signal eop\n"));
 395                 }
 396                 if (ctrl->channels[c].current_d.intr) {
 397                         /* TODO: signal eop to the client.  */
 398                         /* data intr.  */
 399                         D(printf("signal intr\n"));
 400                         ctrl->channels[c].regs[R_INTR] |= (1 << 2);
 401                         channel_update_irq(ctrl, c);
 402                 }
 403                 if (ctrl->channels[c].current_d.eol) {
 404                         D(printf("channel %d EOL\n", c));
 405                         ctrl->channels[c].eol = 1;
 406                         channel_stop(ctrl, c);
 407                 } else {
 408                         ctrl->channels[c].regs[RW_SAVED_DATA] =
 409                                 (uint32_t) ctrl->channels[c].current_d.next;
 410                         /* Load new descriptor.  */
 411                         channel_load_d(ctrl, c);
 412                 }
 413
 414                 channel_store_d(ctrl, c);
 415                 D(dump_d(c, &ctrl->channels[c].current_d));
 416                 return;
 417         }
 418
 419         len = (uint32_t) ctrl->channels[c].current_d.after;
 420         len -= saved_data_buf;
 421
 422         if (len > sizeof buf)
 423                 len = sizeof buf;
 424         cpu_physical_memory_read (saved_data_buf, buf, len);
 425
 426         D(printf("channel %d pushes %x %u bytes\n", c,
 427                  saved_data_buf, len));
 428         /* TODO: Push content.  */
 429         if (ctrl->channels[c].client->client.push)
 430                 ctrl->channels[c].client->client.push(
 431                         ctrl->channels[c].client->client.opaque, buf, len);
 432         else
 433                 printf("WARNING: DMA ch%d dataloss, no attached client.\n", c);
 434
 435         ctrl->channels[c].regs[RW_SAVED_DATA_BUF] += len;
 436 }
 437
 438 static int channel_in_process(struct fs_dma_ctrl *ctrl, int c,
 439                               unsigned char *buf, int buflen, int eop)
 440 {
 441         uint32_t len;
 442         uint32_t saved_data_buf;
 443
 444         if (ctrl->channels[c].eol == 1)
 445                 return 0;
 446
 447         saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
 448         len = (uint32_t) ctrl->channels[c].current_d.after;
 449         len -= saved_data_buf;
 450
 451         if (len > buflen)
 452                 len = buflen;
 453
 454         cpu_physical_memory_write (saved_data_buf, buf, len);
 455         saved_data_buf += len;
 456
 457         if (saved_data_buf == (uint32_t)ctrl->channels[c].current_d.after
 458             || eop) {
 459                 uint32_t r_intr = ctrl->channels[c].regs[R_INTR];
 460
 461                 D(printf("in dscr end len=%d\n",
 462                          ctrl->channels[c].current_d.after
 463                          - ctrl->channels[c].current_d.buf));
 464                 ctrl->channels[c].current_d.after =
 465                         (void *) saved_data_buf;
 466
 467                 /* Done. Step to next.  */
 468                 if (ctrl->channels[c].current_d.intr) {
 469                         /* TODO: signal eop to the client.  */
 470                         /* data intr.  */
 471                         ctrl->channels[c].regs[R_INTR] |= 3;
 472                 }
 473                 if (eop) {
 474                         ctrl->channels[c].current_d.in_eop = 1;
 475                         ctrl->channels[c].regs[R_INTR] |= 8;
 476                 }
 477                 if (r_intr != ctrl->channels[c].regs[R_INTR])
 478                         channel_update_irq(ctrl, c);
 479
 480                 channel_store_d(ctrl, c);
 481                 D(dump_d(c, &ctrl->channels[c].current_d));
 482
 483                 if (ctrl->channels[c].current_d.eol) {
 484                         D(printf("channel %d EOL\n", c));
 485                         ctrl->channels[c].eol = 1;
 486                         channel_stop(ctrl, c);
 487                 } else {
 488                         ctrl->channels[c].regs[RW_SAVED_DATA] =
 489                                 (uint32_t) ctrl->channels[c].current_d.next;
 490                         /* Load new descriptor.  */
 491                         channel_load_d(ctrl, c);
 492                         saved_data_buf =
 493                                 ctrl->channels[c].regs[RW_SAVED_DATA_BUF];
 494                 }
 495         }
 496
 497         ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
 498         return len;
 499 }
 500
 501 static inline void channel_in_run(struct fs_dma_ctrl *ctrl, int c)
 502 {
 503         if (ctrl->channels[c].client->client.pull)
 504                 ctrl->channels[c].client->client.pull(
 505                         ctrl->channels[c].client->client.opaque);
 506 }
 507
 508 static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
 509 {
 510         struct fs_dma_ctrl *ctrl = opaque;
 511         CPUState *env = ctrl->env;
 512         cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
 513                   addr, env->pc);
 514         return 0;
 515 }
 516
 517 static uint32_t
 518 dma_readl (void *opaque, target_phys_addr_t addr)
 519 {
 520         struct fs_dma_ctrl *ctrl = opaque;
 521         int c;
 522         uint32_t r = 0;
 523
 524         /* Make addr relative to this instances base.  */
 525         c = fs_channel(ctrl->base, addr);
 526         addr &= 0x1fff;
 527         switch (addr)
 528         {
 529                 case RW_STAT:
 530                         r = ctrl->channels[c].state & 7;
 531                         r |= ctrl->channels[c].eol << 5;
 532                         r |= ctrl->channels[c].stream_cmd_src << 8;
 533                         break;
 534
 535                 default:
 536                         r = ctrl->channels[c].regs[addr];
 537                         D(printf ("%s c=%d addr=%x pc=%x\n",
 538                                  __func__, c, addr, env->pc));
 539                         break;
 540         }
 541         return r;
 542 }
 543
 544 static void
 545 dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
 546 {
 547         struct fs_dma_ctrl *ctrl = opaque;
 548         CPUState *env = ctrl->env;
 549         cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
 550                   addr, env->pc);
 551 }
 552
 553 static void
 554 dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 555 {
 556         struct fs_dma_ctrl *ctrl = opaque;
 557         int c;
 558
 559         /* Make addr relative to this instances base.  */
 560         c = fs_channel(ctrl->base, addr);
 561         addr &= 0x1fff;
 562         switch (addr)
 563         {
 564                 case RW_DATA:
 565                         ctrl->channels[c].regs[addr] = value;
 566                         break;
 567
 568                 case RW_CFG:
 569                         ctrl->channels[c].regs[addr] = value;
 570                         break;
 571                 case RW_CMD:
 572                         /* continue.  */
 573                         ctrl->channels[c].regs[addr] = value;
 574                         channel_continue(ctrl, c);
 575                         break;
 576
 577                 case RW_SAVED_DATA:
 578                 case RW_SAVED_DATA_BUF:
 579                 case RW_GROUP:
 580                 case RW_GROUP_DOWN:
 581                         ctrl->channels[c].regs[addr] = value;
 582                         break;
 583
 584                 case RW_ACK_INTR:
 585                 case RW_INTR_MASK:
 586                         ctrl->channels[c].regs[addr] = value;
 587                         channel_update_irq(ctrl, c);
 588                         if (addr == RW_ACK_INTR)
 589                                 ctrl->channels[c].regs[RW_ACK_INTR] = 0;
 590                         break;
 591
 592                 case RW_STREAM_CMD:
 593                         ctrl->channels[c].regs[addr] = value;
 594                         channel_stream_cmd(ctrl, c, value);
 595                         break;
 596
 597                 default:
 598                         D(printf ("%s c=%d %x %x pc=%x\n",
 599                                   __func__, c, addr, value, env->pc));
 600                         break;
 601         }
 602 }
 603
 604 static CPUReadMemoryFunc *dma_read[] = {
 605         &dma_rinvalid,
 606         &dma_rinvalid,
 607         &dma_readl,
 608 };
 609
 610 static CPUWriteMemoryFunc *dma_write[] = {
 611         &dma_winvalid,
 612         &dma_winvalid,
 613         &dma_writel,
 614 };
 615
 616 void etraxfs_dmac_run(void *opaque)
 617 {
 618         struct fs_dma_ctrl *ctrl = opaque;
 619         int i;
 620         int p = 0;
 621
 622         for (i = 0;
 623              i < ctrl->nr_channels;
 624              i++)
 625         {
 626                 if (ctrl->channels[i].state == RUNNING)
 627                 {
 628                         p++;
 629                         if (ctrl->channels[i].input)
 630                                 channel_in_run(ctrl, i);
 631                         else
 632                                 channel_out_run(ctrl, i);
 633                 }
 634         }
 635 }
 636
 637 int etraxfs_dmac_input(struct etraxfs_dma_client *client,
 638                        void *buf, int len, int eop)
 639 {
 640         return channel_in_process(client->ctrl, client->channel,
 641                                   buf, len, eop);
 642 }
 643
 644 /* Connect an IRQ line with a channel.  */
 645 void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input)
 646 {
 647         struct fs_dma_ctrl *ctrl = opaque;
 648         ctrl->channels[c].irq = line;
 649         ctrl->channels[c].input = input;
 650 }
 651
 652 void etraxfs_dmac_connect_client(void *opaque, int c,
 653                                  struct etraxfs_dma_client *cl)
 654 {
 655         struct fs_dma_ctrl *ctrl = opaque;
 656         cl->ctrl = ctrl;
 657         cl->channel = c;
 658         ctrl->channels[c].client = cl;
 659 }
 660
 661
 662 static void *etraxfs_dmac;
 663 void DMA_run(void)
 664 {
 665         if (etraxfs_dmac)
 666                 etraxfs_dmac_run(etraxfs_dmac);
 667 }
 668
 669 void *etraxfs_dmac_init(CPUState *env,
 670                         target_phys_addr_t base, int nr_channels)
 671 {
 672         struct fs_dma_ctrl *ctrl = NULL;
 673         int i;
 674
 675         ctrl = qemu_mallocz(sizeof *ctrl);
 676         if (!ctrl)
 677                 return NULL;
 678
 679         ctrl->base = base;
 680         ctrl->env = env;
 681         ctrl->nr_channels = nr_channels;
 682         ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
 683         if (!ctrl->channels)
 684                 goto err;
 685
 686         for (i = 0; i < nr_channels; i++)
 687         {
 688                 ctrl->channels[i].regmap = cpu_register_io_memory(0,
 689                                                                   dma_read,
 690                                                                   dma_write,
 691                                                                   ctrl);
 692                 cpu_register_physical_memory (base + i * 0x2000,
 693                                               sizeof ctrl->channels[i].regs,
 694                                               ctrl->channels[i].regmap);
 695         }
 696
 697         /* Hax, we only support one DMA controller at a time.  */
 698         etraxfs_dmac = ctrl;
 699         return ctrl;
 700   err:
 701         qemu_free(ctrl->channels);
 702         qemu_free(ctrl);
 703         return NULL;
 704 }