git.maemo.org Git - qemu/blob - hw/etraxfs_timer.c

   1 /*
   2  * QEMU ETRAX Timers
   3  *
   4  * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include <stdio.h>
  25 #include <sys/time.h>
  26 #include "hw.h"
  27 #include "sysemu.h"
  28 #include "qemu-timer.h"
  29
  30 #define D(x)
  31
  32 #define RW_TMR0_DIV   0x00
  33 #define R_TMR0_DATA   0x04
  34 #define RW_TMR0_CTRL  0x08
  35 #define RW_TMR1_DIV   0x10
  36 #define R_TMR1_DATA   0x14
  37 #define RW_TMR1_CTRL  0x18
  38 #define R_TIME        0x38
  39 #define RW_WD_CTRL    0x40
  40 #define R_WD_STAT     0x44
  41 #define RW_INTR_MASK  0x48
  42 #define RW_ACK_INTR   0x4c
  43 #define R_INTR        0x50
  44 #define R_MASKED_INTR 0x54
  45
  46 struct fs_timer_t {
  47         CPUState *env;
  48         qemu_irq *irq;
  49         target_phys_addr_t base;
  50
  51         QEMUBH *bh_t0;
  52         QEMUBH *bh_t1;
  53         QEMUBH *bh_wd;
  54         ptimer_state *ptimer_t0;
  55         ptimer_state *ptimer_t1;
  56         ptimer_state *ptimer_wd;
  57         struct timeval last;
  58
  59         /* Control registers.  */
  60         uint32_t rw_tmr0_div;
  61         uint32_t r_tmr0_data;
  62         uint32_t rw_tmr0_ctrl;
  63
  64         uint32_t rw_tmr1_div;
  65         uint32_t r_tmr1_data;
  66         uint32_t rw_tmr1_ctrl;
  67
  68         uint32_t rw_wd_ctrl;
  69
  70         uint32_t rw_intr_mask;
  71         uint32_t rw_ack_intr;
  72         uint32_t r_intr;
  73         uint32_t r_masked_intr;
  74 };
  75
  76 static uint32_t timer_rinvalid (void *opaque, target_phys_addr_t addr)
  77 {
  78         struct fs_timer_t *t = opaque;
  79         CPUState *env = t->env;
  80         cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
  81                   addr, env->pc);
  82         return 0;
  83 }
  84
  85 static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
  86 {
  87         struct fs_timer_t *t = opaque;
  88         D(CPUState *env = t->env);
  89         uint32_t r = 0;
  90
  91         /* Make addr relative to this instances base.  */
  92         addr -= t->base;
  93         switch (addr) {
  94         case R_TMR0_DATA:
  95                 break;
  96         case R_TMR1_DATA:
  97                 D(printf ("R_TMR1_DATA\n"));
  98                 break;
  99         case R_TIME:
 100                 r = qemu_get_clock(vm_clock) * 10;
 101                 break;
 102         case RW_INTR_MASK:
 103                 r = t->rw_intr_mask;
 104                 break;
 105         case R_MASKED_INTR:
 106                 r = t->r_intr & t->rw_intr_mask;
 107                 break;
 108         default:
 109                 D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
 110                 break;
 111         }
 112         return r;
 113 }
 114
 115 static void
 116 timer_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
 117 {
 118         struct fs_timer_t *t = opaque;
 119         CPUState *env = t->env;
 120         cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
 121                   addr, env->pc);
 122 }
 123
 124 #define TIMER_SLOWDOWN 1
 125 static void update_ctrl(struct fs_timer_t *t, int tnum)
 126 {
 127         unsigned int op;
 128         unsigned int freq;
 129         unsigned int freq_hz;
 130         unsigned int div;
 131         uint32_t ctrl;
 132         ptimer_state *timer;
 133
 134         if (tnum == 0) {
 135                 ctrl = t->rw_tmr0_ctrl;
 136                 div = t->rw_tmr0_div;
 137                 timer = t->ptimer_t0;
 138         } else {
 139                 ctrl = t->rw_tmr1_ctrl;
 140                 div = t->rw_tmr1_div;
 141                 timer = t->ptimer_t1;
 142         }
 143
 144
 145         op = ctrl & 3;
 146         freq = ctrl >> 2;
 147         freq_hz = 32000000;
 148
 149         switch (freq)
 150         {
 151         case 0:
 152         case 1:
 153                 D(printf ("extern or disabled timer clock?\n"));
 154                 break;
 155         case 4: freq_hz =  29493000; break;
 156         case 5: freq_hz =  32000000; break;
 157         case 6: freq_hz =  32768000; break;
 158         case 7: freq_hz = 100001000; break;
 159         default:
 160                 abort();
 161                 break;
 162         }
 163
 164         D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
 165         div = div * TIMER_SLOWDOWN;
 166         div >>= 15;
 167         freq_hz >>= 15;
 168         ptimer_set_freq(timer, freq_hz);
 169         ptimer_set_limit(timer, div, 0);
 170
 171         switch (op)
 172         {
 173                 case 0:
 174                         /* Load.  */
 175                         ptimer_set_limit(timer, div, 1);
 176                         break;
 177                 case 1:
 178                         /* Hold.  */
 179                         ptimer_stop(timer);
 180                         break;
 181                 case 2:
 182                         /* Run.  */
 183                         ptimer_run(timer, 0);
 184                         break;
 185                 default:
 186                         abort();
 187                         break;
 188         }
 189 }
 190
 191 static void timer_update_irq(struct fs_timer_t *t)
 192 {
 193         t->r_intr &= ~(t->rw_ack_intr);
 194         t->r_masked_intr = t->r_intr & t->rw_intr_mask;
 195
 196         D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
 197         if (t->r_masked_intr)
 198                 qemu_irq_raise(t->irq[0]);
 199         else
 200                 qemu_irq_lower(t->irq[0]);
 201 }
 202
 203 static void timer0_hit(void *opaque)
 204 {
 205         struct fs_timer_t *t = opaque;
 206         t->r_intr |= 1;
 207         timer_update_irq(t);
 208 }
 209
 210 static void timer1_hit(void *opaque)
 211 {
 212         struct fs_timer_t *t = opaque;
 213         t->r_intr |= 2;
 214         timer_update_irq(t);
 215 }
 216
 217 static void watchdog_hit(void *opaque)
 218 {
 219         qemu_system_reset_request();
 220 }
 221
 222 static inline void timer_watchdog_update(struct fs_timer_t *t, uint32_t value)
 223 {
 224         unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
 225         unsigned int wd_key = t->rw_wd_ctrl >> 9;
 226         unsigned int wd_cnt = t->rw_wd_ctrl & 511;
 227         unsigned int new_key = value >> 9 & ((1 << 7) - 1);
 228         unsigned int new_cmd = (value >> 8) & 1;
 229
 230         /* If the watchdog is enabled, they written key must match the
 231            complement of the previous.  */
 232         wd_key = ~wd_key & ((1 << 7) - 1);
 233
 234         if (wd_en && wd_key != new_key)
 235                 return;
 236
 237         D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
 238                  wd_en, new_key, wd_key, new_cmd, wd_cnt));
 239
 240         ptimer_set_freq(t->ptimer_wd, 760);
 241         if (wd_cnt == 0)
 242                 wd_cnt = 256;
 243         ptimer_set_count(t->ptimer_wd, wd_cnt);
 244         if (new_cmd)
 245                 ptimer_run(t->ptimer_wd, 1);
 246         else
 247                 ptimer_stop(t->ptimer_wd);
 248
 249         t->rw_wd_ctrl = value;
 250 }
 251
 252 static void
 253 timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 254 {
 255         struct fs_timer_t *t = opaque;
 256         CPUState *env = t->env;
 257
 258         /* Make addr relative to this instances base.  */
 259         addr -= t->base;
 260         switch (addr)
 261         {
 262                 case RW_TMR0_DIV:
 263                         t->rw_tmr0_div = value;
 264                         break;
 265                 case RW_TMR0_CTRL:
 266                         D(printf ("RW_TMR0_CTRL=%x\n", value));
 267                         t->rw_tmr0_ctrl = value;
 268                         update_ctrl(t, 0);
 269                         break;
 270                 case RW_TMR1_DIV:
 271                         t->rw_tmr1_div = value;
 272                         break;
 273                 case RW_TMR1_CTRL:
 274                         D(printf ("RW_TMR1_CTRL=%x\n", value));
 275                         t->rw_tmr1_ctrl = value;
 276                         update_ctrl(t, 1);
 277                         break;
 278                 case RW_INTR_MASK:
 279                         D(printf ("RW_INTR_MASK=%x\n", value));
 280                         t->rw_intr_mask = value;
 281                         timer_update_irq(t);
 282                         break;
 283                 case RW_WD_CTRL:
 284                         timer_watchdog_update(t, value);
 285                         break;
 286                 case RW_ACK_INTR:
 287                         t->rw_ack_intr = value;
 288                         timer_update_irq(t);
 289                         t->rw_ack_intr = 0;
 290                         break;
 291                 default:
 292                         printf ("%s %x %x pc=%x\n",
 293                                 __func__, addr, value, env->pc);
 294                         break;
 295         }
 296 }
 297
 298 static CPUReadMemoryFunc *timer_read[] = {
 299         &timer_rinvalid,
 300         &timer_rinvalid,
 301         &timer_readl,
 302 };
 303
 304 static CPUWriteMemoryFunc *timer_write[] = {
 305         &timer_winvalid,
 306         &timer_winvalid,
 307         &timer_writel,
 308 };
 309
 310 static void etraxfs_timer_reset(void *opaque)
 311 {
 312         struct fs_timer_t *t = opaque;
 313
 314         ptimer_stop(t->ptimer_t0);
 315         ptimer_stop(t->ptimer_t1);
 316         ptimer_stop(t->ptimer_wd);
 317         t->rw_wd_ctrl = 0;
 318         t->r_intr = 0;
 319         t->rw_intr_mask = 0;
 320         qemu_irq_lower(t->irq[0]);
 321 }
 322
 323 void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
 324                         target_phys_addr_t base)
 325 {
 326         static struct fs_timer_t *t;
 327         int timer_regs;
 328
 329         t = qemu_mallocz(sizeof *t);
 330         if (!t)
 331                 return;
 332
 333         t->bh_t0 = qemu_bh_new(timer0_hit, t);
 334         t->bh_t1 = qemu_bh_new(timer1_hit, t);
 335         t->bh_wd = qemu_bh_new(watchdog_hit, t);
 336         t->ptimer_t0 = ptimer_init(t->bh_t0);
 337         t->ptimer_t1 = ptimer_init(t->bh_t1);
 338         t->ptimer_wd = ptimer_init(t->bh_wd);
 339         t->irq = irqs;
 340         t->env = env;
 341         t->base = base;
 342
 343         timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
 344         cpu_register_physical_memory (base, 0x5c, timer_regs);
 345
 346         qemu_register_reset(etraxfs_timer_reset, t);
 347 }