2 * QEMU GT64120 PCI host
4 * Copyright (c) 2006,2007 Aurelien Jarno
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 typedef target_phys_addr_t pci_addr_t;
33 #define dprintf(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
35 #define dprintf(fmt, ...)
38 #define GT_REGS (0x1000 >> 2)
40 /* CPU Configuration */
41 #define GT_CPU (0x000 >> 2)
42 #define GT_MULTI (0x120 >> 2)
44 /* CPU Address Decode */
45 #define GT_SCS10LD (0x008 >> 2)
46 #define GT_SCS10HD (0x010 >> 2)
47 #define GT_SCS32LD (0x018 >> 2)
48 #define GT_SCS32HD (0x020 >> 2)
49 #define GT_CS20LD (0x028 >> 2)
50 #define GT_CS20HD (0x030 >> 2)
51 #define GT_CS3BOOTLD (0x038 >> 2)
52 #define GT_CS3BOOTHD (0x040 >> 2)
53 #define GT_PCI0IOLD (0x048 >> 2)
54 #define GT_PCI0IOHD (0x050 >> 2)
55 #define GT_PCI0M0LD (0x058 >> 2)
56 #define GT_PCI0M0HD (0x060 >> 2)
57 #define GT_PCI0M1LD (0x080 >> 2)
58 #define GT_PCI0M1HD (0x088 >> 2)
59 #define GT_PCI1IOLD (0x090 >> 2)
60 #define GT_PCI1IOHD (0x098 >> 2)
61 #define GT_PCI1M0LD (0x0a0 >> 2)
62 #define GT_PCI1M0HD (0x0a8 >> 2)
63 #define GT_PCI1M1LD (0x0b0 >> 2)
64 #define GT_PCI1M1HD (0x0b8 >> 2)
65 #define GT_ISD (0x068 >> 2)
67 #define GT_SCS10AR (0x0d0 >> 2)
68 #define GT_SCS32AR (0x0d8 >> 2)
69 #define GT_CS20R (0x0e0 >> 2)
70 #define GT_CS3BOOTR (0x0e8 >> 2)
72 #define GT_PCI0IOREMAP (0x0f0 >> 2)
73 #define GT_PCI0M0REMAP (0x0f8 >> 2)
74 #define GT_PCI0M1REMAP (0x100 >> 2)
75 #define GT_PCI1IOREMAP (0x108 >> 2)
76 #define GT_PCI1M0REMAP (0x110 >> 2)
77 #define GT_PCI1M1REMAP (0x118 >> 2)
79 /* CPU Error Report */
80 #define GT_CPUERR_ADDRLO (0x070 >> 2)
81 #define GT_CPUERR_ADDRHI (0x078 >> 2)
82 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
83 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
84 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
86 /* CPU Sync Barrier */
87 #define GT_PCI0SYNC (0x0c0 >> 2)
88 #define GT_PCI1SYNC (0x0c8 >> 2)
90 /* SDRAM and Device Address Decode */
91 #define GT_SCS0LD (0x400 >> 2)
92 #define GT_SCS0HD (0x404 >> 2)
93 #define GT_SCS1LD (0x408 >> 2)
94 #define GT_SCS1HD (0x40c >> 2)
95 #define GT_SCS2LD (0x410 >> 2)
96 #define GT_SCS2HD (0x414 >> 2)
97 #define GT_SCS3LD (0x418 >> 2)
98 #define GT_SCS3HD (0x41c >> 2)
99 #define GT_CS0LD (0x420 >> 2)
100 #define GT_CS0HD (0x424 >> 2)
101 #define GT_CS1LD (0x428 >> 2)
102 #define GT_CS1HD (0x42c >> 2)
103 #define GT_CS2LD (0x430 >> 2)
104 #define GT_CS2HD (0x434 >> 2)
105 #define GT_CS3LD (0x438 >> 2)
106 #define GT_CS3HD (0x43c >> 2)
107 #define GT_BOOTLD (0x440 >> 2)
108 #define GT_BOOTHD (0x444 >> 2)
109 #define GT_ADERR (0x470 >> 2)
111 /* SDRAM Configuration */
112 #define GT_SDRAM_CFG (0x448 >> 2)
113 #define GT_SDRAM_OPMODE (0x474 >> 2)
114 #define GT_SDRAM_BM (0x478 >> 2)
115 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
117 /* SDRAM Parameters */
118 #define GT_SDRAM_B0 (0x44c >> 2)
119 #define GT_SDRAM_B1 (0x450 >> 2)
120 #define GT_SDRAM_B2 (0x454 >> 2)
121 #define GT_SDRAM_B3 (0x458 >> 2)
123 /* Device Parameters */
124 #define GT_DEV_B0 (0x45c >> 2)
125 #define GT_DEV_B1 (0x460 >> 2)
126 #define GT_DEV_B2 (0x464 >> 2)
127 #define GT_DEV_B3 (0x468 >> 2)
128 #define GT_DEV_BOOT (0x46c >> 2)
131 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
132 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
133 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
134 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
135 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
138 #define GT_DMA0_CNT (0x800 >> 2)
139 #define GT_DMA1_CNT (0x804 >> 2)
140 #define GT_DMA2_CNT (0x808 >> 2)
141 #define GT_DMA3_CNT (0x80c >> 2)
142 #define GT_DMA0_SA (0x810 >> 2)
143 #define GT_DMA1_SA (0x814 >> 2)
144 #define GT_DMA2_SA (0x818 >> 2)
145 #define GT_DMA3_SA (0x81c >> 2)
146 #define GT_DMA0_DA (0x820 >> 2)
147 #define GT_DMA1_DA (0x824 >> 2)
148 #define GT_DMA2_DA (0x828 >> 2)
149 #define GT_DMA3_DA (0x82c >> 2)
150 #define GT_DMA0_NEXT (0x830 >> 2)
151 #define GT_DMA1_NEXT (0x834 >> 2)
152 #define GT_DMA2_NEXT (0x838 >> 2)
153 #define GT_DMA3_NEXT (0x83c >> 2)
154 #define GT_DMA0_CUR (0x870 >> 2)
155 #define GT_DMA1_CUR (0x874 >> 2)
156 #define GT_DMA2_CUR (0x878 >> 2)
157 #define GT_DMA3_CUR (0x87c >> 2)
159 /* DMA Channel Control */
160 #define GT_DMA0_CTRL (0x840 >> 2)
161 #define GT_DMA1_CTRL (0x844 >> 2)
162 #define GT_DMA2_CTRL (0x848 >> 2)
163 #define GT_DMA3_CTRL (0x84c >> 2)
166 #define GT_DMA_ARB (0x860 >> 2)
169 #define GT_TC0 (0x850 >> 2)
170 #define GT_TC1 (0x854 >> 2)
171 #define GT_TC2 (0x858 >> 2)
172 #define GT_TC3 (0x85c >> 2)
173 #define GT_TC_CONTROL (0x864 >> 2)
176 #define GT_PCI0_CMD (0xc00 >> 2)
177 #define GT_PCI0_TOR (0xc04 >> 2)
178 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
179 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
180 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
181 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
182 #define GT_PCI1_IACK (0xc30 >> 2)
183 #define GT_PCI0_IACK (0xc34 >> 2)
184 #define GT_PCI0_BARE (0xc3c >> 2)
185 #define GT_PCI0_PREFMBR (0xc40 >> 2)
186 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
187 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
188 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
189 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
190 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
191 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
192 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
193 #define GT_PCI1_CMD (0xc80 >> 2)
194 #define GT_PCI1_TOR (0xc84 >> 2)
195 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
196 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
197 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
198 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
199 #define GT_PCI1_BARE (0xcbc >> 2)
200 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
201 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
202 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
203 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
204 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
205 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
206 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
207 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
208 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
209 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
210 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
211 #define GT_PCI0_CFGDATA (0xcfc >> 2)
214 #define GT_INTRCAUSE (0xc18 >> 2)
215 #define GT_INTRMASK (0xc1c >> 2)
216 #define GT_PCI0_ICMASK (0xc24 >> 2)
217 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
218 #define GT_CPU_INTSEL (0xc70 >> 2)
219 #define GT_PCI0_INTSEL (0xc74 >> 2)
220 #define GT_HINTRCAUSE (0xc98 >> 2)
221 #define GT_HINTRMASK (0xc9c >> 2)
222 #define GT_PCI0_HICMASK (0xca4 >> 2)
223 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
226 typedef PCIHostState GT64120PCIState;
228 typedef struct GT64120State {
229 GT64120PCIState *pci;
230 uint32_t regs[GT_REGS];
231 target_phys_addr_t PCI0IO_start;
232 target_phys_addr_t PCI0IO_length;
235 static void gt64120_pci_mapping(GT64120State *s)
237 /* Update IO mapping */
238 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
240 /* Unmap old IO address */
241 if (s->PCI0IO_length)
243 cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
245 /* Map new IO address */
246 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
247 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
248 isa_mem_base = s->PCI0IO_start;
249 isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);
253 static void gt64120_writel (void *opaque, target_phys_addr_t addr,
256 GT64120State *s = opaque;
259 #ifdef TARGET_WORDS_BIGENDIAN
263 saddr = (addr & 0xfff) >> 2;
266 /* CPU Configuration */
268 s->regs[GT_CPU] = val;
271 /* Read-only register as only one GT64xxx is present on the CPU bus */
274 /* CPU Address Decode */
276 s->regs[GT_PCI0IOLD] = val & 0x00007fff;
277 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
278 gt64120_pci_mapping(s);
281 s->regs[GT_PCI0M0LD] = val & 0x00007fff;
282 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
283 gt64120_pci_mapping(s);
286 s->regs[GT_PCI0M1LD] = val & 0x00007fff;
287 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
288 gt64120_pci_mapping(s);
291 s->regs[GT_PCI1IOLD] = val & 0x00007fff;
292 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
293 gt64120_pci_mapping(s);
296 s->regs[GT_PCI1M0LD] = val & 0x00007fff;
297 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
298 gt64120_pci_mapping(s);
301 s->regs[GT_PCI1M1LD] = val & 0x00007fff;
302 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
303 gt64120_pci_mapping(s);
311 s->regs[saddr] = val & 0x0000007f;
312 gt64120_pci_mapping(s);
320 s->regs[saddr] = val & 0x000007ff;
321 gt64120_pci_mapping(s);
324 /* CPU Error Report */
325 case GT_CPUERR_ADDRLO:
326 case GT_CPUERR_ADDRHI:
327 case GT_CPUERR_DATALO:
328 case GT_CPUERR_DATAHI:
329 case GT_CPUERR_PARITY:
330 /* Read-only registers, do nothing */
333 /* CPU Sync Barrier */
336 /* Read-only registers, do nothing */
339 /* SDRAM and Device Address Decode */
359 /* SDRAM Configuration */
361 case GT_SDRAM_OPMODE:
363 case GT_SDRAM_ADDRDECODE:
364 /* Accept and ignore SDRAM interleave configuration */
365 s->regs[saddr] = val;
368 /* Device Parameters */
374 /* Not implemented */
375 dprintf ("Unimplemented device register offset 0x%x\n", saddr << 2);
379 case GT_ECC_ERRDATALO:
380 case GT_ECC_ERRDATAHI:
384 /* Read-only registers, do nothing */
408 /* Not implemented */
409 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
412 /* DMA Channel Control */
417 /* Not implemented */
418 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
423 /* Not implemented */
424 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
433 /* Not implemented */
434 dprintf ("Unimplemented timer register offset 0x%x\n", saddr << 2);
440 s->regs[saddr] = val & 0x0401fc0f;
443 case GT_PCI0_BS_SCS10:
444 case GT_PCI0_BS_SCS32:
445 case GT_PCI0_BS_CS20:
446 case GT_PCI0_BS_CS3BT:
450 case GT_PCI0_PREFMBR:
451 case GT_PCI0_SCS10_BAR:
452 case GT_PCI0_SCS32_BAR:
453 case GT_PCI0_CS20_BAR:
454 case GT_PCI0_CS3BT_BAR:
455 case GT_PCI0_SSCS10_BAR:
456 case GT_PCI0_SSCS32_BAR:
457 case GT_PCI0_SCS3BT_BAR:
459 case GT_PCI1_BS_SCS10:
460 case GT_PCI1_BS_SCS32:
461 case GT_PCI1_BS_CS20:
462 case GT_PCI1_BS_CS3BT:
464 case GT_PCI1_PREFMBR:
465 case GT_PCI1_SCS10_BAR:
466 case GT_PCI1_SCS32_BAR:
467 case GT_PCI1_CS20_BAR:
468 case GT_PCI1_CS3BT_BAR:
469 case GT_PCI1_SSCS10_BAR:
470 case GT_PCI1_SSCS32_BAR:
471 case GT_PCI1_SCS3BT_BAR:
472 case GT_PCI1_CFGADDR:
473 case GT_PCI1_CFGDATA:
474 /* not implemented */
476 case GT_PCI0_CFGADDR:
477 s->pci->config_reg = val & 0x80fffffc;
479 case GT_PCI0_CFGDATA:
480 if (s->pci->config_reg & (1u << 31))
481 pci_host_data_writel(s->pci, 0, val);
486 /* not really implemented */
487 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
488 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
489 dprintf("INTRCAUSE %x\n", val);
492 s->regs[saddr] = val & 0x3c3ffffe;
493 dprintf("INTRMASK %x\n", val);
496 s->regs[saddr] = val & 0x03fffffe;
497 dprintf("ICMASK %x\n", val);
499 case GT_PCI0_SERR0MASK:
500 s->regs[saddr] = val & 0x0000003f;
501 dprintf("SERR0MASK %x\n", val);
504 /* Reserved when only PCI_0 is configured. */
509 case GT_PCI0_HICMASK:
510 case GT_PCI1_SERR1MASK:
511 /* not implemented */
514 /* SDRAM Parameters */
519 /* We don't simulate electrical parameters of the SDRAM.
520 Accept, but ignore the values. */
521 s->regs[saddr] = val;
525 dprintf ("Bad register offset 0x%x\n", (int)addr);
530 static uint32_t gt64120_readl (void *opaque,
531 target_phys_addr_t addr)
533 GT64120State *s = opaque;
538 saddr = (addr & 0xfff) >> 2;
542 /* CPU Configuration */
544 /* Only one GT64xxx is present on the CPU bus, return
546 val = s->regs[saddr];
549 /* CPU Error Report */
550 case GT_CPUERR_ADDRLO:
551 case GT_CPUERR_ADDRHI:
552 case GT_CPUERR_DATALO:
553 case GT_CPUERR_DATAHI:
554 case GT_CPUERR_PARITY:
555 /* Emulated memory has no error, always return the initial
557 val = s->regs[saddr];
560 /* CPU Sync Barrier */
563 /* Reading those register should empty all FIFO on the PCI
564 bus, which are not emulated. The return value should be
565 a random value that should be ignored. */
570 case GT_ECC_ERRDATALO:
571 case GT_ECC_ERRDATAHI:
575 /* Emulated memory has no error, always return the initial
577 val = s->regs[saddr];
612 val = s->regs[saddr];
615 /* Read the IRQ number */
616 val = pic_read_irq(isa_pic);
619 /* SDRAM and Device Address Decode */
639 val = s->regs[saddr];
642 /* SDRAM Configuration */
644 case GT_SDRAM_OPMODE:
646 case GT_SDRAM_ADDRDECODE:
647 val = s->regs[saddr];
650 /* SDRAM Parameters */
655 /* We don't simulate electrical parameters of the SDRAM.
656 Just return the last written value. */
657 val = s->regs[saddr];
660 /* Device Parameters */
666 val = s->regs[saddr];
690 val = s->regs[saddr];
693 /* DMA Channel Control */
698 val = s->regs[saddr];
703 val = s->regs[saddr];
712 val = s->regs[saddr];
716 case GT_PCI0_CFGADDR:
717 val = s->pci->config_reg;
719 case GT_PCI0_CFGDATA:
720 if (!(s->pci->config_reg & (1u << 31)))
723 val = pci_data_read(s->pci->bus, s->pci->config_reg, 4);
728 case GT_PCI0_BS_SCS10:
729 case GT_PCI0_BS_SCS32:
730 case GT_PCI0_BS_CS20:
731 case GT_PCI0_BS_CS3BT:
734 case GT_PCI0_PREFMBR:
735 case GT_PCI0_SCS10_BAR:
736 case GT_PCI0_SCS32_BAR:
737 case GT_PCI0_CS20_BAR:
738 case GT_PCI0_CS3BT_BAR:
739 case GT_PCI0_SSCS10_BAR:
740 case GT_PCI0_SSCS32_BAR:
741 case GT_PCI0_SCS3BT_BAR:
744 case GT_PCI1_BS_SCS10:
745 case GT_PCI1_BS_SCS32:
746 case GT_PCI1_BS_CS20:
747 case GT_PCI1_BS_CS3BT:
749 case GT_PCI1_PREFMBR:
750 case GT_PCI1_SCS10_BAR:
751 case GT_PCI1_SCS32_BAR:
752 case GT_PCI1_CS20_BAR:
753 case GT_PCI1_CS3BT_BAR:
754 case GT_PCI1_SSCS10_BAR:
755 case GT_PCI1_SSCS32_BAR:
756 case GT_PCI1_SCS3BT_BAR:
757 case GT_PCI1_CFGADDR:
758 case GT_PCI1_CFGDATA:
759 val = s->regs[saddr];
764 val = s->regs[saddr];
765 dprintf("INTRCAUSE %x\n", val);
768 val = s->regs[saddr];
769 dprintf("INTRMASK %x\n", val);
772 val = s->regs[saddr];
773 dprintf("ICMASK %x\n", val);
775 case GT_PCI0_SERR0MASK:
776 val = s->regs[saddr];
777 dprintf("SERR0MASK %x\n", val);
780 /* Reserved when only PCI_0 is configured. */
785 case GT_PCI0_HICMASK:
786 case GT_PCI1_SERR1MASK:
787 val = s->regs[saddr];
791 val = s->regs[saddr];
792 dprintf ("Bad register offset 0x%x\n", (int)addr);
796 #ifdef TARGET_WORDS_BIGENDIAN
802 static CPUWriteMemoryFunc *gt64120_write[] = {
808 static CPUReadMemoryFunc *gt64120_read[] = {
814 static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
818 slot = (pci_dev->devfn >> 3);
824 /* AMD 79C973 Ethernet */
827 /* Crystal 4281 Sound */
830 /* PCI slot 1 to 4 */
832 return ((slot - 18) + irq_num) & 0x03;
833 /* Unknown device, don't do any translation */
839 extern PCIDevice *piix4_dev;
840 static int pci_irq_levels[4];
842 static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level)
844 int i, pic_irq, pic_level;
846 pci_irq_levels[irq_num] = level;
848 /* now we change the pic irq level according to the piix irq mappings */
850 pic_irq = piix4_dev->config[0x60 + irq_num];
852 /* The pic level is the logical OR of all the PCI irqs mapped
855 for (i = 0; i < 4; i++) {
856 if (pic_irq == piix4_dev->config[0x60 + i])
857 pic_level |= pci_irq_levels[i];
859 qemu_set_irq(pic[pic_irq], pic_level);
864 void gt64120_reset(void *opaque)
866 GT64120State *s = opaque;
868 /* CPU Configuration */
869 #ifdef TARGET_WORDS_BIGENDIAN
870 s->regs[GT_CPU] = 0x00000000;
872 s->regs[GT_CPU] = 0x00001000;
874 s->regs[GT_MULTI] = 0x00000000;
876 /* CPU Address decode FIXME: not complete*/
877 s->regs[GT_PCI0IOLD] = 0x00000080;
878 s->regs[GT_PCI0IOHD] = 0x0000000f;
879 s->regs[GT_PCI0M0LD] = 0x00000090;
880 s->regs[GT_PCI0M0HD] = 0x0000001f;
881 s->regs[GT_PCI0M1LD] = 0x00000790;
882 s->regs[GT_PCI0M1HD] = 0x0000001f;
883 s->regs[GT_PCI1IOLD] = 0x00000100;
884 s->regs[GT_PCI1IOHD] = 0x0000000f;
885 s->regs[GT_PCI1M0LD] = 0x00000110;
886 s->regs[GT_PCI1M0HD] = 0x0000001f;
887 s->regs[GT_PCI1M1LD] = 0x00000120;
888 s->regs[GT_PCI1M1HD] = 0x0000002f;
889 s->regs[GT_PCI0IOREMAP] = 0x00000080;
890 s->regs[GT_PCI0M0REMAP] = 0x00000090;
891 s->regs[GT_PCI0M1REMAP] = 0x00000790;
892 s->regs[GT_PCI1IOREMAP] = 0x00000100;
893 s->regs[GT_PCI1M0REMAP] = 0x00000110;
894 s->regs[GT_PCI1M1REMAP] = 0x00000120;
896 /* CPU Error Report */
897 s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
898 s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
899 s->regs[GT_CPUERR_DATALO] = 0xffffffff;
900 s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
901 s->regs[GT_CPUERR_PARITY] = 0x000000ff;
904 s->regs[GT_ECC_ERRDATALO] = 0x00000000;
905 s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
906 s->regs[GT_ECC_MEM] = 0x00000000;
907 s->regs[GT_ECC_CALC] = 0x00000000;
908 s->regs[GT_ECC_ERRADDR] = 0x00000000;
910 /* SDRAM Parameters */
911 s->regs[GT_SDRAM_B0] = 0x00000005;
912 s->regs[GT_SDRAM_B1] = 0x00000005;
913 s->regs[GT_SDRAM_B2] = 0x00000005;
914 s->regs[GT_SDRAM_B3] = 0x00000005;
916 /* PCI Internal FIXME: not complete*/
917 #ifdef TARGET_WORDS_BIGENDIAN
918 s->regs[GT_PCI0_CMD] = 0x00000000;
919 s->regs[GT_PCI1_CMD] = 0x00000000;
921 s->regs[GT_PCI0_CMD] = 0x00010001;
922 s->regs[GT_PCI1_CMD] = 0x00010001;
924 s->regs[GT_PCI0_IACK] = 0x00000000;
925 s->regs[GT_PCI1_IACK] = 0x00000000;
927 gt64120_pci_mapping(s);
930 static uint32_t gt64120_read_config(PCIDevice *d, uint32_t address, int len)
932 uint32_t val = pci_default_read_config(d, address, len);
933 #ifdef TARGET_WORDS_BIGENDIAN
939 static void gt64120_write_config(PCIDevice *d, uint32_t address, uint32_t val,
942 #ifdef TARGET_WORDS_BIGENDIAN
945 pci_default_write_config(d, address, val, len);
948 PCIBus *pci_gt64120_init(qemu_irq *pic)
954 s = qemu_mallocz(sizeof(GT64120State));
955 s->pci = qemu_mallocz(sizeof(GT64120PCIState));
958 s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq,
961 gt64120 = cpu_register_io_memory(0, gt64120_read,
963 cpu_register_physical_memory(0x1be00000LL, 0x1000, gt64120);
965 d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
966 0, gt64120_read_config, gt64120_write_config);
968 d->config[0x00] = 0xab; // vendor_id
969 d->config[0x01] = 0x11;
970 d->config[0x02] = 0x20; // device_id
971 d->config[0x03] = 0x46;
972 d->config[0x04] = 0x06;
973 d->config[0x05] = 0x00;
974 d->config[0x06] = 0x80;
975 d->config[0x07] = 0xa2;
976 d->config[0x08] = 0x10;
977 d->config[0x09] = 0x00;
978 d->config[0x0A] = 0x80;
979 d->config[0x0B] = 0x05;
980 d->config[0x0C] = 0x08;
981 d->config[0x0D] = 0x40;
982 d->config[0x0E] = 0x00;
983 d->config[0x0F] = 0x00;
984 d->config[0x17] = 0x08;
985 d->config[0x1B] = 0x1c;
986 d->config[0x1F] = 0x1f;
987 d->config[0x23] = 0x14;
988 d->config[0x27] = 0x14;
989 d->config[0x3D] = 0x01;