2 * QEMU LSI53C895A SCSI Host Bus Adapter emulation
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the LGPL.
10 /* ??? Need to check if the {read,write}[wl] routines work properly on
11 big-endian targets. */
15 #include "scsi-disk.h"
18 //#define DEBUG_LSI_REG
21 #define DPRINTF(fmt, args...) \
22 do { printf("lsi_scsi: " fmt , ##args); } while (0)
23 #define BADF(fmt, args...) \
24 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args); exit(1);} while (0)
26 #define DPRINTF(fmt, args...) do {} while(0)
27 #define BADF(fmt, args...) \
28 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args);} while (0)
31 #define LSI_SCNTL0_TRG 0x01
32 #define LSI_SCNTL0_AAP 0x02
33 #define LSI_SCNTL0_EPC 0x08
34 #define LSI_SCNTL0_WATN 0x10
35 #define LSI_SCNTL0_START 0x20
37 #define LSI_SCNTL1_SST 0x01
38 #define LSI_SCNTL1_IARB 0x02
39 #define LSI_SCNTL1_AESP 0x04
40 #define LSI_SCNTL1_RST 0x08
41 #define LSI_SCNTL1_CON 0x10
42 #define LSI_SCNTL1_DHP 0x20
43 #define LSI_SCNTL1_ADB 0x40
44 #define LSI_SCNTL1_EXC 0x80
46 #define LSI_SCNTL2_WSR 0x01
47 #define LSI_SCNTL2_VUE0 0x02
48 #define LSI_SCNTL2_VUE1 0x04
49 #define LSI_SCNTL2_WSS 0x08
50 #define LSI_SCNTL2_SLPHBEN 0x10
51 #define LSI_SCNTL2_SLPMD 0x20
52 #define LSI_SCNTL2_CHM 0x40
53 #define LSI_SCNTL2_SDU 0x80
55 #define LSI_ISTAT0_DIP 0x01
56 #define LSI_ISTAT0_SIP 0x02
57 #define LSI_ISTAT0_INTF 0x04
58 #define LSI_ISTAT0_CON 0x08
59 #define LSI_ISTAT0_SEM 0x10
60 #define LSI_ISTAT0_SIGP 0x20
61 #define LSI_ISTAT0_SRST 0x40
62 #define LSI_ISTAT0_ABRT 0x80
64 #define LSI_ISTAT1_SI 0x01
65 #define LSI_ISTAT1_SRUN 0x02
66 #define LSI_ISTAT1_FLSH 0x04
68 #define LSI_SSTAT0_SDP0 0x01
69 #define LSI_SSTAT0_RST 0x02
70 #define LSI_SSTAT0_WOA 0x04
71 #define LSI_SSTAT0_LOA 0x08
72 #define LSI_SSTAT0_AIP 0x10
73 #define LSI_SSTAT0_OLF 0x20
74 #define LSI_SSTAT0_ORF 0x40
75 #define LSI_SSTAT0_ILF 0x80
77 #define LSI_SIST0_PAR 0x01
78 #define LSI_SIST0_RST 0x02
79 #define LSI_SIST0_UDC 0x04
80 #define LSI_SIST0_SGE 0x08
81 #define LSI_SIST0_RSL 0x10
82 #define LSI_SIST0_SEL 0x20
83 #define LSI_SIST0_CMP 0x40
84 #define LSI_SIST0_MA 0x80
86 #define LSI_SIST1_HTH 0x01
87 #define LSI_SIST1_GEN 0x02
88 #define LSI_SIST1_STO 0x04
89 #define LSI_SIST1_SBMC 0x10
91 #define LSI_SOCL_IO 0x01
92 #define LSI_SOCL_CD 0x02
93 #define LSI_SOCL_MSG 0x04
94 #define LSI_SOCL_ATN 0x08
95 #define LSI_SOCL_SEL 0x10
96 #define LSI_SOCL_BSY 0x20
97 #define LSI_SOCL_ACK 0x40
98 #define LSI_SOCL_REQ 0x80
100 #define LSI_DSTAT_IID 0x01
101 #define LSI_DSTAT_SIR 0x04
102 #define LSI_DSTAT_SSI 0x08
103 #define LSI_DSTAT_ABRT 0x10
104 #define LSI_DSTAT_BF 0x20
105 #define LSI_DSTAT_MDPE 0x40
106 #define LSI_DSTAT_DFE 0x80
108 #define LSI_DCNTL_COM 0x01
109 #define LSI_DCNTL_IRQD 0x02
110 #define LSI_DCNTL_STD 0x04
111 #define LSI_DCNTL_IRQM 0x08
112 #define LSI_DCNTL_SSM 0x10
113 #define LSI_DCNTL_PFEN 0x20
114 #define LSI_DCNTL_PFF 0x40
115 #define LSI_DCNTL_CLSE 0x80
117 #define LSI_DMODE_MAN 0x01
118 #define LSI_DMODE_BOF 0x02
119 #define LSI_DMODE_ERMP 0x04
120 #define LSI_DMODE_ERL 0x08
121 #define LSI_DMODE_DIOM 0x10
122 #define LSI_DMODE_SIOM 0x20
124 #define LSI_CTEST2_DACK 0x01
125 #define LSI_CTEST2_DREQ 0x02
126 #define LSI_CTEST2_TEOP 0x04
127 #define LSI_CTEST2_PCICIE 0x08
128 #define LSI_CTEST2_CM 0x10
129 #define LSI_CTEST2_CIO 0x20
130 #define LSI_CTEST2_SIGP 0x40
131 #define LSI_CTEST2_DDIR 0x80
133 #define LSI_CTEST5_BL2 0x04
134 #define LSI_CTEST5_DDIR 0x08
135 #define LSI_CTEST5_MASR 0x10
136 #define LSI_CTEST5_DFSN 0x20
137 #define LSI_CTEST5_BBCK 0x40
138 #define LSI_CTEST5_ADCK 0x80
140 #define LSI_CCNTL0_DILS 0x01
141 #define LSI_CCNTL0_DISFC 0x10
142 #define LSI_CCNTL0_ENNDJ 0x20
143 #define LSI_CCNTL0_PMJCTL 0x40
144 #define LSI_CCNTL0_ENPMJ 0x80
154 /* Maximum length of MSG IN data. */
155 #define LSI_MAX_MSGIN_LEN 8
157 /* Flag set if this is a tagged command. */
158 #define LSI_TAG_VALID (1 << 16)
170 uint32_t script_ram_base;
172 int carry; /* ??? Should this be an a visible register somewhere? */
174 /* Action to take at the end of a MSG IN phase.
175 0 = COMMAND, 1 = disconect, 2 = DATA OUT, 3 = DATA IN. */
178 uint8_t msg[LSI_MAX_MSGIN_LEN];
179 /* 0 if SCRIPTS are running or stopped.
180 * 1 if a Wait Reselect instruction has been issued.
181 * 2 if processing DMA from lsi_execute_script.
182 * 3 if a DMA operation is in progress. */
184 SCSIDevice *scsi_dev[LSI_MAX_DEVS];
185 SCSIDevice *current_dev;
187 /* The tag is a combination of the device ID and the SCSI tag. */
188 uint32_t current_tag;
189 uint32_t current_dma_len;
253 uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
255 /* Script ram is stored as 32-bit words in host byteorder. */
256 uint32_t script_ram[2048];
259 static void lsi_soft_reset(LSIState *s)
269 memset(s->scratch, 0, sizeof(s->scratch));
323 static uint8_t lsi_reg_readb(LSIState *s, int offset);
324 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val);
325 static void lsi_execute_script(LSIState *s);
327 static inline uint32_t read_dword(LSIState *s, uint32_t addr)
331 /* Optimize reading from SCRIPTS RAM. */
332 if ((addr & 0xffffe000) == s->script_ram_base) {
333 return s->script_ram[(addr & 0x1fff) >> 2];
335 cpu_physical_memory_read(addr, (uint8_t *)&buf, 4);
336 return cpu_to_le32(buf);
339 static void lsi_stop_script(LSIState *s)
341 s->istat1 &= ~LSI_ISTAT1_SRUN;
344 static void lsi_update_irq(LSIState *s)
347 static int last_level;
349 /* It's unclear whether the DIP/SIP bits should be cleared when the
350 Interrupt Status Registers are cleared or when istat0 is read.
351 We currently do the formwer, which seems to work. */
354 if (s->dstat & s->dien)
356 s->istat0 |= LSI_ISTAT0_DIP;
358 s->istat0 &= ~LSI_ISTAT0_DIP;
361 if (s->sist0 || s->sist1) {
362 if ((s->sist0 & s->sien0) || (s->sist1 & s->sien1))
364 s->istat0 |= LSI_ISTAT0_SIP;
366 s->istat0 &= ~LSI_ISTAT0_SIP;
368 if (s->istat0 & LSI_ISTAT0_INTF)
371 if (level != last_level) {
372 DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
373 level, s->dstat, s->sist1, s->sist0);
376 qemu_set_irq(s->pci_dev.irq[0], level);
379 /* Stop SCRIPTS execution and raise a SCSI interrupt. */
380 static void lsi_script_scsi_interrupt(LSIState *s, int stat0, int stat1)
385 DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
386 stat1, stat0, s->sist1, s->sist0);
389 /* Stop processor on fatal or unmasked interrupt. As a special hack
390 we don't stop processing when raising STO. Instead continue
391 execution and stop at the next insn that accesses the SCSI bus. */
392 mask0 = s->sien0 | ~(LSI_SIST0_CMP | LSI_SIST0_SEL | LSI_SIST0_RSL);
393 mask1 = s->sien1 | ~(LSI_SIST1_GEN | LSI_SIST1_HTH);
394 mask1 &= ~LSI_SIST1_STO;
395 if (s->sist0 & mask0 || s->sist1 & mask1) {
401 /* Stop SCRIPTS execution and raise a DMA interrupt. */
402 static void lsi_script_dma_interrupt(LSIState *s, int stat)
404 DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat, s->dstat);
410 static inline void lsi_set_phase(LSIState *s, int phase)
412 s->sstat1 = (s->sstat1 & ~PHASE_MASK) | phase;
415 static void lsi_bad_phase(LSIState *s, int out, int new_phase)
417 /* Trigger a phase mismatch. */
418 if (s->ccntl0 & LSI_CCNTL0_ENPMJ) {
419 if ((s->ccntl0 & LSI_CCNTL0_PMJCTL) || out) {
424 DPRINTF("Data phase mismatch jump to %08x\n", s->dsp);
426 DPRINTF("Phase mismatch interrupt\n");
427 lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
430 lsi_set_phase(s, new_phase);
434 /* Resume SCRIPTS execution after a DMA operation. */
435 static void lsi_resume_script(LSIState *s)
437 if (s->waiting != 2) {
439 lsi_execute_script(s);
445 /* Initiate a SCSI layer data transfer. */
446 static void lsi_do_dma(LSIState *s, int out)
451 if (!s->current_dma_len) {
452 /* Wait until data is available. */
453 DPRINTF("DMA no data available\n");
458 if (count > s->current_dma_len)
459 count = s->current_dma_len;
460 DPRINTF("DMA addr=0x%08x len=%d\n", s->dnad, count);
467 if (s->dma_buf == NULL) {
468 s->dma_buf = scsi_get_buf(s->current_dev, s->current_tag);
471 /* ??? Set SFBR to first data byte. */
473 cpu_physical_memory_read(addr, s->dma_buf, count);
475 cpu_physical_memory_write(addr, s->dma_buf, count);
477 s->current_dma_len -= count;
478 if (s->current_dma_len == 0) {
481 /* Write the data. */
482 scsi_write_data(s->current_dev, s->current_tag);
484 /* Request any remaining data. */
485 scsi_read_data(s->current_dev, s->current_tag);
489 lsi_resume_script(s);
494 /* Add a command to the queue. */
495 static void lsi_queue_command(LSIState *s)
499 DPRINTF("Queueing tag=0x%x\n", s->current_tag);
500 if (s->queue_len == s->active_commands) {
502 s->queue = realloc(s->queue, s->queue_len * sizeof(lsi_queue));
504 p = &s->queue[s->active_commands++];
505 p->tag = s->current_tag;
507 p->out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
510 /* Queue a byte for a MSG IN phase. */
511 static void lsi_add_msg_byte(LSIState *s, uint8_t data)
513 if (s->msg_len >= LSI_MAX_MSGIN_LEN) {
514 BADF("MSG IN data too long\n");
516 DPRINTF("MSG IN 0x%02x\n", data);
517 s->msg[s->msg_len++] = data;
521 /* Perform reselection to continue a command. */
522 static void lsi_reselect(LSIState *s, uint32_t tag)
529 for (n = 0; n < s->active_commands; n++) {
534 if (n == s->active_commands) {
535 BADF("Reselected non-existant command tag=0x%x\n", tag);
538 id = (tag >> 8) & 0xf;
540 DPRINTF("Reselected target %d\n", id);
541 s->current_dev = s->scsi_dev[id];
542 s->current_tag = tag;
543 s->scntl1 |= LSI_SCNTL1_CON;
544 lsi_set_phase(s, PHASE_MI);
545 s->msg_action = p->out ? 2 : 3;
546 s->current_dma_len = p->pending;
548 lsi_add_msg_byte(s, 0x80);
549 if (s->current_tag & LSI_TAG_VALID) {
550 lsi_add_msg_byte(s, 0x20);
551 lsi_add_msg_byte(s, tag & 0xff);
554 s->active_commands--;
555 if (n != s->active_commands) {
556 s->queue[n] = s->queue[s->active_commands];
560 /* Record that data is available for a queued command. Returns zero if
561 the device was reselected, nonzero if the IO is deferred. */
562 static int lsi_queue_tag(LSIState *s, uint32_t tag, uint32_t arg)
566 for (i = 0; i < s->active_commands; i++) {
570 BADF("Multiple IO pending for tag %d\n", tag);
573 if (s->waiting == 1) {
574 /* Reselect device. */
575 lsi_reselect(s, tag);
578 DPRINTF("Queueing IO tag=0x%x\n", tag);
584 BADF("IO with unknown tag %d\n", tag);
588 /* Callback to indicate that the SCSI layer has completed a transfer. */
589 static void lsi_command_complete(void *opaque, int reason, uint32_t tag,
592 LSIState *s = (LSIState *)opaque;
595 out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
596 if (reason == SCSI_REASON_DONE) {
597 DPRINTF("Command complete sense=%d\n", (int)arg);
599 if (s->waiting && s->dbc != 0) {
600 /* Raise phase mismatch for short transfers. */
601 lsi_bad_phase(s, out, PHASE_ST);
603 lsi_set_phase(s, PHASE_ST);
605 lsi_resume_script(s);
609 if (s->waiting == 1 || tag != s->current_tag) {
610 if (lsi_queue_tag(s, tag, arg))
613 DPRINTF("Data ready tag=0x%x len=%d\n", tag, arg);
614 s->current_dma_len = arg;
617 if (s->waiting == 1 || s->dbc == 0) {
618 lsi_resume_script(s);
624 static void lsi_do_command(LSIState *s)
629 DPRINTF("Send command len=%d\n", s->dbc);
632 cpu_physical_memory_read(s->dnad, buf, s->dbc);
634 n = scsi_send_command(s->current_dev, s->current_tag, buf, s->current_lun);
636 lsi_set_phase(s, PHASE_DI);
637 scsi_read_data(s->current_dev, s->current_tag);
639 lsi_set_phase(s, PHASE_DO);
640 scsi_write_data(s->current_dev, s->current_tag);
642 if (n && s->current_dma_len == 0) {
643 /* Command did not complete immediately so disconnect. */
644 lsi_add_msg_byte(s, 2); /* SAVE DATA POINTER */
645 lsi_add_msg_byte(s, 4); /* DISCONNECT */
646 lsi_set_phase(s, PHASE_MI);
648 lsi_queue_command(s);
652 static void lsi_do_status(LSIState *s)
655 DPRINTF("Get status len=%d sense=%d\n", s->dbc, s->sense);
657 BADF("Bad Status move\n");
661 cpu_physical_memory_write(s->dnad, &sense, 1);
662 lsi_set_phase(s, PHASE_MI);
664 lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */
667 static void lsi_disconnect(LSIState *s)
669 s->scntl1 &= ~LSI_SCNTL1_CON;
670 s->sstat1 &= ~PHASE_MASK;
673 static void lsi_do_msgin(LSIState *s)
676 DPRINTF("Message in len=%d/%d\n", s->dbc, s->msg_len);
681 cpu_physical_memory_write(s->dnad, s->msg, len);
682 /* Linux drivers rely on the last byte being in the SIDL. */
683 s->sidl = s->msg[len - 1];
686 memmove(s->msg, s->msg + len, s->msg_len);
688 /* ??? Check if ATN (not yet implemented) is asserted and maybe
689 switch to PHASE_MO. */
690 switch (s->msg_action) {
692 lsi_set_phase(s, PHASE_CMD);
698 lsi_set_phase(s, PHASE_DO);
701 lsi_set_phase(s, PHASE_DI);
709 /* Read the next byte during a MSGOUT phase. */
710 static uint8_t lsi_get_msgbyte(LSIState *s)
713 cpu_physical_memory_read(s->dnad, &data, 1);
719 static void lsi_do_msgout(LSIState *s)
724 DPRINTF("MSG out len=%d\n", s->dbc);
726 msg = lsi_get_msgbyte(s);
731 DPRINTF("MSG: Disconnect\n");
735 DPRINTF("MSG: No Operation\n");
736 lsi_set_phase(s, PHASE_CMD);
739 len = lsi_get_msgbyte(s);
740 msg = lsi_get_msgbyte(s);
741 DPRINTF("Extended message 0x%x (len %d)\n", msg, len);
744 DPRINTF("SDTR (ignored)\n");
748 DPRINTF("WDTR (ignored)\n");
755 case 0x20: /* SIMPLE queue */
756 s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
757 DPRINTF("SIMPLE queue tag=0x%x\n", s->current_tag & 0xff);
759 case 0x21: /* HEAD of queue */
760 BADF("HEAD queue not implemented\n");
761 s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
763 case 0x22: /* ORDERED queue */
764 BADF("ORDERED queue not implemented\n");
765 s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
768 if ((msg & 0x80) == 0) {
771 s->current_lun = msg & 7;
772 DPRINTF("Select LUN %d\n", s->current_lun);
773 lsi_set_phase(s, PHASE_CMD);
779 BADF("Unimplemented message 0x%02x\n", msg);
780 lsi_set_phase(s, PHASE_MI);
781 lsi_add_msg_byte(s, 7); /* MESSAGE REJECT */
785 /* Sign extend a 24-bit value. */
786 static inline int32_t sxt24(int32_t n)
788 return (n << 8) >> 8;
791 static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count)
794 uint8_t buf[TARGET_PAGE_SIZE];
796 DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest, src, count);
798 n = (count > TARGET_PAGE_SIZE) ? TARGET_PAGE_SIZE : count;
799 cpu_physical_memory_read(src, buf, n);
800 cpu_physical_memory_write(dest, buf, n);
807 static void lsi_wait_reselect(LSIState *s)
810 DPRINTF("Wait Reselect\n");
811 if (s->current_dma_len)
812 BADF("Reselect with pending DMA\n");
813 for (i = 0; i < s->active_commands; i++) {
814 if (s->queue[i].pending) {
815 lsi_reselect(s, s->queue[i].tag);
819 if (s->current_dma_len == 0) {
824 static void lsi_execute_script(LSIState *s)
830 s->istat1 |= LSI_ISTAT1_SRUN;
832 insn = read_dword(s, s->dsp);
833 addr = read_dword(s, s->dsp + 4);
834 DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s->dsp, insn, addr);
836 s->dcmd = insn >> 24;
838 switch (insn >> 30) {
839 case 0: /* Block move. */
840 if (s->sist1 & LSI_SIST1_STO) {
841 DPRINTF("Delayed select timeout\n");
845 s->dbc = insn & 0xffffff;
847 if (insn & (1 << 29)) {
848 /* Indirect addressing. */
849 addr = read_dword(s, addr);
850 } else if (insn & (1 << 28)) {
853 /* Table indirect addressing. */
854 offset = sxt24(addr);
855 cpu_physical_memory_read(s->dsa + offset, (uint8_t *)buf, 8);
856 s->dbc = cpu_to_le32(buf[0]);
858 addr = cpu_to_le32(buf[1]);
860 if ((s->sstat1 & PHASE_MASK) != ((insn >> 24) & 7)) {
861 DPRINTF("Wrong phase got %d expected %d\n",
862 s->sstat1 & PHASE_MASK, (insn >> 24) & 7);
863 lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
869 switch (s->sstat1 & 0x7) {
895 BADF("Unimplemented phase %d\n", s->sstat1 & PHASE_MASK);
898 s->dfifo = s->dbc & 0xff;
899 s->ctest5 = (s->ctest5 & 0xfc) | ((s->dbc >> 8) & 3);
902 s->ua = addr + s->dbc;
905 case 1: /* IO or Read/Write instruction. */
906 opcode = (insn >> 27) & 7;
910 if (insn & (1 << 25)) {
911 id = read_dword(s, s->dsa + sxt24(insn));
915 id = (id >> 16) & 0xf;
916 if (insn & (1 << 26)) {
917 addr = s->dsp + sxt24(addr);
923 if (s->current_dma_len && (s->ssid & 0xf) == id) {
924 DPRINTF("Already reselected by target %d\n", id);
927 s->sstat0 |= LSI_SSTAT0_WOA;
928 s->scntl1 &= ~LSI_SCNTL1_IARB;
929 if (id >= LSI_MAX_DEVS || !s->scsi_dev[id]) {
930 DPRINTF("Selected absent target %d\n", id);
931 lsi_script_scsi_interrupt(s, 0, LSI_SIST1_STO);
935 DPRINTF("Selected target %d%s\n",
936 id, insn & (1 << 3) ? " ATN" : "");
937 /* ??? Linux drivers compain when this is set. Maybe
938 it only applies in low-level mode (unimplemented).
939 lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
940 s->current_dev = s->scsi_dev[id];
941 s->current_tag = id << 8;
942 s->scntl1 |= LSI_SCNTL1_CON;
943 if (insn & (1 << 3)) {
944 s->socl |= LSI_SOCL_ATN;
946 lsi_set_phase(s, PHASE_MO);
948 case 1: /* Disconnect */
949 DPRINTF("Wait Disconect\n");
950 s->scntl1 &= ~LSI_SCNTL1_CON;
952 case 2: /* Wait Reselect */
953 lsi_wait_reselect(s);
956 DPRINTF("Set%s%s%s%s\n",
957 insn & (1 << 3) ? " ATN" : "",
958 insn & (1 << 6) ? " ACK" : "",
959 insn & (1 << 9) ? " TM" : "",
960 insn & (1 << 10) ? " CC" : "");
961 if (insn & (1 << 3)) {
962 s->socl |= LSI_SOCL_ATN;
963 lsi_set_phase(s, PHASE_MO);
965 if (insn & (1 << 9)) {
966 BADF("Target mode not implemented\n");
969 if (insn & (1 << 10))
973 DPRINTF("Clear%s%s%s%s\n",
974 insn & (1 << 3) ? " ATN" : "",
975 insn & (1 << 6) ? " ACK" : "",
976 insn & (1 << 9) ? " TM" : "",
977 insn & (1 << 10) ? " CC" : "");
978 if (insn & (1 << 3)) {
979 s->socl &= ~LSI_SOCL_ATN;
981 if (insn & (1 << 10))
992 static const char *opcode_names[3] =
993 {"Write", "Read", "Read-Modify-Write"};
994 static const char *operator_names[8] =
995 {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"};
998 reg = ((insn >> 16) & 0x7f) | (insn & 0x80);
999 data8 = (insn >> 8) & 0xff;
1000 opcode = (insn >> 27) & 7;
1001 operator = (insn >> 24) & 7;
1002 DPRINTF("%s reg 0x%x %s data8=0x%02x sfbr=0x%02x%s\n",
1003 opcode_names[opcode - 5], reg,
1004 operator_names[operator], data8, s->sfbr,
1005 (insn & (1 << 23)) ? " SFBR" : "");
1008 case 5: /* From SFBR */
1012 case 6: /* To SFBR */
1014 op0 = lsi_reg_readb(s, reg);
1017 case 7: /* Read-modify-write */
1019 op0 = lsi_reg_readb(s, reg);
1020 if (insn & (1 << 23)) {
1032 case 1: /* Shift left */
1034 op0 = (op0 << 1) | s->carry;
1048 op0 = (op0 >> 1) | (s->carry << 7);
1053 s->carry = op0 < op1;
1056 op0 += op1 + s->carry;
1058 s->carry = op0 <= op1;
1060 s->carry = op0 < op1;
1065 case 5: /* From SFBR */
1066 case 7: /* Read-modify-write */
1067 lsi_reg_writeb(s, reg, op0);
1069 case 6: /* To SFBR */
1076 case 2: /* Transfer Control. */
1081 if ((insn & 0x002e0000) == 0) {
1085 if (s->sist1 & LSI_SIST1_STO) {
1086 DPRINTF("Delayed select timeout\n");
1090 cond = jmp = (insn & (1 << 19)) != 0;
1091 if (cond == jmp && (insn & (1 << 21))) {
1092 DPRINTF("Compare carry %d\n", s->carry == jmp);
1093 cond = s->carry != 0;
1095 if (cond == jmp && (insn & (1 << 17))) {
1096 DPRINTF("Compare phase %d %c= %d\n",
1097 (s->sstat1 & PHASE_MASK),
1099 ((insn >> 24) & 7));
1100 cond = (s->sstat1 & PHASE_MASK) == ((insn >> 24) & 7);
1102 if (cond == jmp && (insn & (1 << 18))) {
1105 mask = (~insn >> 8) & 0xff;
1106 DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
1107 s->sfbr, mask, jmp ? '=' : '!', insn & mask);
1108 cond = (s->sfbr & mask) == (insn & mask);
1111 if (insn & (1 << 23)) {
1112 /* Relative address. */
1113 addr = s->dsp + sxt24(addr);
1115 switch ((insn >> 27) & 7) {
1117 DPRINTF("Jump to 0x%08x\n", addr);
1121 DPRINTF("Call 0x%08x\n", addr);
1125 case 2: /* Return */
1126 DPRINTF("Return to 0x%08x\n", s->temp);
1129 case 3: /* Interrupt */
1130 DPRINTF("Interrupt 0x%08x\n", s->dsps);
1131 if ((insn & (1 << 20)) != 0) {
1132 s->istat0 |= LSI_ISTAT0_INTF;
1135 lsi_script_dma_interrupt(s, LSI_DSTAT_SIR);
1139 DPRINTF("Illegal transfer control\n");
1140 lsi_script_dma_interrupt(s, LSI_DSTAT_IID);
1144 DPRINTF("Control condition failed\n");
1150 if ((insn & (1 << 29)) == 0) {
1153 /* ??? The docs imply the destination address is loaded into
1154 the TEMP register. However the Linux drivers rely on
1155 the value being presrved. */
1156 dest = read_dword(s, s->dsp);
1158 lsi_memcpy(s, dest, addr, insn & 0xffffff);
1165 if (insn & (1 << 28)) {
1166 addr = s->dsa + sxt24(addr);
1169 reg = (insn >> 16) & 0xff;
1170 if (insn & (1 << 24)) {
1171 cpu_physical_memory_read(addr, data, n);
1172 DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg, n,
1173 addr, *(int *)data);
1174 for (i = 0; i < n; i++) {
1175 lsi_reg_writeb(s, reg + i, data[i]);
1178 DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg, n, addr);
1179 for (i = 0; i < n; i++) {
1180 data[i] = lsi_reg_readb(s, reg + i);
1182 cpu_physical_memory_write(addr, data, n);
1186 /* ??? Need to avoid infinite loops. */
1187 if (s->istat1 & LSI_ISTAT1_SRUN && !s->waiting) {
1188 if (s->dcntl & LSI_DCNTL_SSM) {
1189 lsi_script_dma_interrupt(s, LSI_DSTAT_SSI);
1194 DPRINTF("SCRIPTS execution stopped\n");
1197 static uint8_t lsi_reg_readb(LSIState *s, int offset)
1200 #define CASE_GET_REG32(name, addr) \
1201 case addr: return s->name & 0xff; \
1202 case addr + 1: return (s->name >> 8) & 0xff; \
1203 case addr + 2: return (s->name >> 16) & 0xff; \
1204 case addr + 3: return (s->name >> 24) & 0xff;
1206 #ifdef DEBUG_LSI_REG
1207 DPRINTF("Read reg %x\n", offset);
1210 case 0x00: /* SCNTL0 */
1212 case 0x01: /* SCNTL1 */
1214 case 0x02: /* SCNTL2 */
1216 case 0x03: /* SCNTL3 */
1218 case 0x04: /* SCID */
1220 case 0x05: /* SXFER */
1222 case 0x06: /* SDID */
1224 case 0x07: /* GPREG0 */
1226 case 0xa: /* SSID */
1228 case 0xb: /* SBCL */
1229 /* ??? This is not correct. However it's (hopefully) only
1230 used for diagnostics, so should be ok. */
1232 case 0xc: /* DSTAT */
1233 tmp = s->dstat | 0x80;
1234 if ((s->istat0 & LSI_ISTAT0_INTF) == 0)
1238 case 0x0d: /* SSTAT0 */
1240 case 0x0e: /* SSTAT1 */
1242 case 0x0f: /* SSTAT2 */
1243 return s->scntl1 & LSI_SCNTL1_CON ? 0 : 2;
1244 CASE_GET_REG32(dsa, 0x10)
1245 case 0x14: /* ISTAT0 */
1247 case 0x16: /* MBOX0 */
1249 case 0x17: /* MBOX1 */
1251 case 0x18: /* CTEST0 */
1253 case 0x19: /* CTEST1 */
1255 case 0x1a: /* CTEST2 */
1256 tmp = LSI_CTEST2_DACK | LSI_CTEST2_CM;
1257 if (s->istat0 & LSI_ISTAT0_SIGP) {
1258 s->istat0 &= ~LSI_ISTAT0_SIGP;
1259 tmp |= LSI_CTEST2_SIGP;
1262 case 0x1b: /* CTEST3 */
1264 CASE_GET_REG32(temp, 0x1c)
1265 case 0x20: /* DFIFO */
1267 case 0x21: /* CTEST4 */
1269 case 0x22: /* CTEST5 */
1271 case 0x24: /* DBC[0:7] */
1272 return s->dbc & 0xff;
1273 case 0x25: /* DBC[8:15] */
1274 return (s->dbc >> 8) & 0xff;
1275 case 0x26: /* DBC[16->23] */
1276 return (s->dbc >> 16) & 0xff;
1277 case 0x27: /* DCMD */
1279 CASE_GET_REG32(dsp, 0x2c)
1280 CASE_GET_REG32(dsps, 0x30)
1281 CASE_GET_REG32(scratch[0], 0x34)
1282 case 0x38: /* DMODE */
1284 case 0x39: /* DIEN */
1286 case 0x3b: /* DCNTL */
1288 case 0x40: /* SIEN0 */
1290 case 0x41: /* SIEN1 */
1292 case 0x42: /* SIST0 */
1297 case 0x43: /* SIST1 */
1302 case 0x47: /* GPCNTL0 */
1304 case 0x48: /* STIME0 */
1306 case 0x4a: /* RESPID0 */
1308 case 0x4b: /* RESPID1 */
1310 case 0x4d: /* STEST1 */
1312 case 0x4e: /* STEST2 */
1314 case 0x4f: /* STEST3 */
1316 case 0x50: /* SIDL */
1317 /* This is needed by the linux drivers. We currently only update it
1318 during the MSG IN phase. */
1320 case 0x52: /* STEST4 */
1322 case 0x56: /* CCNTL0 */
1324 case 0x57: /* CCNTL1 */
1326 case 0x58: /* SBDL */
1327 /* Some drivers peek at the data bus during the MSG IN phase. */
1328 if ((s->sstat1 & PHASE_MASK) == PHASE_MI)
1331 case 0x59: /* SBDL high */
1333 CASE_GET_REG32(mmrs, 0xa0)
1334 CASE_GET_REG32(mmws, 0xa4)
1335 CASE_GET_REG32(sfs, 0xa8)
1336 CASE_GET_REG32(drs, 0xac)
1337 CASE_GET_REG32(sbms, 0xb0)
1338 CASE_GET_REG32(dmbs, 0xb4)
1339 CASE_GET_REG32(dnad64, 0xb8)
1340 CASE_GET_REG32(pmjad1, 0xc0)
1341 CASE_GET_REG32(pmjad2, 0xc4)
1342 CASE_GET_REG32(rbc, 0xc8)
1343 CASE_GET_REG32(ua, 0xcc)
1344 CASE_GET_REG32(ia, 0xd4)
1345 CASE_GET_REG32(sbc, 0xd8)
1346 CASE_GET_REG32(csbc, 0xdc)
1348 if (offset >= 0x5c && offset < 0xa0) {
1351 n = (offset - 0x58) >> 2;
1352 shift = (offset & 3) * 8;
1353 return (s->scratch[n] >> shift) & 0xff;
1355 BADF("readb 0x%x\n", offset);
1357 #undef CASE_GET_REG32
1360 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
1362 #define CASE_SET_REG32(name, addr) \
1363 case addr : s->name &= 0xffffff00; s->name |= val; break; \
1364 case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \
1365 case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \
1366 case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break;
1368 #ifdef DEBUG_LSI_REG
1369 DPRINTF("Write reg %x = %02x\n", offset, val);
1372 case 0x00: /* SCNTL0 */
1374 if (val & LSI_SCNTL0_START) {
1375 BADF("Start sequence not implemented\n");
1378 case 0x01: /* SCNTL1 */
1379 s->scntl1 = val & ~LSI_SCNTL1_SST;
1380 if (val & LSI_SCNTL1_IARB) {
1381 BADF("Immediate Arbritration not implemented\n");
1383 if (val & LSI_SCNTL1_RST) {
1384 s->sstat0 |= LSI_SSTAT0_RST;
1385 lsi_script_scsi_interrupt(s, LSI_SIST0_RST, 0);
1387 s->sstat0 &= ~LSI_SSTAT0_RST;
1390 case 0x02: /* SCNTL2 */
1391 val &= ~(LSI_SCNTL2_WSR | LSI_SCNTL2_WSS);
1394 case 0x03: /* SCNTL3 */
1397 case 0x04: /* SCID */
1400 case 0x05: /* SXFER */
1403 case 0x06: /* SDID */
1404 if ((val & 0xf) != (s->ssid & 0xf))
1405 BADF("Destination ID does not match SSID\n");
1406 s->sdid = val & 0xf;
1408 case 0x07: /* GPREG0 */
1410 case 0x08: /* SFBR */
1411 /* The CPU is not allowed to write to this register. However the
1412 SCRIPTS register move instructions are. */
1415 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1416 /* Linux writes to these readonly registers on startup. */
1418 CASE_SET_REG32(dsa, 0x10)
1419 case 0x14: /* ISTAT0 */
1420 s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0);
1421 if (val & LSI_ISTAT0_ABRT) {
1422 lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT);
1424 if (val & LSI_ISTAT0_INTF) {
1425 s->istat0 &= ~LSI_ISTAT0_INTF;
1428 if (s->waiting == 1 && val & LSI_ISTAT0_SIGP) {
1429 DPRINTF("Woken by SIGP\n");
1432 lsi_execute_script(s);
1434 if (val & LSI_ISTAT0_SRST) {
1438 case 0x16: /* MBOX0 */
1441 case 0x17: /* MBOX1 */
1444 case 0x1b: /* CTEST3 */
1445 s->ctest3 = val & 0x0f;
1447 CASE_SET_REG32(temp, 0x1c)
1448 case 0x21: /* CTEST4 */
1450 BADF("Unimplemented CTEST4-FBL 0x%x\n", val);
1454 case 0x22: /* CTEST5 */
1455 if (val & (LSI_CTEST5_ADCK | LSI_CTEST5_BBCK)) {
1456 BADF("CTEST5 DMA increment not implemented\n");
1460 case 0x2c: /* DSP[0:7] */
1461 s->dsp &= 0xffffff00;
1464 case 0x2d: /* DSP[8:15] */
1465 s->dsp &= 0xffff00ff;
1468 case 0x2e: /* DSP[16:23] */
1469 s->dsp &= 0xff00ffff;
1470 s->dsp |= val << 16;
1472 case 0x2f: /* DSP[24:31] */
1473 s->dsp &= 0x00ffffff;
1474 s->dsp |= val << 24;
1475 if ((s->dmode & LSI_DMODE_MAN) == 0
1476 && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1477 lsi_execute_script(s);
1479 CASE_SET_REG32(dsps, 0x30)
1480 CASE_SET_REG32(scratch[0], 0x34)
1481 case 0x38: /* DMODE */
1482 if (val & (LSI_DMODE_SIOM | LSI_DMODE_DIOM)) {
1483 BADF("IO mappings not implemented\n");
1487 case 0x39: /* DIEN */
1491 case 0x3b: /* DCNTL */
1492 s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD);
1493 if ((val & LSI_DCNTL_STD) && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1494 lsi_execute_script(s);
1496 case 0x40: /* SIEN0 */
1500 case 0x41: /* SIEN1 */
1504 case 0x47: /* GPCNTL0 */
1506 case 0x48: /* STIME0 */
1509 case 0x49: /* STIME1 */
1511 DPRINTF("General purpose timer not implemented\n");
1512 /* ??? Raising the interrupt immediately seems to be sufficient
1513 to keep the FreeBSD driver happy. */
1514 lsi_script_scsi_interrupt(s, 0, LSI_SIST1_GEN);
1517 case 0x4a: /* RESPID0 */
1520 case 0x4b: /* RESPID1 */
1523 case 0x4d: /* STEST1 */
1526 case 0x4e: /* STEST2 */
1528 BADF("Low level mode not implemented\n");
1532 case 0x4f: /* STEST3 */
1534 BADF("SCSI FIFO test mode not implemented\n");
1538 case 0x56: /* CCNTL0 */
1541 case 0x57: /* CCNTL1 */
1544 CASE_SET_REG32(mmrs, 0xa0)
1545 CASE_SET_REG32(mmws, 0xa4)
1546 CASE_SET_REG32(sfs, 0xa8)
1547 CASE_SET_REG32(drs, 0xac)
1548 CASE_SET_REG32(sbms, 0xb0)
1549 CASE_SET_REG32(dmbs, 0xb4)
1550 CASE_SET_REG32(dnad64, 0xb8)
1551 CASE_SET_REG32(pmjad1, 0xc0)
1552 CASE_SET_REG32(pmjad2, 0xc4)
1553 CASE_SET_REG32(rbc, 0xc8)
1554 CASE_SET_REG32(ua, 0xcc)
1555 CASE_SET_REG32(ia, 0xd4)
1556 CASE_SET_REG32(sbc, 0xd8)
1557 CASE_SET_REG32(csbc, 0xdc)
1559 if (offset >= 0x5c && offset < 0xa0) {
1562 n = (offset - 0x58) >> 2;
1563 shift = (offset & 3) * 8;
1564 s->scratch[n] &= ~(0xff << shift);
1565 s->scratch[n] |= (val & 0xff) << shift;
1567 BADF("Unhandled writeb 0x%x = 0x%x\n", offset, val);
1570 #undef CASE_SET_REG32
1573 static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1575 LSIState *s = (LSIState *)opaque;
1577 lsi_reg_writeb(s, addr & 0xff, val);
1580 static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1582 LSIState *s = (LSIState *)opaque;
1585 lsi_reg_writeb(s, addr, val & 0xff);
1586 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1589 static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1591 LSIState *s = (LSIState *)opaque;
1594 lsi_reg_writeb(s, addr, val & 0xff);
1595 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1596 lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1597 lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1600 static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr)
1602 LSIState *s = (LSIState *)opaque;
1604 return lsi_reg_readb(s, addr & 0xff);
1607 static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
1609 LSIState *s = (LSIState *)opaque;
1613 val = lsi_reg_readb(s, addr);
1614 val |= lsi_reg_readb(s, addr + 1) << 8;
1618 static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr)
1620 LSIState *s = (LSIState *)opaque;
1623 val = lsi_reg_readb(s, addr);
1624 val |= lsi_reg_readb(s, addr + 1) << 8;
1625 val |= lsi_reg_readb(s, addr + 2) << 16;
1626 val |= lsi_reg_readb(s, addr + 3) << 24;
1630 static CPUReadMemoryFunc *lsi_mmio_readfn[3] = {
1636 static CPUWriteMemoryFunc *lsi_mmio_writefn[3] = {
1642 static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1644 LSIState *s = (LSIState *)opaque;
1649 newval = s->script_ram[addr >> 2];
1650 shift = (addr & 3) * 8;
1651 newval &= ~(0xff << shift);
1652 newval |= val << shift;
1653 s->script_ram[addr >> 2] = newval;
1656 static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1658 LSIState *s = (LSIState *)opaque;
1662 newval = s->script_ram[addr >> 2];
1664 newval = (newval & 0xffff) | (val << 16);
1666 newval = (newval & 0xffff0000) | val;
1668 s->script_ram[addr >> 2] = newval;
1672 static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1674 LSIState *s = (LSIState *)opaque;
1677 s->script_ram[addr >> 2] = val;
1680 static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
1682 LSIState *s = (LSIState *)opaque;
1686 val = s->script_ram[addr >> 2];
1687 val >>= (addr & 3) * 8;
1691 static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr)
1693 LSIState *s = (LSIState *)opaque;
1697 val = s->script_ram[addr >> 2];
1700 return le16_to_cpu(val);
1703 static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr)
1705 LSIState *s = (LSIState *)opaque;
1708 return le32_to_cpu(s->script_ram[addr >> 2]);
1711 static CPUReadMemoryFunc *lsi_ram_readfn[3] = {
1717 static CPUWriteMemoryFunc *lsi_ram_writefn[3] = {
1723 static uint32_t lsi_io_readb(void *opaque, uint32_t addr)
1725 LSIState *s = (LSIState *)opaque;
1726 return lsi_reg_readb(s, addr & 0xff);
1729 static uint32_t lsi_io_readw(void *opaque, uint32_t addr)
1731 LSIState *s = (LSIState *)opaque;
1734 val = lsi_reg_readb(s, addr);
1735 val |= lsi_reg_readb(s, addr + 1) << 8;
1739 static uint32_t lsi_io_readl(void *opaque, uint32_t addr)
1741 LSIState *s = (LSIState *)opaque;
1744 val = lsi_reg_readb(s, addr);
1745 val |= lsi_reg_readb(s, addr + 1) << 8;
1746 val |= lsi_reg_readb(s, addr + 2) << 16;
1747 val |= lsi_reg_readb(s, addr + 3) << 24;
1751 static void lsi_io_writeb(void *opaque, uint32_t addr, uint32_t val)
1753 LSIState *s = (LSIState *)opaque;
1754 lsi_reg_writeb(s, addr & 0xff, val);
1757 static void lsi_io_writew(void *opaque, uint32_t addr, uint32_t val)
1759 LSIState *s = (LSIState *)opaque;
1761 lsi_reg_writeb(s, addr, val & 0xff);
1762 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1765 static void lsi_io_writel(void *opaque, uint32_t addr, uint32_t val)
1767 LSIState *s = (LSIState *)opaque;
1769 lsi_reg_writeb(s, addr, val & 0xff);
1770 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1771 lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1772 lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1775 static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
1776 uint32_t addr, uint32_t size, int type)
1778 LSIState *s = (LSIState *)pci_dev;
1780 DPRINTF("Mapping IO at %08x\n", addr);
1782 register_ioport_write(addr, 256, 1, lsi_io_writeb, s);
1783 register_ioport_read(addr, 256, 1, lsi_io_readb, s);
1784 register_ioport_write(addr, 256, 2, lsi_io_writew, s);
1785 register_ioport_read(addr, 256, 2, lsi_io_readw, s);
1786 register_ioport_write(addr, 256, 4, lsi_io_writel, s);
1787 register_ioport_read(addr, 256, 4, lsi_io_readl, s);
1790 static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
1791 uint32_t addr, uint32_t size, int type)
1793 LSIState *s = (LSIState *)pci_dev;
1795 DPRINTF("Mapping ram at %08x\n", addr);
1796 s->script_ram_base = addr;
1797 cpu_register_physical_memory(addr + 0, 0x2000, s->ram_io_addr);
1800 static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
1801 uint32_t addr, uint32_t size, int type)
1803 LSIState *s = (LSIState *)pci_dev;
1805 DPRINTF("Mapping registers at %08x\n", addr);
1806 cpu_register_physical_memory(addr + 0, 0x400, s->mmio_io_addr);
1809 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id)
1811 LSIState *s = (LSIState *)opaque;
1814 for (id = 0; id < LSI_MAX_DEVS; id++) {
1815 if (s->scsi_dev[id] == NULL)
1819 if (id >= LSI_MAX_DEVS) {
1820 BADF("Bad Device ID %d\n", id);
1823 if (s->scsi_dev[id]) {
1824 DPRINTF("Destroying device %d\n", id);
1825 scsi_disk_destroy(s->scsi_dev[id]);
1827 DPRINTF("Attaching block device %d\n", id);
1828 s->scsi_dev[id] = scsi_disk_init(bd, 1, lsi_command_complete, s);
1831 void *lsi_scsi_init(PCIBus *bus, int devfn)
1835 s = (LSIState *)pci_register_device(bus, "LSI53C895A SCSI HBA",
1836 sizeof(*s), devfn, NULL, NULL);
1838 fprintf(stderr, "lsi-scsi: Failed to register PCI device\n");
1842 s->pci_dev.config[0x00] = 0x00;
1843 s->pci_dev.config[0x01] = 0x10;
1844 s->pci_dev.config[0x02] = 0x12;
1845 s->pci_dev.config[0x03] = 0x00;
1846 s->pci_dev.config[0x0b] = 0x01;
1847 s->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */
1849 s->mmio_io_addr = cpu_register_io_memory(0, lsi_mmio_readfn,
1850 lsi_mmio_writefn, s);
1851 s->ram_io_addr = cpu_register_io_memory(0, lsi_ram_readfn,
1852 lsi_ram_writefn, s);
1854 pci_register_io_region((struct PCIDevice *)s, 0, 256,
1855 PCI_ADDRESS_SPACE_IO, lsi_io_mapfunc);
1856 pci_register_io_region((struct PCIDevice *)s, 1, 0x400,
1857 PCI_ADDRESS_SPACE_MEM, lsi_mmio_mapfunc);
1858 pci_register_io_region((struct PCIDevice *)s, 2, 0x2000,
1859 PCI_ADDRESS_SPACE_MEM, lsi_ram_mapfunc);
1860 s->queue = qemu_malloc(sizeof(lsi_queue));
1862 s->active_commands = 0;