2 * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
4 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #if defined(DEBUG_NVRAM)
30 #define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
32 #define NVRAM_PRINTF(fmt, args...) do { } while (0)
36 * The M48T08 and M48T59 chips are very similar. The newer '59 has
37 * alarm and a watchdog timer and related control registers. In the
38 * PPC platform there is also a nvram lock function.
41 /* Model parameters */
42 int type; // 8 = m48t08, 59 = m48t59
43 /* Hardware parameters */
46 target_phys_addr_t mem_base;
52 /* Alarm & watchdog */
54 struct QEMUTimer *alrm_timer;
55 struct QEMUTimer *wd_timer;
62 /* Fake timer functions */
63 /* Generic helpers for BCD */
64 static inline uint8_t toBCD (uint8_t value)
66 return (((value / 10) % 10) << 4) | (value % 10);
69 static inline uint8_t fromBCD (uint8_t BCD)
71 return ((BCD >> 4) * 10) + (BCD & 0x0F);
74 /* RTC management helpers */
75 static void get_time (m48t59_t *NVRAM, struct tm *tm)
79 t = time(NULL) + NVRAM->time_offset;
81 memcpy(tm,localtime(&t),sizeof(*tm));
86 localtime_r (&t, tm) ;
90 static void set_time (m48t59_t *NVRAM, struct tm *tm)
94 new_time = mktime(tm);
96 NVRAM->time_offset = new_time - now;
99 /* Alarm management */
100 static void alarm_cb (void *opaque)
102 struct tm tm, tm_now;
104 m48t59_t *NVRAM = opaque;
106 qemu_set_irq(NVRAM->IRQ, 1);
107 if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
108 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
109 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
110 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
111 /* Repeat once a month */
112 get_time(NVRAM, &tm_now);
113 memcpy(&tm, &tm_now, sizeof(struct tm));
115 if (tm.tm_mon == 13) {
119 next_time = mktime(&tm);
120 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
121 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
122 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
123 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
124 /* Repeat once a day */
125 next_time = 24 * 60 * 60 + mktime(&tm_now);
126 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
127 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
128 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
129 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
130 /* Repeat once an hour */
131 next_time = 60 * 60 + mktime(&tm_now);
132 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
133 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
134 (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
135 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
136 /* Repeat once a minute */
137 next_time = 60 + mktime(&tm_now);
139 /* Repeat once a second */
140 next_time = 1 + mktime(&tm_now);
142 qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
143 qemu_set_irq(NVRAM->IRQ, 0);
147 static void get_alarm (m48t59_t *NVRAM, struct tm *tm)
150 memcpy(tm,localtime(&NVRAM->alarm),sizeof(*tm));
153 gmtime_r (&NVRAM->alarm, tm);
155 localtime_r (&NVRAM->alarm, tm);
159 static void set_alarm (m48t59_t *NVRAM, struct tm *tm)
161 NVRAM->alarm = mktime(tm);
162 if (NVRAM->alrm_timer != NULL) {
163 qemu_del_timer(NVRAM->alrm_timer);
164 if (NVRAM->alarm - time(NULL) > 0)
165 qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
169 /* Watchdog management */
170 static void watchdog_cb (void *opaque)
172 m48t59_t *NVRAM = opaque;
174 NVRAM->buffer[0x1FF0] |= 0x80;
175 if (NVRAM->buffer[0x1FF7] & 0x80) {
176 NVRAM->buffer[0x1FF7] = 0x00;
177 NVRAM->buffer[0x1FFC] &= ~0x40;
178 /* May it be a hw CPU Reset instead ? */
179 qemu_system_reset_request();
181 qemu_set_irq(NVRAM->IRQ, 1);
182 qemu_set_irq(NVRAM->IRQ, 0);
186 static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
188 uint64_t interval; /* in 1/16 seconds */
190 NVRAM->buffer[0x1FF0] &= ~0x80;
191 if (NVRAM->wd_timer != NULL) {
192 qemu_del_timer(NVRAM->wd_timer);
194 interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
195 qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
196 ((interval * 1000) >> 4));
201 /* Direct access to NVRAM */
202 void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
204 m48t59_t *NVRAM = opaque;
208 if (addr > 0x1FF8 && addr < 0x2000)
209 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
210 if (NVRAM->type == 8 &&
211 (addr >= 0x1ff0 && addr <= 0x1ff7))
215 /* flags register : read-only */
222 tmp = fromBCD(val & 0x7F);
223 if (tmp >= 0 && tmp <= 59) {
224 get_alarm(NVRAM, &tm);
226 NVRAM->buffer[0x1FF2] = val;
227 set_alarm(NVRAM, &tm);
232 tmp = fromBCD(val & 0x7F);
233 if (tmp >= 0 && tmp <= 59) {
234 get_alarm(NVRAM, &tm);
236 NVRAM->buffer[0x1FF3] = val;
237 set_alarm(NVRAM, &tm);
242 tmp = fromBCD(val & 0x3F);
243 if (tmp >= 0 && tmp <= 23) {
244 get_alarm(NVRAM, &tm);
246 NVRAM->buffer[0x1FF4] = val;
247 set_alarm(NVRAM, &tm);
252 tmp = fromBCD(val & 0x1F);
254 get_alarm(NVRAM, &tm);
256 NVRAM->buffer[0x1FF5] = val;
257 set_alarm(NVRAM, &tm);
262 NVRAM->buffer[0x1FF6] = val;
266 NVRAM->buffer[0x1FF7] = val;
267 set_up_watchdog(NVRAM, val);
271 NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90;
275 tmp = fromBCD(val & 0x7F);
276 if (tmp >= 0 && tmp <= 59) {
277 get_time(NVRAM, &tm);
279 set_time(NVRAM, &tm);
281 if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) {
283 NVRAM->stop_time = time(NULL);
285 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
286 NVRAM->stop_time = 0;
289 NVRAM->buffer[0x1FF9] = val & 0x80;
293 tmp = fromBCD(val & 0x7F);
294 if (tmp >= 0 && tmp <= 59) {
295 get_time(NVRAM, &tm);
297 set_time(NVRAM, &tm);
302 tmp = fromBCD(val & 0x3F);
303 if (tmp >= 0 && tmp <= 23) {
304 get_time(NVRAM, &tm);
306 set_time(NVRAM, &tm);
310 /* day of the week / century */
311 tmp = fromBCD(val & 0x07);
312 get_time(NVRAM, &tm);
314 set_time(NVRAM, &tm);
315 NVRAM->buffer[0x1FFC] = val & 0x40;
319 tmp = fromBCD(val & 0x1F);
321 get_time(NVRAM, &tm);
323 set_time(NVRAM, &tm);
328 tmp = fromBCD(val & 0x1F);
329 if (tmp >= 1 && tmp <= 12) {
330 get_time(NVRAM, &tm);
332 set_time(NVRAM, &tm);
338 if (tmp >= 0 && tmp <= 99) {
339 get_time(NVRAM, &tm);
340 if (NVRAM->type == 8)
341 tm.tm_year = fromBCD(val) + 68; // Base year is 1968
343 tm.tm_year = fromBCD(val);
344 set_time(NVRAM, &tm);
348 /* Check lock registers state */
349 if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
351 if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
354 if (addr < NVRAM->size) {
355 NVRAM->buffer[addr] = val & 0xFF;
361 uint32_t m48t59_read (void *opaque, uint32_t addr)
363 m48t59_t *NVRAM = opaque;
365 uint32_t retval = 0xFF;
367 if (NVRAM->type == 8 &&
368 (addr >= 0x1ff0 && addr <= 0x1ff7))
394 /* A read resets the watchdog */
395 set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
402 get_time(NVRAM, &tm);
403 retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec);
407 get_time(NVRAM, &tm);
408 retval = toBCD(tm.tm_min);
412 get_time(NVRAM, &tm);
413 retval = toBCD(tm.tm_hour);
416 /* day of the week / century */
417 get_time(NVRAM, &tm);
418 retval = NVRAM->buffer[0x1FFC] | tm.tm_wday;
422 get_time(NVRAM, &tm);
423 retval = toBCD(tm.tm_mday);
427 get_time(NVRAM, &tm);
428 retval = toBCD(tm.tm_mon + 1);
432 get_time(NVRAM, &tm);
433 if (NVRAM->type == 8)
434 retval = toBCD(tm.tm_year - 68); // Base year is 1968
436 retval = toBCD(tm.tm_year);
439 /* Check lock registers state */
440 if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
442 if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
445 if (addr < NVRAM->size) {
446 retval = NVRAM->buffer[addr];
450 if (addr > 0x1FF9 && addr < 0x2000)
451 NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr, retval);
456 void m48t59_set_addr (void *opaque, uint32_t addr)
458 m48t59_t *NVRAM = opaque;
463 void m48t59_toggle_lock (void *opaque, int lock)
465 m48t59_t *NVRAM = opaque;
467 NVRAM->lock ^= 1 << lock;
470 /* IO access to NVRAM */
471 static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
473 m48t59_t *NVRAM = opaque;
475 addr -= NVRAM->io_base;
476 NVRAM_PRINTF("0x%08x => 0x%08x\n", addr, val);
479 NVRAM->addr &= ~0x00FF;
483 NVRAM->addr &= ~0xFF00;
484 NVRAM->addr |= val << 8;
487 m48t59_write(NVRAM, val, NVRAM->addr);
488 NVRAM->addr = 0x0000;
495 static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
497 m48t59_t *NVRAM = opaque;
500 addr -= NVRAM->io_base;
503 retval = m48t59_read(NVRAM, NVRAM->addr);
509 NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr, retval);
514 static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
516 m48t59_t *NVRAM = opaque;
518 addr -= NVRAM->mem_base;
519 m48t59_write(NVRAM, addr, value & 0xff);
522 static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
524 m48t59_t *NVRAM = opaque;
526 addr -= NVRAM->mem_base;
527 m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
528 m48t59_write(NVRAM, addr + 1, value & 0xff);
531 static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
533 m48t59_t *NVRAM = opaque;
535 addr -= NVRAM->mem_base;
536 m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
537 m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
538 m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
539 m48t59_write(NVRAM, addr + 3, value & 0xff);
542 static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
544 m48t59_t *NVRAM = opaque;
547 addr -= NVRAM->mem_base;
548 retval = m48t59_read(NVRAM, addr);
552 static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
554 m48t59_t *NVRAM = opaque;
557 addr -= NVRAM->mem_base;
558 retval = m48t59_read(NVRAM, addr) << 8;
559 retval |= m48t59_read(NVRAM, addr + 1);
563 static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
565 m48t59_t *NVRAM = opaque;
568 addr -= NVRAM->mem_base;
569 retval = m48t59_read(NVRAM, addr) << 24;
570 retval |= m48t59_read(NVRAM, addr + 1) << 16;
571 retval |= m48t59_read(NVRAM, addr + 2) << 8;
572 retval |= m48t59_read(NVRAM, addr + 3);
576 static CPUWriteMemoryFunc *nvram_write[] = {
582 static CPUReadMemoryFunc *nvram_read[] = {
588 static void m48t59_save(QEMUFile *f, void *opaque)
590 m48t59_t *s = opaque;
592 qemu_put_8s(f, &s->lock);
593 qemu_put_be16s(f, &s->addr);
594 qemu_put_buffer(f, s->buffer, s->size);
597 static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
599 m48t59_t *s = opaque;
604 qemu_get_8s(f, &s->lock);
605 qemu_get_be16s(f, &s->addr);
606 qemu_get_buffer(f, s->buffer, s->size);
611 static void m48t59_reset(void *opaque)
613 m48t59_t *NVRAM = opaque;
615 if (NVRAM->alrm_timer != NULL)
616 qemu_del_timer(NVRAM->alrm_timer);
618 if (NVRAM->wd_timer != NULL)
619 qemu_del_timer(NVRAM->wd_timer);
622 /* Initialisation routine */
623 m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
624 uint32_t io_base, uint16_t size,
628 target_phys_addr_t save_base;
630 s = qemu_mallocz(sizeof(m48t59_t));
633 s->buffer = qemu_mallocz(size);
640 s->mem_base = mem_base;
641 s->io_base = io_base;
645 register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
646 register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
649 s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
650 cpu_register_physical_memory(mem_base, 0x4000, s->mem_index);
653 s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
654 s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
658 qemu_register_reset(m48t59_reset, s);
659 save_base = mem_base ? mem_base : io_base;
660 register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s);