2 * QEMU M48T59 NVRAM emulation for PPC PREP platform
4 * Copyright (c) 2003-2004 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include <stdio.h> /* needed by vl.h */
35 #if defined(NVRAM_DEBUG)
36 #define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
38 #define NVRAM_PRINTF(fmt, args...) do { } while (0)
41 typedef struct m48t59_t {
42 /* Hardware parameters */
49 /* Alarm & watchdog */
51 struct QEMUTimer *alrm_timer;
52 struct QEMUTimer *wd_timer;
58 static m48t59_t *NVRAMs;
61 /* Fake timer functions */
62 /* Generic helpers for BCD */
63 static inline uint8_t toBCD (uint8_t value)
65 return (((value / 10) % 10) << 4) | (value % 10);
68 static inline uint8_t fromBCD (uint8_t BCD)
70 return ((BCD >> 4) * 10) + (BCD & 0x0F);
73 /* RTC management helpers */
74 static void get_time (m48t59_t *NVRAM, struct tm *tm)
78 t = time(NULL) + NVRAM->time_offset;
82 static void set_time (m48t59_t *NVRAM, struct tm *tm)
86 new_time = mktime(tm);
88 NVRAM->time_offset = new_time - now;
91 /* Alarm management */
92 static void alarm_cb (void *opaque)
96 m48t59_t *NVRAM = opaque;
98 pic_set_irq(NVRAM->IRQ, 1);
99 if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
100 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
101 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
102 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
103 /* Repeat once a month */
104 get_time(NVRAM, &tm_now);
105 memcpy(&tm, &tm_now, sizeof(struct tm));
107 if (tm.tm_mon == 13) {
111 next_time = mktime(&tm);
112 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
113 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
114 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
115 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
116 /* Repeat once a day */
117 next_time = 24 * 60 * 60 + mktime(&tm_now);
118 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
119 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
120 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
121 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
122 /* Repeat once an hour */
123 next_time = 60 * 60 + mktime(&tm_now);
124 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
125 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
126 (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
127 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
128 /* Repeat once a minute */
129 next_time = 60 + mktime(&tm_now);
131 /* Repeat once a second */
132 next_time = 1 + mktime(&tm_now);
134 qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
135 pic_set_irq(NVRAM->IRQ, 0);
139 static void get_alarm (m48t59_t *NVRAM, struct tm *tm)
141 localtime_r(&NVRAM->alarm, tm);
144 static void set_alarm (m48t59_t *NVRAM, struct tm *tm)
146 NVRAM->alarm = mktime(tm);
147 if (NVRAM->alrm_timer != NULL) {
148 qemu_del_timer(NVRAM->alrm_timer);
149 NVRAM->alrm_timer = NULL;
151 if (NVRAM->alarm - time(NULL) > 0)
152 qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
155 /* Watchdog management */
156 static void watchdog_cb (void *opaque)
158 m48t59_t *NVRAM = opaque;
160 NVRAM->buffer[0x1FF0] |= 0x80;
161 if (NVRAM->buffer[0x1FF7] & 0x80) {
162 NVRAM->buffer[0x1FF7] = 0x00;
163 NVRAM->buffer[0x1FFC] &= ~0x40;
166 pic_set_irq(NVRAM->IRQ, 1);
167 pic_set_irq(NVRAM->IRQ, 0);
171 static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
173 uint64_t interval; /* in 1/16 seconds */
175 if (NVRAM->wd_timer != NULL) {
176 qemu_del_timer(NVRAM->wd_timer);
177 NVRAM->wd_timer = NULL;
179 NVRAM->buffer[0x1FF0] &= ~0x80;
181 interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
182 qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
183 ((interval * 1000) >> 4));
187 /* Direct access to NVRAM */
188 void m48t59_write (void *opaque, uint32_t val)
190 m48t59_t *NVRAM = opaque;
194 if (NVRAM->addr > 0x1FF8 && NVRAM->addr < 0x2000)
195 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, NVRAM->addr, val);
196 switch (NVRAM->addr) {
198 /* flags register : read-only */
205 tmp = fromBCD(val & 0x7F);
206 if (tmp >= 0 && tmp <= 59) {
207 get_alarm(NVRAM, &tm);
209 NVRAM->buffer[0x1FF2] = val;
210 set_alarm(NVRAM, &tm);
215 tmp = fromBCD(val & 0x7F);
216 if (tmp >= 0 && tmp <= 59) {
217 get_alarm(NVRAM, &tm);
219 NVRAM->buffer[0x1FF3] = val;
220 set_alarm(NVRAM, &tm);
225 tmp = fromBCD(val & 0x3F);
226 if (tmp >= 0 && tmp <= 23) {
227 get_alarm(NVRAM, &tm);
229 NVRAM->buffer[0x1FF4] = val;
230 set_alarm(NVRAM, &tm);
235 tmp = fromBCD(val & 0x1F);
237 get_alarm(NVRAM, &tm);
239 NVRAM->buffer[0x1FF5] = val;
240 set_alarm(NVRAM, &tm);
245 NVRAM->buffer[0x1FF6] = val;
249 NVRAM->buffer[0x1FF7] = val;
250 set_up_watchdog(NVRAM, val);
254 NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90;
258 tmp = fromBCD(val & 0x7F);
259 if (tmp >= 0 && tmp <= 59) {
260 get_time(NVRAM, &tm);
262 set_time(NVRAM, &tm);
264 if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) {
266 NVRAM->stop_time = time(NULL);
268 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
269 NVRAM->stop_time = 0;
272 NVRAM->buffer[0x1FF9] = val & 0x80;
276 tmp = fromBCD(val & 0x7F);
277 if (tmp >= 0 && tmp <= 59) {
278 get_time(NVRAM, &tm);
280 set_time(NVRAM, &tm);
285 tmp = fromBCD(val & 0x3F);
286 if (tmp >= 0 && tmp <= 23) {
287 get_time(NVRAM, &tm);
289 set_time(NVRAM, &tm);
293 /* day of the week / century */
294 tmp = fromBCD(val & 0x07);
295 get_time(NVRAM, &tm);
297 set_time(NVRAM, &tm);
298 NVRAM->buffer[0x1FFC] = val & 0x40;
302 tmp = fromBCD(val & 0x1F);
304 get_time(NVRAM, &tm);
306 set_time(NVRAM, &tm);
311 tmp = fromBCD(val & 0x1F);
312 if (tmp >= 1 && tmp <= 12) {
313 get_time(NVRAM, &tm);
315 set_time(NVRAM, &tm);
321 if (tmp >= 0 && tmp <= 99) {
322 get_time(NVRAM, &tm);
323 tm.tm_year = fromBCD(val);
324 set_time(NVRAM, &tm);
328 if (NVRAM->addr < 0x1FF0 ||
329 (NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
330 NVRAM->buffer[NVRAM->addr] = val & 0xFF;
336 uint32_t m48t59_read (void *opaque)
338 m48t59_t *NVRAM = opaque;
340 uint32_t retval = 0xFF;
342 switch (NVRAM->addr) {
366 /* A read resets the watchdog */
367 set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
374 get_time(NVRAM, &tm);
375 retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec);
379 get_time(NVRAM, &tm);
380 retval = toBCD(tm.tm_min);
384 get_time(NVRAM, &tm);
385 retval = toBCD(tm.tm_hour);
388 /* day of the week / century */
389 get_time(NVRAM, &tm);
390 retval = NVRAM->buffer[0x1FFC] | tm.tm_wday;
394 get_time(NVRAM, &tm);
395 retval = toBCD(tm.tm_mday);
399 get_time(NVRAM, &tm);
400 retval = toBCD(tm.tm_mon + 1);
404 get_time(NVRAM, &tm);
405 retval = toBCD(tm.tm_year);
408 if (NVRAM->addr < 0x1FF0 ||
409 (NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
411 retval = NVRAM->buffer[NVRAM->addr];
415 if (NVRAM->addr > 0x1FF9 && NVRAM->addr < 0x2000)
416 NVRAM_PRINTF("0x%08x <= 0x%08x\n", NVRAM->addr, retval);
421 void m48t59_set_addr (void *opaque, uint32_t addr)
423 m48t59_t *NVRAM = opaque;
428 /* IO access to NVRAM */
429 static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
431 m48t59_t *NVRAM = opaque;
433 addr -= NVRAM->io_base;
436 NVRAM->addr &= ~0x00FF;
440 NVRAM->addr &= ~0xFF00;
441 NVRAM->addr |= val << 8;
444 m48t59_write(NVRAM, val);
445 NVRAM->addr = 0x0000;
452 static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
454 m48t59_t *NVRAM = opaque;
456 if (addr == NVRAM->io_base + 3)
457 return m48t59_read(NVRAM);
462 /* Initialisation routine */
463 void *m48t59_init (int IRQ, uint32_t io_base, uint16_t size)
467 tmp = realloc(NVRAMs, (nb_NVRAMs + 1) * sizeof(m48t59_t));
471 tmp[nb_NVRAMs].buffer = malloc(size);
472 if (tmp[nb_NVRAMs].buffer == NULL)
474 memset(tmp[nb_NVRAMs].buffer, 0, size);
475 tmp[nb_NVRAMs].IRQ = IRQ;
476 tmp[nb_NVRAMs].size = size;
477 tmp[nb_NVRAMs].io_base = io_base;
478 tmp[nb_NVRAMs].addr = 0;
479 register_ioport_read(io_base, 0x04, 1, NVRAM_readb, &NVRAMs[nb_NVRAMs]);
480 register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, &NVRAMs[nb_NVRAMs]);
481 tmp[nb_NVRAMs].alrm_timer = qemu_new_timer(vm_clock, &alarm_cb,
483 tmp[nb_NVRAMs].wd_timer = qemu_new_timer(vm_clock, &watchdog_cb,
485 return &NVRAMs[nb_NVRAMs++];