2 * QEMU MC146818 RTC emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu-timer.h"
29 #include "hpet_emul.h"
34 #define RTC_SECONDS_ALARM 1
36 #define RTC_MINUTES_ALARM 3
38 #define RTC_HOURS_ALARM 5
39 #define RTC_ALARM_DONT_CARE 0xC0
41 #define RTC_DAY_OF_WEEK 6
42 #define RTC_DAY_OF_MONTH 7
51 #define REG_A_UIP 0x80
53 #define REG_B_SET 0x80
54 #define REG_B_PIE 0x40
55 #define REG_B_AIE 0x20
56 #define REG_B_UIE 0x10
57 #define REG_B_SQWE 0x08
61 #define REG_C_IRQF 0x80
66 uint8_t cmos_data[128];
74 QEMUTimer *periodic_timer;
75 int64_t next_periodic_time;
77 int64_t next_second_time;
79 uint32_t irq_coalesced;
81 QEMUTimer *coalesced_timer;
83 QEMUTimer *second_timer;
84 QEMUTimer *second_timer2;
87 static void rtc_irq_raise(qemu_irq irq) {
88 /* When HPET is operating in legacy mode, RTC interrupts are disabled
89 * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
90 * mode is established while interrupt is raised. We want it to
91 * be lowered in any case
93 #if defined TARGET_I386 || defined TARGET_X86_64
94 if (!hpet_in_legacy_mode())
99 static void rtc_set_time(RTCState *s);
100 static void rtc_copy_date(RTCState *s);
103 static void rtc_coalesced_timer_update(RTCState *s)
105 if (s->irq_coalesced == 0) {
106 qemu_del_timer(s->coalesced_timer);
108 /* divide each RTC interval to 2 - 8 smaller intervals */
109 int c = MIN(s->irq_coalesced, 7) + 1;
110 int64_t next_clock = qemu_get_clock(vm_clock) +
111 muldiv64(s->period / c, ticks_per_sec, 32768);
112 qemu_mod_timer(s->coalesced_timer, next_clock);
116 static void rtc_coalesced_timer(void *opaque)
118 RTCState *s = opaque;
120 if (s->irq_coalesced != 0) {
121 apic_reset_irq_delivered();
122 s->cmos_data[RTC_REG_C] |= 0xc0;
123 rtc_irq_raise(s->irq);
124 if (apic_get_irq_delivered()) {
129 rtc_coalesced_timer_update(s);
133 static void rtc_timer_update(RTCState *s, int64_t current_time)
135 int period_code, period;
136 int64_t cur_clock, next_irq_clock;
139 period_code = s->cmos_data[RTC_REG_A] & 0x0f;
140 #if defined TARGET_I386 || defined TARGET_X86_64
141 /* disable periodic timer if hpet is in legacy mode, since interrupts are
144 enable_pie = !hpet_in_legacy_mode();
149 && (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie)
150 || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
151 if (period_code <= 2)
153 /* period in 32 Khz cycles */
154 period = 1 << (period_code - 1);
156 if(period != s->period)
157 s->irq_coalesced = (s->irq_coalesced * s->period) / period;
160 /* compute 32 khz clock */
161 cur_clock = muldiv64(current_time, 32768, ticks_per_sec);
162 next_irq_clock = (cur_clock & ~(period - 1)) + period;
163 s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1;
164 qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
167 s->irq_coalesced = 0;
169 qemu_del_timer(s->periodic_timer);
173 static void rtc_periodic_timer(void *opaque)
175 RTCState *s = opaque;
177 rtc_timer_update(s, s->next_periodic_time);
178 if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
179 s->cmos_data[RTC_REG_C] |= 0xc0;
182 apic_reset_irq_delivered();
183 rtc_irq_raise(s->irq);
184 if (!apic_get_irq_delivered()) {
186 rtc_coalesced_timer_update(s);
190 rtc_irq_raise(s->irq);
192 if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
193 /* Not square wave at all but we don't want 2048Hz interrupts!
194 Must be seen as a pulse. */
195 qemu_irq_raise(s->sqw_irq);
199 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
201 RTCState *s = opaque;
203 if ((addr & 1) == 0) {
204 s->cmos_index = data & 0x7f;
207 printf("cmos: write index=0x%02x val=0x%02x\n",
208 s->cmos_index, data);
210 switch(s->cmos_index) {
211 case RTC_SECONDS_ALARM:
212 case RTC_MINUTES_ALARM:
213 case RTC_HOURS_ALARM:
214 /* XXX: not supported */
215 s->cmos_data[s->cmos_index] = data;
220 case RTC_DAY_OF_WEEK:
221 case RTC_DAY_OF_MONTH:
224 s->cmos_data[s->cmos_index] = data;
225 /* if in set mode, do not update the time */
226 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
231 /* UIP bit is read only */
232 s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
233 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
234 rtc_timer_update(s, qemu_get_clock(vm_clock));
237 if (data & REG_B_SET) {
238 /* set mode: reset UIP mode */
239 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
242 /* if disabling set mode, update the time */
243 if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
247 s->cmos_data[RTC_REG_B] = data;
248 rtc_timer_update(s, qemu_get_clock(vm_clock));
252 /* cannot write to them */
255 s->cmos_data[s->cmos_index] = data;
261 static inline int to_bcd(RTCState *s, int a)
263 if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
266 return ((a / 10) << 4) | (a % 10);
270 static inline int from_bcd(RTCState *s, int a)
272 if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
275 return ((a >> 4) * 10) + (a & 0x0f);
279 static void rtc_set_time(RTCState *s)
281 struct tm *tm = &s->current_tm;
283 tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
284 tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
285 tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
286 if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
287 (s->cmos_data[RTC_HOURS] & 0x80)) {
290 tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
291 tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
292 tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
293 tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
296 static void rtc_copy_date(RTCState *s)
298 const struct tm *tm = &s->current_tm;
301 s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
302 s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
303 if (s->cmos_data[RTC_REG_B] & 0x02) {
305 s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
308 s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
309 if (tm->tm_hour >= 12)
310 s->cmos_data[RTC_HOURS] |= 0x80;
312 s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday + 1);
313 s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
314 s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
315 year = (tm->tm_year - s->base_year) % 100;
318 s->cmos_data[RTC_YEAR] = to_bcd(s, year);
321 /* month is between 0 and 11. */
322 static int get_days_in_month(int month, int year)
324 static const int days_tab[12] = {
325 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
328 if ((unsigned )month >= 12)
332 if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
338 /* update 'tm' to the next second */
339 static void rtc_next_second(struct tm *tm)
344 if ((unsigned)tm->tm_sec >= 60) {
347 if ((unsigned)tm->tm_min >= 60) {
350 if ((unsigned)tm->tm_hour >= 24) {
354 if ((unsigned)tm->tm_wday >= 7)
356 days_in_month = get_days_in_month(tm->tm_mon,
359 if (tm->tm_mday < 1) {
361 } else if (tm->tm_mday > days_in_month) {
364 if (tm->tm_mon >= 12) {
375 static void rtc_update_second(void *opaque)
377 RTCState *s = opaque;
380 /* if the oscillator is not in normal operation, we do not update */
381 if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
382 s->next_second_time += ticks_per_sec;
383 qemu_mod_timer(s->second_timer, s->next_second_time);
385 rtc_next_second(&s->current_tm);
387 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
388 /* update in progress bit */
389 s->cmos_data[RTC_REG_A] |= REG_A_UIP;
391 /* should be 244 us = 8 / 32768 seconds, but currently the
392 timers do not have the necessary resolution. */
393 delay = (ticks_per_sec * 1) / 100;
396 qemu_mod_timer(s->second_timer2,
397 s->next_second_time + delay);
401 static void rtc_update_second2(void *opaque)
403 RTCState *s = opaque;
405 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
410 if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
411 if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
412 s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
413 ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
414 s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
415 ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
416 s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
418 s->cmos_data[RTC_REG_C] |= 0xa0;
419 rtc_irq_raise(s->irq);
423 /* update ended interrupt */
424 if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
425 s->cmos_data[RTC_REG_C] |= 0x90;
426 rtc_irq_raise(s->irq);
429 /* clear update in progress bit */
430 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
432 s->next_second_time += ticks_per_sec;
433 qemu_mod_timer(s->second_timer, s->next_second_time);
436 static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
438 RTCState *s = opaque;
440 if ((addr & 1) == 0) {
443 switch(s->cmos_index) {
447 case RTC_DAY_OF_WEEK:
448 case RTC_DAY_OF_MONTH:
451 ret = s->cmos_data[s->cmos_index];
454 ret = s->cmos_data[s->cmos_index];
457 ret = s->cmos_data[s->cmos_index];
458 qemu_irq_lower(s->irq);
459 s->cmos_data[RTC_REG_C] = 0x00;
462 ret = s->cmos_data[s->cmos_index];
466 printf("cmos: read index=0x%02x val=0x%02x\n",
473 void rtc_set_memory(RTCState *s, int addr, int val)
475 if (addr >= 0 && addr <= 127)
476 s->cmos_data[addr] = val;
479 void rtc_set_date(RTCState *s, const struct tm *tm)
485 /* PC cmos mappings */
486 #define REG_IBM_CENTURY_BYTE 0x32
487 #define REG_IBM_PS2_CENTURY_BYTE 0x37
489 static void rtc_set_date_from_host(RTCState *s)
494 /* set the CMOS date */
495 qemu_get_timedate(&tm, 0);
496 rtc_set_date(s, &tm);
498 val = to_bcd(s, (tm.tm_year / 100) + 19);
499 rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val);
500 rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val);
503 static void rtc_save(QEMUFile *f, void *opaque)
505 RTCState *s = opaque;
507 qemu_put_buffer(f, s->cmos_data, 128);
508 qemu_put_8s(f, &s->cmos_index);
510 qemu_put_be32(f, s->current_tm.tm_sec);
511 qemu_put_be32(f, s->current_tm.tm_min);
512 qemu_put_be32(f, s->current_tm.tm_hour);
513 qemu_put_be32(f, s->current_tm.tm_wday);
514 qemu_put_be32(f, s->current_tm.tm_mday);
515 qemu_put_be32(f, s->current_tm.tm_mon);
516 qemu_put_be32(f, s->current_tm.tm_year);
518 qemu_put_timer(f, s->periodic_timer);
519 qemu_put_be64(f, s->next_periodic_time);
521 qemu_put_be64(f, s->next_second_time);
522 qemu_put_timer(f, s->second_timer);
523 qemu_put_timer(f, s->second_timer2);
526 static int rtc_load(QEMUFile *f, void *opaque, int version_id)
528 RTCState *s = opaque;
533 qemu_get_buffer(f, s->cmos_data, 128);
534 qemu_get_8s(f, &s->cmos_index);
536 s->current_tm.tm_sec=qemu_get_be32(f);
537 s->current_tm.tm_min=qemu_get_be32(f);
538 s->current_tm.tm_hour=qemu_get_be32(f);
539 s->current_tm.tm_wday=qemu_get_be32(f);
540 s->current_tm.tm_mday=qemu_get_be32(f);
541 s->current_tm.tm_mon=qemu_get_be32(f);
542 s->current_tm.tm_year=qemu_get_be32(f);
544 qemu_get_timer(f, s->periodic_timer);
545 s->next_periodic_time=qemu_get_be64(f);
547 s->next_second_time=qemu_get_be64(f);
548 qemu_get_timer(f, s->second_timer);
549 qemu_get_timer(f, s->second_timer2);
554 static void rtc_save_td(QEMUFile *f, void *opaque)
556 RTCState *s = opaque;
558 qemu_put_be32(f, s->irq_coalesced);
559 qemu_put_be32(f, s->period);
562 static int rtc_load_td(QEMUFile *f, void *opaque, int version_id)
564 RTCState *s = opaque;
569 s->irq_coalesced = qemu_get_be32(f);
570 s->period = qemu_get_be32(f);
571 rtc_coalesced_timer_update(s);
576 static void rtc_reset(void *opaque)
578 RTCState *s = opaque;
580 s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
581 s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
583 qemu_irq_lower(s->irq);
587 s->irq_coalesced = 0;
591 RTCState *rtc_init_sqw(int base, qemu_irq irq, qemu_irq sqw_irq, int base_year)
595 s = qemu_mallocz(sizeof(RTCState));
598 s->sqw_irq = sqw_irq;
599 s->cmos_data[RTC_REG_A] = 0x26;
600 s->cmos_data[RTC_REG_B] = 0x02;
601 s->cmos_data[RTC_REG_C] = 0x00;
602 s->cmos_data[RTC_REG_D] = 0x80;
604 s->base_year = base_year;
605 rtc_set_date_from_host(s);
607 s->periodic_timer = qemu_new_timer(vm_clock,
608 rtc_periodic_timer, s);
611 s->coalesced_timer = qemu_new_timer(vm_clock, rtc_coalesced_timer, s);
613 s->second_timer = qemu_new_timer(vm_clock,
614 rtc_update_second, s);
615 s->second_timer2 = qemu_new_timer(vm_clock,
616 rtc_update_second2, s);
618 s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
619 qemu_mod_timer(s->second_timer2, s->next_second_time);
621 register_ioport_write(base, 2, 1, cmos_ioport_write, s);
622 register_ioport_read(base, 2, 1, cmos_ioport_read, s);
624 register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
627 register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s);
629 qemu_register_reset(rtc_reset, s);
634 RTCState *rtc_init(int base, qemu_irq irq, int base_year)
636 return rtc_init_sqw(base, irq, NULL, base_year);
639 /* Memory mapped interface */
640 static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
642 RTCState *s = opaque;
644 return cmos_ioport_read(s, addr >> s->it_shift) & 0xFF;
647 static void cmos_mm_writeb (void *opaque,
648 target_phys_addr_t addr, uint32_t value)
650 RTCState *s = opaque;
652 cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
655 static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
657 RTCState *s = opaque;
660 val = cmos_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
661 #ifdef TARGET_WORDS_BIGENDIAN
667 static void cmos_mm_writew (void *opaque,
668 target_phys_addr_t addr, uint32_t value)
670 RTCState *s = opaque;
671 #ifdef TARGET_WORDS_BIGENDIAN
672 value = bswap16(value);
674 cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
677 static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
679 RTCState *s = opaque;
682 val = cmos_ioport_read(s, addr >> s->it_shift);
683 #ifdef TARGET_WORDS_BIGENDIAN
689 static void cmos_mm_writel (void *opaque,
690 target_phys_addr_t addr, uint32_t value)
692 RTCState *s = opaque;
693 #ifdef TARGET_WORDS_BIGENDIAN
694 value = bswap32(value);
696 cmos_ioport_write(s, addr >> s->it_shift, value);
699 static CPUReadMemoryFunc *rtc_mm_read[] = {
705 static CPUWriteMemoryFunc *rtc_mm_write[] = {
711 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
717 s = qemu_mallocz(sizeof(RTCState));
720 s->cmos_data[RTC_REG_A] = 0x26;
721 s->cmos_data[RTC_REG_B] = 0x02;
722 s->cmos_data[RTC_REG_C] = 0x00;
723 s->cmos_data[RTC_REG_D] = 0x80;
725 s->base_year = base_year;
726 rtc_set_date_from_host(s);
728 s->periodic_timer = qemu_new_timer(vm_clock,
729 rtc_periodic_timer, s);
730 s->second_timer = qemu_new_timer(vm_clock,
731 rtc_update_second, s);
732 s->second_timer2 = qemu_new_timer(vm_clock,
733 rtc_update_second2, s);
735 s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
736 qemu_mod_timer(s->second_timer2, s->next_second_time);
738 io_memory = cpu_register_io_memory(rtc_mm_read, rtc_mm_write, s);
739 cpu_register_physical_memory(base, 2 << it_shift, io_memory);
741 register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
744 register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s);
746 qemu_register_reset(rtc_reset, s);