4 /* Raise IRQ to CPU if necessary. It must be called every time the active
6 void cpu_mips_update_irq(CPUState *env)
8 if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
9 (env->CP0_Status & (1 << CP0St_IE)) &&
10 !(env->hflags & MIPS_HFLAG_EXL) &&
11 !(env->hflags & MIPS_HFLAG_ERL) &&
12 !(env->hflags & MIPS_HFLAG_DM)) {
13 if (! (env->interrupt_request & CPU_INTERRUPT_HARD)) {
14 cpu_interrupt(env, CPU_INTERRUPT_HARD);
17 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
21 void cpu_mips_irq_request(void *opaque, int irq, int level)
23 CPUState *env = (CPUState *)opaque;
25 if (irq < 0 || irq > 7)
29 env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
31 env->CP0_Cause &= ~(1 << (irq +CP0Ca_IP));
33 cpu_mips_update_irq(env);