2 * QEMU MIPS Jazz support
4 * Copyright (c) 2007-2008 Hervé Poussineau
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "audio/audio.h"
36 #ifdef TARGET_WORDS_BIGENDIAN
37 #define BIOS_FILENAME "mips_bios.bin"
39 #define BIOS_FILENAME "mipsel_bios.bin"
48 static void main_cpu_reset(void *opaque)
50 CPUState *env = opaque;
54 static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
56 CPUState *env = opaque;
57 return cpu_inw(env, 0x71);
60 static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
62 CPUState *env = opaque;
63 cpu_outw(env, 0x71, val & 0xff);
66 static CPUReadMemoryFunc *rtc_read[3] = {
72 static CPUWriteMemoryFunc *rtc_write[3] = {
78 static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
80 /* Nothing to do. That is only to ensure that
81 * the current DMA acknowledge cycle is completed. */
84 static CPUReadMemoryFunc *dma_dummy_read[3] = {
90 static CPUWriteMemoryFunc *dma_dummy_write[3] = {
97 static void audio_init(qemu_irq *pic)
100 int audio_enabled = 0;
102 for (c = soundhw; !audio_enabled && c->name; ++c) {
103 audio_enabled = c->enabled;
111 for (c = soundhw; c->name; ++c) {
114 c->init.init_isa(s, pic);
123 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
124 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
127 void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
128 DisplayState *ds, const char *cpu_model,
129 enum jazz_model_e jazz_model)
132 unsigned long bios_offset;
135 qemu_irq *rc4030, *i8259;
137 rc4030_dma_function dma_read, dma_write;
140 int s_rtc, s_dma_dummy;
142 BlockDriverState *fds[MAX_FD];
146 if (cpu_model == NULL) {
150 /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
154 env = cpu_init(cpu_model);
156 fprintf(stderr, "Unable to find CPU definition\n");
159 qemu_register_reset(main_cpu_reset, env);
162 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
164 /* load the BIOS image. */
165 bios_offset = ram_size + vga_ram_size;
166 if (bios_name == NULL)
167 bios_name = BIOS_FILENAME;
168 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
169 bios_size = load_image(buf, phys_ram_base + bios_offset);
170 if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
171 fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
176 cpu_register_physical_memory(0x1fc00000LL,
177 MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
178 cpu_register_physical_memory(0xfff00000LL,
179 MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
181 /* Init CPU internal devices */
182 cpu_mips_irq_init_cpu(env);
183 cpu_mips_clock_init(env);
186 rc4030 = rc4030_init(env->irq[6], env->irq[3],
187 &dmas, &dma_read, &dma_write);
188 s_dma_dummy = cpu_register_io_memory(0, dma_dummy_read, dma_dummy_write, NULL);
189 cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
192 i8259 = i8259_init(env->irq[4]);
194 pit = pit_init(0x40, i8259[0]);
197 /* ISA IO space at 0x90000000 */
198 isa_mmio_init(0x90000000, 0x01000000);
199 isa_mem_base = 0x11000000;
202 switch (jazz_model) {
204 g364fb_mm_init(ds, vga_ram_size, 0, 0x40000000, 0x60000000);
207 isa_vga_mm_init(ds, phys_ram_base + ram_size, ram_size, vga_ram_size,
208 0x40000000, 0x60000000, 0);
214 /* Network controller */
215 /* FIXME: missing NS SONIC DP83932 */
218 scsi_hba = esp_init(0x80002000, 0,
219 dma_read, dma_write, dmas[0],
220 rc4030[5], &esp_reset);
221 for (n = 0; n < ESP_MAX_DEVS; n++) {
222 hd = drive_get_index(IF_SCSI, 0, n);
224 esp_scsi_attach(scsi_hba, drives_table[hd].bdrv, n);
229 if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
230 fprintf(stderr, "qemu: too many floppy drives\n");
233 for (n = 0; n < MAX_FD; n++) {
234 int fd = drive_get_index(IF_FLOPPY, 0, n);
236 fds[n] = drives_table[fd].bdrv;
240 fdctrl_init(rc4030[1], 0, 1, 0x80003000, fds);
242 /* Real time clock */
243 rtc_init(0x70, i8259[8]);
244 s_rtc = cpu_register_io_memory(0, rtc_read, rtc_write, env);
245 cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
247 /* Keyboard (i8042) */
248 i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
252 serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1);
254 serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1);
258 parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);
261 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
266 /* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
267 ds1225y_init(0x80009000, "nvram");
270 jazz_led_init(ds, 0x8000f000);
274 void mips_magnum_init (ram_addr_t ram_size, int vga_ram_size,
275 const char *boot_device, DisplayState *ds,
276 const char *kernel_filename, const char *kernel_cmdline,
277 const char *initrd_filename, const char *cpu_model)
279 mips_jazz_init(ram_size, vga_ram_size, ds, cpu_model, JAZZ_MAGNUM);
283 void mips_pica61_init (ram_addr_t ram_size, int vga_ram_size,
284 const char *boot_device, DisplayState *ds,
285 const char *kernel_filename, const char *kernel_cmdline,
286 const char *initrd_filename, const char *cpu_model)
288 mips_jazz_init(ram_size, vga_ram_size, ds, cpu_model, JAZZ_PICA61);
291 QEMUMachine mips_magnum_machine = {
293 .desc = "MIPS Magnum",
294 .init = mips_magnum_init,
295 .ram_require = MAGNUM_BIOS_SIZE + VGA_RAM_SIZE,
300 QEMUMachine mips_pica61_machine = {
302 .desc = "Acer Pica 61",
303 .init = mips_pica61_init,
304 .ram_require = MAGNUM_BIOS_SIZE + VGA_RAM_SIZE,