2 * QEMU Malta board support
4 * Copyright (c) 2006 Aurelien Jarno
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #ifdef TARGET_WORDS_BIGENDIAN
28 #define BIOS_FILENAME "mips_bios.bin"
30 #define BIOS_FILENAME "mipsel_bios.bin"
34 #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL)
36 #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU)
39 #define ENVP_ADDR (int32_t)0x80002000
40 #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
42 #define ENVP_NB_ENTRIES 16
43 #define ENVP_ENTRY_SIZE 256
55 CharDriverState *display;
63 static void malta_fpga_update_display(void *opaque)
67 MaltaFPGAState *s = opaque;
69 for (i = 7 ; i >= 0 ; i--) {
70 if (s->leds & (1 << i))
77 qemu_chr_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text);
78 qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
82 * EEPROM 24C01 / 24C02 emulation.
84 * Emulation for serial EEPROMs:
85 * 24C01 - 1024 bit (128 x 8)
86 * 24C02 - 2048 bit (256 x 8)
88 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
94 # define logout(fmt, args...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ##args)
96 # define logout(fmt, args...) ((void)0)
99 struct _eeprom24c0x_t {
108 uint8_t contents[256];
111 typedef struct _eeprom24c0x_t eeprom24c0x_t;
113 static eeprom24c0x_t eeprom = {
115 /* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00,
116 /* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
117 /* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x0E,0x00,
118 /* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0x40,
119 /* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
120 /* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
121 /* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
122 /* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
123 /* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
124 /* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
125 /* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
126 /* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
127 /* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
128 /* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
129 /* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
130 /* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
134 static uint8_t eeprom24c0x_read()
136 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
137 eeprom.tick, eeprom.scl, eeprom.sda, eeprom.data);
141 static void eeprom24c0x_write(int scl, int sda)
143 if (eeprom.scl && scl && (eeprom.sda != sda)) {
144 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
145 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda, sda ? "stop" : "start");
150 } else if (eeprom.tick == 0 && !eeprom.ack) {
151 /* Waiting for start. */
152 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
153 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
154 } else if (!eeprom.scl && scl) {
155 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
156 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
158 logout("\ti2c ack bit = 0\n");
161 } else if (eeprom.sda == sda) {
162 uint8_t bit = (sda != 0);
163 logout("\ti2c bit = %d\n", bit);
164 if (eeprom.tick < 9) {
165 eeprom.command <<= 1;
166 eeprom.command += bit;
168 if (eeprom.tick == 9) {
169 logout("\tcommand 0x%04x, %s\n", eeprom.command, bit ? "read" : "write");
172 } else if (eeprom.tick < 17) {
173 if (eeprom.command & 1) {
174 sda = ((eeprom.data & 0x80) != 0);
176 eeprom.address <<= 1;
177 eeprom.address += bit;
180 if (eeprom.tick == 17) {
181 eeprom.data = eeprom.contents[eeprom.address];
182 logout("\taddress 0x%04x, data 0x%02x\n", eeprom.address, eeprom.data);
186 } else if (eeprom.tick >= 17) {
190 logout("\tsda changed with raising scl\n");
193 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
199 static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
201 MaltaFPGAState *s = opaque;
205 saddr = (addr & 0xfffff);
209 /* SWITCH Register */
211 val = 0x00000000; /* All switches closed */
214 /* STATUS Register */
216 #ifdef TARGET_WORDS_BIGENDIAN
228 /* LEDBAR Register */
233 /* BRKRES Register */
238 /* UART Registers are handled directly by the serial device */
245 /* XXX: implement a real I2C controller */
249 /* IN = OUT until a real I2C control is implemented */
256 /* I2CINP Register */
258 val = ((s->i2cin & ~1) | eeprom24c0x_read());
266 /* I2COUT Register */
271 /* I2CSEL Register */
278 printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
286 static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
289 MaltaFPGAState *s = opaque;
292 saddr = (addr & 0xfffff);
296 /* SWITCH Register */
304 /* LEDBAR Register */
305 /* XXX: implement a 8-LED array */
307 s->leds = val & 0xff;
310 /* ASCIIWORD Register */
312 snprintf(s->display_text, 9, "%08X", val);
313 malta_fpga_update_display(s);
316 /* ASCIIPOS0 to ASCIIPOS7 Registers */
325 s->display_text[(saddr - 0x00418) >> 3] = (char) val;
326 malta_fpga_update_display(s);
329 /* SOFTRES Register */
332 qemu_system_reset_request ();
335 /* BRKRES Register */
340 /* UART Registers are handled directly by the serial device */
344 s->gpout = val & 0xff;
349 s->i2coe = val & 0x03;
352 /* I2COUT Register */
354 eeprom24c0x_write(val & 0x02, val & 0x01);
358 /* I2CSEL Register */
360 s->i2csel = val & 0x01;
365 printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
372 static CPUReadMemoryFunc *malta_fpga_read[] = {
378 static CPUWriteMemoryFunc *malta_fpga_write[] = {
384 void malta_fpga_reset(void *opaque)
386 MaltaFPGAState *s = opaque;
396 s->display_text[8] = '\0';
397 snprintf(s->display_text, 9, " ");
398 malta_fpga_update_display(s);
401 MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
404 CharDriverState *uart_chr;
407 s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState));
409 malta = cpu_register_io_memory(0, malta_fpga_read,
410 malta_fpga_write, s);
412 cpu_register_physical_memory(base, 0x900, malta);
413 cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta);
415 s->display = qemu_chr_open("vc");
416 qemu_chr_printf(s->display, "\e[HMalta LEDBAR\r\n");
417 qemu_chr_printf(s->display, "+--------+\r\n");
418 qemu_chr_printf(s->display, "+ +\r\n");
419 qemu_chr_printf(s->display, "+--------+\r\n");
420 qemu_chr_printf(s->display, "\n");
421 qemu_chr_printf(s->display, "Malta ASCII\r\n");
422 qemu_chr_printf(s->display, "+--------+\r\n");
423 qemu_chr_printf(s->display, "+ +\r\n");
424 qemu_chr_printf(s->display, "+--------+\r\n");
426 uart_chr = qemu_chr_open("vc");
427 qemu_chr_printf(uart_chr, "CBUS UART\r\n");
428 s->uart = serial_mm_init(base + 0x900, 3, env->irq[2], uart_chr, 1);
431 qemu_register_reset(malta_fpga_reset, s);
438 static void audio_init (PCIBus *pci_bus)
441 int audio_enabled = 0;
443 for (c = soundhw; !audio_enabled && c->name; ++c) {
444 audio_enabled = c->enabled;
452 for (c = soundhw; c->name; ++c) {
454 c->init.init_pci (pci_bus, s);
461 /* Network support */
462 static void network_init (PCIBus *pci_bus)
467 for(i = 0; i < nb_nics; i++) {
472 if (i == 0 && strcmp(nd->model, "pcnet") == 0) {
473 /* The malta board has a PCNet card using PCI SLOT 11 */
474 pci_nic_init(pci_bus, nd, 88);
476 pci_nic_init(pci_bus, nd, -1);
481 /* ROM and pseudo bootloader
483 The following code implements a very very simple bootloader. It first
484 loads the registers a0 to a3 to the values expected by the OS, and
485 then jump at the kernel address.
487 The bootloader should pass the locations of the kernel arguments and
488 environment variables tables. Those tables contain the 32-bit address
489 of NULL terminated strings. The environment variables table should be
490 terminated by a NULL address.
492 For a simpler implementation, the number of kernel arguments is fixed
493 to two (the name of the kernel and the command line), and the two
494 tables are actually the same one.
496 The registers a0 to a3 should contain the following values:
497 a0 - number of kernel arguments
498 a1 - 32-bit address of the kernel arguments table
499 a2 - 32-bit address of the environment variables table
500 a3 - RAM size in bytes
503 static void write_bootloader (CPUState *env, unsigned long bios_offset, int64_t kernel_entry)
507 /* Small bootloader */
508 p = (uint32_t *) (phys_ram_base + bios_offset);
509 stl_raw(p++, 0x0bf00160); /* j 0x1fc00580 */
510 stl_raw(p++, 0x00000000); /* nop */
512 /* YAMON service vector */
513 stl_raw(phys_ram_base + bios_offset + 0x500, 0xbfc00580); /* start: */
514 stl_raw(phys_ram_base + bios_offset + 0x504, 0xbfc0083c); /* print_count: */
515 stl_raw(phys_ram_base + bios_offset + 0x520, 0xbfc00580); /* start: */
516 stl_raw(phys_ram_base + bios_offset + 0x52c, 0xbfc00800); /* flush_cache: */
517 stl_raw(phys_ram_base + bios_offset + 0x534, 0xbfc00808); /* print: */
518 stl_raw(phys_ram_base + bios_offset + 0x538, 0xbfc00800); /* reg_cpu_isr: */
519 stl_raw(phys_ram_base + bios_offset + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
520 stl_raw(phys_ram_base + bios_offset + 0x540, 0xbfc00800); /* reg_ic_isr: */
521 stl_raw(phys_ram_base + bios_offset + 0x544, 0xbfc00800); /* unred_ic_isr: */
522 stl_raw(phys_ram_base + bios_offset + 0x548, 0xbfc00800); /* reg_esr: */
523 stl_raw(phys_ram_base + bios_offset + 0x54c, 0xbfc00800); /* unreg_esr: */
524 stl_raw(phys_ram_base + bios_offset + 0x550, 0xbfc00800); /* getchar: */
525 stl_raw(phys_ram_base + bios_offset + 0x554, 0xbfc00800); /* syscon_read: */
528 /* Second part of the bootloader */
529 p = (uint32_t *) (phys_ram_base + bios_offset + 0x580);
530 stl_raw(p++, 0x24040002); /* addiu a0, zero, 2 */
531 stl_raw(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
532 stl_raw(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
533 stl_raw(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
534 stl_raw(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */
535 stl_raw(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
536 stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
537 stl_raw(p++, 0x3c070000 | (env->ram_size >> 16)); /* lui a3, high(env->ram_size) */
538 stl_raw(p++, 0x34e70000 | (env->ram_size & 0xffff)); /* ori a3, a3, low(env->ram_size) */
540 /* Load BAR registers as done by YAMON */
541 stl_raw(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
543 #ifdef TARGET_WORDS_BIGENDIAN
544 stl_raw(p++, 0x3c08c000); /* lui t0, 0xc000 */
546 stl_raw(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */
548 stl_raw(p++, 0xad280048); /* sw t0, 0x0048(t1) */
549 #ifdef TARGET_WORDS_BIGENDIAN
550 stl_raw(p++, 0x3c084000); /* lui t0, 0x4000 */
552 stl_raw(p++, 0x34080040); /* ori t0, r0, 0x0040 */
554 stl_raw(p++, 0xad280050); /* sw t0, 0x0050(t1) */
556 #ifdef TARGET_WORDS_BIGENDIAN
557 stl_raw(p++, 0x3c088000); /* lui t0, 0x8000 */
559 stl_raw(p++, 0x34080080); /* ori t0, r0, 0x0080 */
561 stl_raw(p++, 0xad280058); /* sw t0, 0x0058(t1) */
562 #ifdef TARGET_WORDS_BIGENDIAN
563 stl_raw(p++, 0x3c083f00); /* lui t0, 0x3f00 */
565 stl_raw(p++, 0x3408003f); /* ori t0, r0, 0x003f */
567 stl_raw(p++, 0xad280060); /* sw t0, 0x0060(t1) */
569 #ifdef TARGET_WORDS_BIGENDIAN
570 stl_raw(p++, 0x3c08c100); /* lui t0, 0xc100 */
572 stl_raw(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */
574 stl_raw(p++, 0xad280080); /* sw t0, 0x0080(t1) */
575 #ifdef TARGET_WORDS_BIGENDIAN
576 stl_raw(p++, 0x3c085e00); /* lui t0, 0x5e00 */
578 stl_raw(p++, 0x3408005e); /* ori t0, r0, 0x005e */
580 stl_raw(p++, 0xad280088); /* sw t0, 0x0088(t1) */
582 /* Jump to kernel code */
583 stl_raw(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
584 stl_raw(p++, 0x37ff0000 | (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
585 stl_raw(p++, 0x03e00008); /* jr ra */
586 stl_raw(p++, 0x00000000); /* nop */
588 /* YAMON subroutines */
589 p = (uint32_t *) (phys_ram_base + bios_offset + 0x800);
590 stl_raw(p++, 0x03e00008); /* jr ra */
591 stl_raw(p++, 0x24020000); /* li v0,0 */
592 /* 808 YAMON print */
593 stl_raw(p++, 0x03e06821); /* move t5,ra */
594 stl_raw(p++, 0x00805821); /* move t3,a0 */
595 stl_raw(p++, 0x00a05021); /* move t2,a1 */
596 stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
597 stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
598 stl_raw(p++, 0x10800005); /* beqz a0,834 */
599 stl_raw(p++, 0x00000000); /* nop */
600 stl_raw(p++, 0x0ff0021c); /* jal 870 */
601 stl_raw(p++, 0x00000000); /* nop */
602 stl_raw(p++, 0x08000205); /* j 814 */
603 stl_raw(p++, 0x00000000); /* nop */
604 stl_raw(p++, 0x01a00008); /* jr t5 */
605 stl_raw(p++, 0x01602021); /* move a0,t3 */
606 /* 0x83c YAMON print_count */
607 stl_raw(p++, 0x03e06821); /* move t5,ra */
608 stl_raw(p++, 0x00805821); /* move t3,a0 */
609 stl_raw(p++, 0x00a05021); /* move t2,a1 */
610 stl_raw(p++, 0x00c06021); /* move t4,a2 */
611 stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
612 stl_raw(p++, 0x0ff0021c); /* jal 870 */
613 stl_raw(p++, 0x00000000); /* nop */
614 stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
615 stl_raw(p++, 0x258cffff); /* addiu t4,t4,-1 */
616 stl_raw(p++, 0x1580fffa); /* bnez t4,84c */
617 stl_raw(p++, 0x00000000); /* nop */
618 stl_raw(p++, 0x01a00008); /* jr t5 */
619 stl_raw(p++, 0x01602021); /* move a0,t3 */
621 stl_raw(p++, 0x3c08b800); /* lui t0,0xb400 */
622 stl_raw(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
623 stl_raw(p++, 0x91090005); /* lbu t1,5(t0) */
624 stl_raw(p++, 0x00000000); /* nop */
625 stl_raw(p++, 0x31290040); /* andi t1,t1,0x40 */
626 stl_raw(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
627 stl_raw(p++, 0x00000000); /* nop */
628 stl_raw(p++, 0x03e00008); /* jr ra */
629 stl_raw(p++, 0xa1040000); /* sb a0,0(t0) */
633 static void prom_set(int index, const char *string, ...)
640 if (index >= ENVP_NB_ENTRIES)
643 p = (int32_t *) (phys_ram_base + ENVP_ADDR + VIRT_TO_PHYS_ADDEND);
646 if (string == NULL) {
651 table_addr = ENVP_ADDR + sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
652 s = (char *) (phys_ram_base + VIRT_TO_PHYS_ADDEND + table_addr);
654 stl_raw(p, table_addr);
656 va_start(ap, string);
657 vsnprintf (s, ENVP_ENTRY_SIZE, string, ap);
662 static int64_t load_kernel (CPUState *env)
664 int64_t kernel_entry, kernel_low, kernel_high;
667 ram_addr_t initrd_offset;
669 if (load_elf(env->kernel_filename, VIRT_TO_PHYS_ADDEND,
670 &kernel_entry, &kernel_low, &kernel_high) < 0) {
671 fprintf(stderr, "qemu: could not load kernel '%s'\n",
672 env->kernel_filename);
679 if (env->initrd_filename) {
680 initrd_size = get_image_size (env->initrd_filename);
681 if (initrd_size > 0) {
682 initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
683 if (initrd_offset + initrd_size > env->ram_size) {
685 "qemu: memory too small for initial ram disk '%s'\n",
686 env->initrd_filename);
689 initrd_size = load_image(env->initrd_filename,
690 phys_ram_base + initrd_offset);
692 if (initrd_size == (target_ulong) -1) {
693 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
694 env->initrd_filename);
699 /* Store command line. */
700 prom_set(index++, env->kernel_filename);
702 prom_set(index++, "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s",
703 PHYS_TO_VIRT(initrd_offset), initrd_size,
704 env->kernel_cmdline);
706 prom_set(index++, env->kernel_cmdline);
708 /* Setup minimum environment variables */
709 prom_set(index++, "memsize");
710 prom_set(index++, "%i", env->ram_size);
711 prom_set(index++, "modetty0");
712 prom_set(index++, "38400n8r");
713 prom_set(index++, NULL);
718 static void main_cpu_reset(void *opaque)
720 CPUState *env = opaque;
722 cpu_mips_register(env, NULL);
724 /* The bootload does not need to be rewritten as it is located in a
725 read only location. The kernel location and the arguments table
726 location does not change. */
727 if (env->kernel_filename) {
728 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
734 void mips_malta_init (int ram_size, int vga_ram_size, int boot_device,
735 DisplayState *ds, const char **fd_filename, int snapshot,
736 const char *kernel_filename, const char *kernel_cmdline,
737 const char *initrd_filename, const char *cpu_model)
740 unsigned long bios_offset;
741 int64_t kernel_entry;
745 /* fdctrl_t *floppy_controller; */
746 MaltaFPGAState *malta_fpga;
756 if (cpu_model == NULL) {
763 if (mips_find_by_name(cpu_model, &def) != 0)
766 cpu_mips_register(env, def);
767 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
768 qemu_register_reset(main_cpu_reset, env);
771 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
773 /* Map the bios at two physical locations, as on the real board */
774 bios_offset = ram_size + vga_ram_size;
775 cpu_register_physical_memory(0x1e000000LL,
776 BIOS_SIZE, bios_offset | IO_MEM_ROM);
777 cpu_register_physical_memory(0x1fc00000LL,
778 BIOS_SIZE, bios_offset | IO_MEM_ROM);
781 malta_fpga = malta_fpga_init(0x1f000000LL, env);
783 /* Load a BIOS image unless a kernel image has been specified. */
784 if (!kernel_filename) {
785 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
786 ret = load_image(buf, phys_ram_base + bios_offset);
787 if (ret < 0 || ret > BIOS_SIZE) {
789 "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
793 /* In little endian mode the 32bit words in the bios are swapped,
794 a neat trick which allows bi-endian firmware. */
795 #ifndef TARGET_WORDS_BIGENDIAN
798 for (addr = (uint32_t *)(phys_ram_base + bios_offset);
799 addr < (uint32_t *)(phys_ram_base + bios_offset + ret);
801 *addr = bswap32(*addr);
807 /* If a kernel image has been specified, write a small bootloader
808 to the flash location. */
809 if (kernel_filename) {
810 env->ram_size = ram_size;
811 env->kernel_filename = kernel_filename;
812 env->kernel_cmdline = kernel_cmdline;
813 env->initrd_filename = initrd_filename;
814 kernel_entry = load_kernel(env);
815 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
816 write_bootloader(env, bios_offset, kernel_entry);
819 /* Board ID = 0x420 (Malta Board with CoreLV)
820 XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
821 map to the board ID. */
822 stl_raw(phys_ram_base + bios_offset + 0x10, 0x00000420);
824 /* Init internal devices */
825 cpu_mips_irq_init_cpu(env);
826 cpu_mips_clock_init(env);
827 cpu_mips_irqctrl_init();
829 /* Interrupt controller */
830 /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
831 i8259 = i8259_init(env->irq[2]);
834 pci_bus = pci_gt64120_init(i8259);
837 piix4_devfn = piix4_init(pci_bus, 80);
838 pci_piix4_ide_init(pci_bus, bs_table, piix4_devfn + 1, i8259);
839 usb_uhci_piix4_init(pci_bus, piix4_devfn + 2);
840 smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100);
841 eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
842 for (i = 0; i < 8; i++) {
843 /* TODO: Populate SPD eeprom data. */
844 smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
846 pit = pit_init(0x40, i8259[0]);
850 i8042_init(i8259[1], i8259[12], 0x60);
851 rtc_state = rtc_init(0x70, i8259[8]);
853 serial_init(0x3f8, i8259[4], serial_hds[0]);
855 serial_init(0x2f8, i8259[3], serial_hds[1]);
857 parallel_init(0x378, i8259[7], parallel_hds[0]);
858 /* XXX: The floppy controller does not work correctly, something is
860 floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd_table); */
868 network_init(pci_bus);
870 /* Optional PCI video card */
871 pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size,
872 ram_size, vga_ram_size);
875 QEMUMachine mips_malta_machine = {
877 "MIPS Malta Core LV",