2 * QEMU Malta board support
4 * Copyright (c) 2006 Aurelien Jarno
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
35 #include "qemu-char.h"
37 #include "audio/audio.h"
41 //#define DEBUG_BOARD_INIT
43 #ifdef TARGET_WORDS_BIGENDIAN
44 #define BIOS_FILENAME "mips_bios.bin"
46 #define BIOS_FILENAME "mipsel_bios.bin"
50 #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL)
52 #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU)
55 #define ENVP_ADDR (int32_t)0x80002000
56 #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
58 #define ENVP_NB_ENTRIES 16
59 #define ENVP_ENTRY_SIZE 256
71 CharDriverState *display;
78 static struct _loaderparams {
80 const char *kernel_filename;
81 const char *kernel_cmdline;
82 const char *initrd_filename;
86 static void malta_fpga_update_display(void *opaque)
90 MaltaFPGAState *s = opaque;
92 for (i = 7 ; i >= 0 ; i--) {
93 if (s->leds & (1 << i))
100 qemu_chr_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text);
101 qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
105 * EEPROM 24C01 / 24C02 emulation.
107 * Emulation for serial EEPROMs:
108 * 24C01 - 1024 bit (128 x 8)
109 * 24C02 - 2048 bit (256 x 8)
111 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
117 # define logout(fmt, args...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ##args)
119 # define logout(fmt, args...) ((void)0)
122 struct _eeprom24c0x_t {
131 uint8_t contents[256];
134 typedef struct _eeprom24c0x_t eeprom24c0x_t;
136 static eeprom24c0x_t eeprom = {
138 /* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00,
139 /* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
140 /* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x0E,0x00,
141 /* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0x40,
142 /* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
143 /* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
144 /* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
145 /* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
146 /* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
147 /* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
148 /* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
149 /* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
150 /* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
151 /* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
152 /* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
153 /* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
157 static uint8_t eeprom24c0x_read(void)
159 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
160 eeprom.tick, eeprom.scl, eeprom.sda, eeprom.data);
164 static void eeprom24c0x_write(int scl, int sda)
166 if (eeprom.scl && scl && (eeprom.sda != sda)) {
167 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
168 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda, sda ? "stop" : "start");
173 } else if (eeprom.tick == 0 && !eeprom.ack) {
174 /* Waiting for start. */
175 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
176 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
177 } else if (!eeprom.scl && scl) {
178 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
179 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
181 logout("\ti2c ack bit = 0\n");
184 } else if (eeprom.sda == sda) {
185 uint8_t bit = (sda != 0);
186 logout("\ti2c bit = %d\n", bit);
187 if (eeprom.tick < 9) {
188 eeprom.command <<= 1;
189 eeprom.command += bit;
191 if (eeprom.tick == 9) {
192 logout("\tcommand 0x%04x, %s\n", eeprom.command, bit ? "read" : "write");
195 } else if (eeprom.tick < 17) {
196 if (eeprom.command & 1) {
197 sda = ((eeprom.data & 0x80) != 0);
199 eeprom.address <<= 1;
200 eeprom.address += bit;
203 if (eeprom.tick == 17) {
204 eeprom.data = eeprom.contents[eeprom.address];
205 logout("\taddress 0x%04x, data 0x%02x\n", eeprom.address, eeprom.data);
209 } else if (eeprom.tick >= 17) {
213 logout("\tsda changed with raising scl\n");
216 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
222 static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
224 MaltaFPGAState *s = opaque;
228 saddr = (addr & 0xfffff);
232 /* SWITCH Register */
234 val = 0x00000000; /* All switches closed */
237 /* STATUS Register */
239 #ifdef TARGET_WORDS_BIGENDIAN
251 /* LEDBAR Register */
256 /* BRKRES Register */
261 /* UART Registers are handled directly by the serial device */
268 /* XXX: implement a real I2C controller */
272 /* IN = OUT until a real I2C control is implemented */
279 /* I2CINP Register */
281 val = ((s->i2cin & ~1) | eeprom24c0x_read());
289 /* I2COUT Register */
294 /* I2CSEL Register */
301 printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
309 static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
312 MaltaFPGAState *s = opaque;
315 saddr = (addr & 0xfffff);
319 /* SWITCH Register */
327 /* LEDBAR Register */
328 /* XXX: implement a 8-LED array */
330 s->leds = val & 0xff;
333 /* ASCIIWORD Register */
335 snprintf(s->display_text, 9, "%08X", val);
336 malta_fpga_update_display(s);
339 /* ASCIIPOS0 to ASCIIPOS7 Registers */
348 s->display_text[(saddr - 0x00418) >> 3] = (char) val;
349 malta_fpga_update_display(s);
352 /* SOFTRES Register */
355 qemu_system_reset_request ();
358 /* BRKRES Register */
363 /* UART Registers are handled directly by the serial device */
367 s->gpout = val & 0xff;
372 s->i2coe = val & 0x03;
375 /* I2COUT Register */
377 eeprom24c0x_write(val & 0x02, val & 0x01);
381 /* I2CSEL Register */
383 s->i2csel = val & 0x01;
388 printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
395 static CPUReadMemoryFunc *malta_fpga_read[] = {
401 static CPUWriteMemoryFunc *malta_fpga_write[] = {
407 static void malta_fpga_reset(void *opaque)
409 MaltaFPGAState *s = opaque;
419 s->display_text[8] = '\0';
420 snprintf(s->display_text, 9, " ");
423 static void malta_fpga_led_init(CharDriverState *chr)
425 qemu_chr_printf(chr, "\e[HMalta LEDBAR\r\n");
426 qemu_chr_printf(chr, "+--------+\r\n");
427 qemu_chr_printf(chr, "+ +\r\n");
428 qemu_chr_printf(chr, "+--------+\r\n");
429 qemu_chr_printf(chr, "\n");
430 qemu_chr_printf(chr, "Malta ASCII\r\n");
431 qemu_chr_printf(chr, "+--------+\r\n");
432 qemu_chr_printf(chr, "+ +\r\n");
433 qemu_chr_printf(chr, "+--------+\r\n");
436 static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr)
441 s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState));
443 malta = cpu_register_io_memory(0, malta_fpga_read,
444 malta_fpga_write, s);
446 cpu_register_physical_memory(base, 0x900, malta);
447 /* 0xa00 is less than a page, so will still get the right offsets. */
448 cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta);
450 s->display = qemu_chr_open("fpga", "vc:320x200", malta_fpga_led_init);
452 s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1);
455 qemu_register_reset(malta_fpga_reset, s);
462 static void audio_init (PCIBus *pci_bus)
465 int audio_enabled = 0;
467 for (c = soundhw; !audio_enabled && c->name; ++c) {
468 audio_enabled = c->enabled;
475 for (c = soundhw; c->name; ++c) {
477 c->init.init_pci (pci_bus, s);
484 /* Network support */
485 static void network_init (PCIBus *pci_bus)
489 for(i = 0; i < nb_nics; i++) {
490 NICInfo *nd = &nd_table[i];
493 if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0))
494 /* The malta board has a PCNet card using PCI SLOT 11 */
497 pci_nic_init(pci_bus, nd, devfn, "pcnet");
501 /* ROM and pseudo bootloader
503 The following code implements a very very simple bootloader. It first
504 loads the registers a0 to a3 to the values expected by the OS, and
505 then jump at the kernel address.
507 The bootloader should pass the locations of the kernel arguments and
508 environment variables tables. Those tables contain the 32-bit address
509 of NULL terminated strings. The environment variables table should be
510 terminated by a NULL address.
512 For a simpler implementation, the number of kernel arguments is fixed
513 to two (the name of the kernel and the command line), and the two
514 tables are actually the same one.
516 The registers a0 to a3 should contain the following values:
517 a0 - number of kernel arguments
518 a1 - 32-bit address of the kernel arguments table
519 a2 - 32-bit address of the environment variables table
520 a3 - RAM size in bytes
523 static void write_bootloader (CPUState *env, uint8_t *base,
524 int64_t kernel_entry)
528 /* Small bootloader */
529 p = (uint32_t *)base;
530 stl_raw(p++, 0x0bf00160); /* j 0x1fc00580 */
531 stl_raw(p++, 0x00000000); /* nop */
533 /* YAMON service vector */
534 stl_raw(base + 0x500, 0xbfc00580); /* start: */
535 stl_raw(base + 0x504, 0xbfc0083c); /* print_count: */
536 stl_raw(base + 0x520, 0xbfc00580); /* start: */
537 stl_raw(base + 0x52c, 0xbfc00800); /* flush_cache: */
538 stl_raw(base + 0x534, 0xbfc00808); /* print: */
539 stl_raw(base + 0x538, 0xbfc00800); /* reg_cpu_isr: */
540 stl_raw(base + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
541 stl_raw(base + 0x540, 0xbfc00800); /* reg_ic_isr: */
542 stl_raw(base + 0x544, 0xbfc00800); /* unred_ic_isr: */
543 stl_raw(base + 0x548, 0xbfc00800); /* reg_esr: */
544 stl_raw(base + 0x54c, 0xbfc00800); /* unreg_esr: */
545 stl_raw(base + 0x550, 0xbfc00800); /* getchar: */
546 stl_raw(base + 0x554, 0xbfc00800); /* syscon_read: */
549 /* Second part of the bootloader */
550 p = (uint32_t *) (base + 0x580);
551 stl_raw(p++, 0x24040002); /* addiu a0, zero, 2 */
552 stl_raw(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
553 stl_raw(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
554 stl_raw(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
555 stl_raw(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */
556 stl_raw(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
557 stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
558 stl_raw(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); /* lui a3, high(ram_size) */
559 stl_raw(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(ram_size) */
561 /* Load BAR registers as done by YAMON */
562 stl_raw(p++, 0x3c09b400); /* lui t1, 0xb400 */
564 #ifdef TARGET_WORDS_BIGENDIAN
565 stl_raw(p++, 0x3c08df00); /* lui t0, 0xdf00 */
567 stl_raw(p++, 0x340800df); /* ori t0, r0, 0x00df */
569 stl_raw(p++, 0xad280068); /* sw t0, 0x0068(t1) */
571 stl_raw(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
573 #ifdef TARGET_WORDS_BIGENDIAN
574 stl_raw(p++, 0x3c08c000); /* lui t0, 0xc000 */
576 stl_raw(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */
578 stl_raw(p++, 0xad280048); /* sw t0, 0x0048(t1) */
579 #ifdef TARGET_WORDS_BIGENDIAN
580 stl_raw(p++, 0x3c084000); /* lui t0, 0x4000 */
582 stl_raw(p++, 0x34080040); /* ori t0, r0, 0x0040 */
584 stl_raw(p++, 0xad280050); /* sw t0, 0x0050(t1) */
586 #ifdef TARGET_WORDS_BIGENDIAN
587 stl_raw(p++, 0x3c088000); /* lui t0, 0x8000 */
589 stl_raw(p++, 0x34080080); /* ori t0, r0, 0x0080 */
591 stl_raw(p++, 0xad280058); /* sw t0, 0x0058(t1) */
592 #ifdef TARGET_WORDS_BIGENDIAN
593 stl_raw(p++, 0x3c083f00); /* lui t0, 0x3f00 */
595 stl_raw(p++, 0x3408003f); /* ori t0, r0, 0x003f */
597 stl_raw(p++, 0xad280060); /* sw t0, 0x0060(t1) */
599 #ifdef TARGET_WORDS_BIGENDIAN
600 stl_raw(p++, 0x3c08c100); /* lui t0, 0xc100 */
602 stl_raw(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */
604 stl_raw(p++, 0xad280080); /* sw t0, 0x0080(t1) */
605 #ifdef TARGET_WORDS_BIGENDIAN
606 stl_raw(p++, 0x3c085e00); /* lui t0, 0x5e00 */
608 stl_raw(p++, 0x3408005e); /* ori t0, r0, 0x005e */
610 stl_raw(p++, 0xad280088); /* sw t0, 0x0088(t1) */
612 /* Jump to kernel code */
613 stl_raw(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
614 stl_raw(p++, 0x37ff0000 | (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
615 stl_raw(p++, 0x03e00008); /* jr ra */
616 stl_raw(p++, 0x00000000); /* nop */
618 /* YAMON subroutines */
619 p = (uint32_t *) (base + 0x800);
620 stl_raw(p++, 0x03e00008); /* jr ra */
621 stl_raw(p++, 0x24020000); /* li v0,0 */
622 /* 808 YAMON print */
623 stl_raw(p++, 0x03e06821); /* move t5,ra */
624 stl_raw(p++, 0x00805821); /* move t3,a0 */
625 stl_raw(p++, 0x00a05021); /* move t2,a1 */
626 stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
627 stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
628 stl_raw(p++, 0x10800005); /* beqz a0,834 */
629 stl_raw(p++, 0x00000000); /* nop */
630 stl_raw(p++, 0x0ff0021c); /* jal 870 */
631 stl_raw(p++, 0x00000000); /* nop */
632 stl_raw(p++, 0x08000205); /* j 814 */
633 stl_raw(p++, 0x00000000); /* nop */
634 stl_raw(p++, 0x01a00008); /* jr t5 */
635 stl_raw(p++, 0x01602021); /* move a0,t3 */
636 /* 0x83c YAMON print_count */
637 stl_raw(p++, 0x03e06821); /* move t5,ra */
638 stl_raw(p++, 0x00805821); /* move t3,a0 */
639 stl_raw(p++, 0x00a05021); /* move t2,a1 */
640 stl_raw(p++, 0x00c06021); /* move t4,a2 */
641 stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
642 stl_raw(p++, 0x0ff0021c); /* jal 870 */
643 stl_raw(p++, 0x00000000); /* nop */
644 stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
645 stl_raw(p++, 0x258cffff); /* addiu t4,t4,-1 */
646 stl_raw(p++, 0x1580fffa); /* bnez t4,84c */
647 stl_raw(p++, 0x00000000); /* nop */
648 stl_raw(p++, 0x01a00008); /* jr t5 */
649 stl_raw(p++, 0x01602021); /* move a0,t3 */
651 stl_raw(p++, 0x3c08b800); /* lui t0,0xb400 */
652 stl_raw(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
653 stl_raw(p++, 0x91090005); /* lbu t1,5(t0) */
654 stl_raw(p++, 0x00000000); /* nop */
655 stl_raw(p++, 0x31290040); /* andi t1,t1,0x40 */
656 stl_raw(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
657 stl_raw(p++, 0x00000000); /* nop */
658 stl_raw(p++, 0x03e00008); /* jr ra */
659 stl_raw(p++, 0xa1040000); /* sb a0,0(t0) */
663 static void prom_set(int index, const char *string, ...)
665 char buf[ENVP_ENTRY_SIZE];
666 target_phys_addr_t p;
670 if (index >= ENVP_NB_ENTRIES)
673 p = ENVP_ADDR + VIRT_TO_PHYS_ADDEND + index * 4;
675 if (string == NULL) {
680 table_addr = ENVP_ADDR + sizeof(int32_t) * ENVP_NB_ENTRIES
681 + index * ENVP_ENTRY_SIZE;
682 stl_phys(p, table_addr);
684 va_start(ap, string);
685 vsnprintf(buf, ENVP_ENTRY_SIZE, string, ap);
687 pstrcpy_targphys(table_addr + VIRT_TO_PHYS_ADDEND, ENVP_ENTRY_SIZE, buf);
691 static int64_t load_kernel (CPUState *env)
693 int64_t kernel_entry, kernel_low, kernel_high;
696 ram_addr_t initrd_offset;
698 if (load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND,
699 (uint64_t *)&kernel_entry, (uint64_t *)&kernel_low,
700 (uint64_t *)&kernel_high) < 0) {
701 fprintf(stderr, "qemu: could not load kernel '%s'\n",
702 loaderparams.kernel_filename);
709 if (loaderparams.initrd_filename) {
710 initrd_size = get_image_size (loaderparams.initrd_filename);
711 if (initrd_size > 0) {
712 initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
713 if (initrd_offset + initrd_size > ram_size) {
715 "qemu: memory too small for initial ram disk '%s'\n",
716 loaderparams.initrd_filename);
719 initrd_size = load_image_targphys(loaderparams.initrd_filename,
721 ram_size - initrd_offset);
723 if (initrd_size == (target_ulong) -1) {
724 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
725 loaderparams.initrd_filename);
730 /* Store command line. */
731 prom_set(index++, loaderparams.kernel_filename);
733 prom_set(index++, "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s",
734 PHYS_TO_VIRT(initrd_offset), initrd_size,
735 loaderparams.kernel_cmdline);
737 prom_set(index++, loaderparams.kernel_cmdline);
739 /* Setup minimum environment variables */
740 prom_set(index++, "memsize");
741 prom_set(index++, "%i", loaderparams.ram_size);
742 prom_set(index++, "modetty0");
743 prom_set(index++, "38400n8r");
744 prom_set(index++, NULL);
749 static void main_cpu_reset(void *opaque)
751 CPUState *env = opaque;
754 /* The bootload does not need to be rewritten as it is located in a
755 read only location. The kernel location and the arguments table
756 location does not change. */
757 if (loaderparams.kernel_filename) {
758 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
764 void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
765 const char *boot_device,
766 const char *kernel_filename, const char *kernel_cmdline,
767 const char *initrd_filename, const char *cpu_model)
770 ram_addr_t ram_offset;
771 ram_addr_t bios_offset;
772 target_long bios_size;
773 int64_t kernel_entry;
777 fdctrl_t *floppy_controller;
778 MaltaFPGAState *malta_fpga;
785 BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
786 BlockDriverState *fd[MAX_FD];
791 if (cpu_model == NULL) {
798 env = cpu_init(cpu_model);
800 fprintf(stderr, "Unable to find CPU definition\n");
803 qemu_register_reset(main_cpu_reset, env);
806 if (ram_size > (256 << 20)) {
808 "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n",
809 ((unsigned int)ram_size / (1 << 20)));
812 ram_offset = qemu_ram_alloc(ram_size);
813 bios_offset = qemu_ram_alloc(BIOS_SIZE);
816 cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
818 /* Map the bios at two physical locations, as on the real board. */
819 cpu_register_physical_memory(0x1e000000LL,
820 BIOS_SIZE, bios_offset | IO_MEM_ROM);
821 cpu_register_physical_memory(0x1fc00000LL,
822 BIOS_SIZE, bios_offset | IO_MEM_ROM);
825 malta_fpga = malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]);
827 /* Load firmware in flash / BIOS unless we boot directly into a kernel. */
828 if (kernel_filename) {
829 /* Write a small bootloader to the flash location. */
830 loaderparams.ram_size = ram_size;
831 loaderparams.kernel_filename = kernel_filename;
832 loaderparams.kernel_cmdline = kernel_cmdline;
833 loaderparams.initrd_filename = initrd_filename;
834 kernel_entry = load_kernel(env);
835 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
836 write_bootloader(env, qemu_get_ram_ptr(bios_offset), kernel_entry);
838 index = drive_get_index(IF_PFLASH, 0, fl_idx);
840 /* Load firmware from flash. */
841 bios_size = 0x400000;
842 fl_sectors = bios_size >> 16;
843 #ifdef DEBUG_BOARD_INIT
844 printf("Register parallel flash %d size " TARGET_FMT_lx " at "
845 "offset %08lx addr %08llx '%s' %x\n",
846 fl_idx, bios_size, bios_offset, 0x1e000000LL,
847 bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
849 pflash_cfi01_register(0x1e000000LL, bios_offset,
850 drives_table[index].bdrv, 65536, fl_sectors,
851 4, 0x0000, 0x0000, 0x0000, 0x0000);
854 /* Load a BIOS image. */
855 if (bios_name == NULL)
856 bios_name = BIOS_FILENAME;
857 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
858 bios_size = load_image_targphys(buf, 0x1fc00000LL, BIOS_SIZE);
859 if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) {
861 "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
866 /* In little endian mode the 32bit words in the bios are swapped,
867 a neat trick which allows bi-endian firmware. */
868 #ifndef TARGET_WORDS_BIGENDIAN
870 uint32_t *addr = qemu_get_ram_ptr(bios_offset);;
871 uint32_t *end = addr + bios_size;
879 /* Board ID = 0x420 (Malta Board with CoreLV)
880 XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
881 map to the board ID. */
882 stl_phys(0x1fc00010LL, 0x00000420);
884 /* Init internal devices */
885 cpu_mips_irq_init_cpu(env);
886 cpu_mips_clock_init(env);
888 /* Interrupt controller */
889 /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
890 i8259 = i8259_init(env->irq[2]);
893 pci_bus = pci_gt64120_init(i8259);
897 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
898 fprintf(stderr, "qemu: too many IDE bus\n");
902 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
903 index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
905 hd[i] = drives_table[index].bdrv;
910 piix4_devfn = piix4_init(pci_bus, 80);
911 pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1, i8259);
912 usb_uhci_piix4_init(pci_bus, piix4_devfn + 2);
913 smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, i8259[9]);
914 eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
915 for (i = 0; i < 8; i++) {
916 /* TODO: Populate SPD eeprom data. */
917 smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
919 pit = pit_init(0x40, i8259[0]);
923 i8042_init(i8259[1], i8259[12], 0x60);
924 rtc_state = rtc_init(0x70, i8259[8], 2000);
925 serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
926 serial_init(0x2f8, i8259[3], 115200, serial_hds[1]);
928 parallel_init(0x378, i8259[7], parallel_hds[0]);
929 for(i = 0; i < MAX_FD; i++) {
930 index = drive_get_index(IF_FLOPPY, 0, i);
932 fd[i] = drives_table[index].bdrv;
936 floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
944 network_init(pci_bus);
946 /* Optional PCI video card */
947 if (cirrus_vga_enabled) {
948 pci_cirrus_vga_init(pci_bus, vga_ram_size);
949 } else if (vmsvga_enabled) {
950 pci_vmsvga_init(pci_bus, vga_ram_size);
951 } else if (std_vga_enabled) {
952 pci_vga_init(pci_bus, vga_ram_size, 0, 0);
956 QEMUMachine mips_malta_machine = {
958 .desc = "MIPS Malta Core LV",
959 .init = mips_malta_init,