2 * Nokia N-series internet tablets.
4 * Copyright (C) 2007 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "qemu-common.h"
35 /* Nokia N8x0 support */
37 struct omap_mpu_state_s *cpu;
39 struct rfbi_chip_s blizzard;
42 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
43 struct uwire_slave_s *chip;
57 #define N8X0_TUSB_ENABLE_GPIO 0
58 #define N800_MMC2_WP_GPIO 8
59 #define N800_UNKNOWN_GPIO0 9 /* out */
60 #define N810_MMC2_VIOSD_GPIO 9
61 #define N810_HEADSET_AMP_GPIO 10
62 #define N800_CAM_TURN_GPIO 12
63 #define N810_GPS_RESET_GPIO 12
64 #define N800_BLIZZARD_POWERDOWN_GPIO 15
65 #define N800_MMC1_WP_GPIO 23
66 #define N810_MMC2_VSD_GPIO 23
67 #define N8X0_ONENAND_GPIO 26
68 #define N810_BLIZZARD_RESET_GPIO 30
69 #define N800_UNKNOWN_GPIO2 53 /* out */
70 #define N8X0_TUSB_INT_GPIO 58
71 #define N8X0_BT_WKUP_GPIO 61
72 #define N8X0_STI_GPIO 62
73 #define N8X0_CBUS_SEL_GPIO 64
74 #define N8X0_CBUS_DAT_GPIO 65
75 #define N8X0_CBUS_CLK_GPIO 66
76 #define N8X0_WLAN_IRQ_GPIO 87
77 #define N8X0_BT_RESET_GPIO 92
78 #define N8X0_TEA5761_CS_GPIO 93
79 #define N800_UNKNOWN_GPIO 94
80 #define N810_TSC_RESET_GPIO 94
81 #define N800_CAM_ACT_GPIO 95
82 #define N810_GPS_WAKEUP_GPIO 95
83 #define N8X0_MMC_CS_GPIO 96
84 #define N8X0_WLAN_PWR_GPIO 97
85 #define N8X0_BT_HOST_WKUP_GPIO 98
86 #define N810_SPEAKER_AMP_GPIO 101
87 #define N810_KB_LOCK_GPIO 102
88 #define N800_TSC_TS_GPIO 103
89 #define N810_TSC_TS_GPIO 106
90 #define N8X0_HEADPHONE_GPIO 107
91 #define N8X0_RETU_GPIO 108
92 #define N800_TSC_KP_IRQ_GPIO 109
93 #define N810_KEYBOARD_GPIO 109
94 #define N800_BAT_COVER_GPIO 110
95 #define N810_SLIDE_GPIO 110
96 #define N8X0_TAHVO_GPIO 111
97 #define N800_UNKNOWN_GPIO4 112 /* out */
98 #define N810_SLEEPX_LED_GPIO 112
99 #define N800_TSC_RESET_GPIO 118 /* ? */
100 #define N810_AIC33_RESET_GPIO 118
101 #define N800_TSC_UNKNOWN_GPIO 119 /* out */
102 #define N8X0_TMP105_GPIO 125
106 #define XLDR_LL_UART 1
108 /* Addresses on the I2C bus 0 */
109 #define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
110 #define N8X0_TCM825x_ADDR 0x29 /* Camera */
111 #define N810_LP5521_ADDR 0x32 /* LEDs */
112 #define N810_TSL2563_ADDR 0x3d /* Light sensor */
113 #define N810_LM8323_ADDR 0x45 /* Keyboard */
114 /* Addresses on the I2C bus 1 */
115 #define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
116 #define N8X0_MENELAUS_ADDR 0x72 /* Power management */
118 /* Chipselects on GPMC NOR interface */
119 #define N8X0_ONENAND_CS 0
120 #define N8X0_USB_ASYNC_CS 1
121 #define N8X0_USB_SYNC_CS 4
123 #define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
125 static void n800_mmc_cs_cb(void *opaque, int line, int level)
127 /* TODO: this seems to actually be connected to the menelaus, to
128 * which also both MMC slots connect. */
129 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
131 printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1);
134 static void n8x0_gpio_setup(struct n800_s *s)
136 qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc, 1);
137 omap2_gpio_out_set(s->cpu->gpif, N8X0_MMC_CS_GPIO, mmc_cs[0]);
139 qemu_irq_lower(omap2_gpio_in_get(s->cpu->gpif, N800_BAT_COVER_GPIO)[0]);
142 #define MAEMO_CAL_HEADER(...) \
143 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
147 static const uint8_t n8x0_cal_wlan_mac[] = {
148 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
149 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
150 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
151 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
152 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
153 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
156 static const uint8_t n8x0_cal_bt_id[] = {
157 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
158 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
159 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
163 static void n8x0_nand_setup(struct n800_s *s)
167 /* Either ec40xx or ec48xx are OK for the ID */
168 omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update,
170 (s->nand = onenand_init(0xec4800, 1,
171 omap2_gpio_in_get(s->cpu->gpif,
172 N8X0_ONENAND_GPIO)[0])),
174 otp_region = onenand_raw_otp(s->nand);
176 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
177 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
178 /* XXX: in theory should also update the OOB for both pages */
181 static void n8x0_i2c_setup(struct n800_s *s)
183 qemu_irq tmp_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TMP105_GPIO)[0];
185 /* Attach the CPU on one end of our I2C bus. */
186 s->i2c = omap_i2c_bus(s->cpu->i2c[0]);
188 /* Attach a menelaus PM chip */
189 i2c_set_slave_address(
190 twl92230_init(s->i2c,
191 s->cpu->irq[0][OMAP_INT_24XX_SYS_NIRQ]),
194 /* Attach a TMP105 PM chip (A0 wired to ground) */
195 i2c_set_slave_address(tmp105_init(s->i2c, tmp_irq), N8X0_TMP105_ADDR);
198 /* Touchscreen and keypad controller */
199 static struct mouse_transform_info_s n800_pointercal = {
202 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
205 static struct mouse_transform_info_s n810_pointercal = {
208 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
211 #define RETU_KEYCODE 61 /* F3 */
213 static void n800_key_event(void *opaque, int keycode)
215 struct n800_s *s = (struct n800_s *) opaque;
216 int code = s->keymap[keycode & 0x7f];
219 if ((keycode & 0x7f) == RETU_KEYCODE)
220 retu_key_event(s->retu, !(keycode & 0x80));
224 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
227 static const int n800_keys[16] = {
241 64, /* FullScreen (F6) */
246 static void n800_tsc_kbd_setup(struct n800_s *s)
250 /* XXX: are the three pins inverted inside the chip between the
251 * tsc and the cpu (N4111)? */
252 qemu_irq penirq = 0; /* NC */
253 qemu_irq kbirq = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_KP_IRQ_GPIO)[0];
254 qemu_irq dav = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_TS_GPIO)[0];
256 s->ts.chip = tsc2301_init(penirq, kbirq, dav, 0);
257 s->ts.opaque = s->ts.chip->opaque;
258 s->ts.txrx = tsc210x_txrx;
260 for (i = 0; i < 0x80; i ++)
262 for (i = 0; i < 0x10; i ++)
263 if (n800_keys[i] >= 0)
264 s->keymap[n800_keys[i]] = i;
266 qemu_add_kbd_event_handler(n800_key_event, s);
268 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
271 static void n810_tsc_setup(struct n800_s *s)
273 qemu_irq pintdav = omap2_gpio_in_get(s->cpu->gpif, N810_TSC_TS_GPIO)[0];
275 s->ts.opaque = tsc2005_init(pintdav);
276 s->ts.txrx = tsc2005_txrx;
278 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
281 /* N810 Keyboard controller */
282 static void n810_key_event(void *opaque, int keycode)
284 struct n800_s *s = (struct n800_s *) opaque;
285 int code = s->keymap[keycode & 0x7f];
288 if ((keycode & 0x7f) == RETU_KEYCODE)
289 retu_key_event(s->retu, !(keycode & 0x80));
293 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
298 static int n810_keys[0x80] = {
303 [0x05] = 14, /* Backspace */
313 [0x12] = 62, /* Menu (F4) */
315 [0x14] = 40, /* ' (Apostrophe) */
322 [0x1c] = 42, /* Shift (Left shift) */
323 [0x1f] = 65, /* Zoom+ (F7) */
326 [0x22] = 39, /* ; (Semicolon) */
327 [0x23] = 12, /* - (Minus) */
328 [0x24] = 13, /* = (Equal) */
329 [0x2b] = 56, /* Fn (Left Alt) */
331 [0x2f] = 66, /* Zoom- (F8) */
334 [0x32] = 29 | M, /* Right Ctrl */
335 [0x34] = 57, /* Space */
336 [0x35] = 51, /* , (Comma) */
337 [0x37] = 72 | M, /* Up */
338 [0x3c] = 82 | M, /* Compose (Insert) */
339 [0x3f] = 64, /* FullScreen (F6) */
342 [0x44] = 52, /* . (Dot) */
343 [0x46] = 77 | M, /* Right */
344 [0x4f] = 63, /* Home (F5) */
346 [0x53] = 80 | M, /* Down */
347 [0x55] = 28, /* Enter */
348 [0x5f] = 1, /* Cycle (ESC) */
351 [0x64] = 75 | M, /* Left */
355 [0x75] = 28 | M, /* KP Enter (KP Enter) */
357 [0x75] = 15, /* KP Enter (Tab) */
363 static void n810_kbd_setup(struct n800_s *s)
365 qemu_irq kbd_irq = omap2_gpio_in_get(s->cpu->gpif, N810_KEYBOARD_GPIO)[0];
368 for (i = 0; i < 0x80; i ++)
370 for (i = 0; i < 0x80; i ++)
371 if (n810_keys[i] > 0)
372 s->keymap[n810_keys[i]] = i;
374 qemu_add_kbd_event_handler(n810_key_event, s);
376 /* Attach the LM8322 keyboard to the I2C bus,
377 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */
378 s->kbd = lm8323_init(s->i2c, kbd_irq);
379 i2c_set_slave_address(s->kbd, N810_LM8323_ADDR);
382 /* LCD MIPI DBI-C controller (URAL) */
403 static void mipid_reset(struct mipid_s *s)
406 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
414 (1 << 7) | /* Register loading OK. */
415 (1 << 5) | /* The chip is attached. */
416 (1 << 4); /* Display glass still in one piece. */
426 static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
428 struct mipid_s *s = (struct mipid_s *) opaque;
432 cpu_abort(cpu_single_env, "%s: FIXME: bad SPI word width %i\n",
435 if (s->p >= ARRAY_SIZE(s->resp))
438 ret = s->resp[s->p ++];
440 s->param[s->pm] = cmd;
448 case 0x01: /* SWRESET */
452 case 0x02: /* BSTROFF */
455 case 0x03: /* BSTRON */
459 case 0x04: /* RDDID */
461 s->resp[0] = (s->id >> 16) & 0xff;
462 s->resp[1] = (s->id >> 8) & 0xff;
463 s->resp[2] = (s->id >> 0) & 0xff;
466 case 0x06: /* RD_RED */
467 case 0x07: /* RD_GREEN */
468 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
469 * for the bootloader one needs to change this. */
470 case 0x08: /* RD_BLUE */
472 /* TODO: return first pixel components */
476 case 0x09: /* RDDST */
478 s->resp[0] = s->booster << 7;
479 s->resp[1] = (5 << 4) | (s->partial << 2) |
480 (s->sleep << 1) | s->normal;
481 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
482 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
483 s->resp[3] = s->gamma << 6;
486 case 0x0a: /* RDDPM */
488 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
489 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
491 case 0x0b: /* RDDMADCTR */
495 case 0x0c: /* RDDCOLMOD */
497 s->resp[0] = 5; /* 65K colours */
499 case 0x0d: /* RDDIM */
501 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
503 case 0x0e: /* RDDSM */
505 s->resp[0] = s->te << 7;
507 case 0x0f: /* RDDSDR */
509 s->resp[0] = s->selfcheck;
512 case 0x10: /* SLPIN */
515 case 0x11: /* SLPOUT */
517 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
520 case 0x12: /* PTLON */
525 case 0x13: /* NORON */
531 case 0x20: /* INVOFF */
534 case 0x21: /* INVON */
538 case 0x22: /* APOFF */
539 case 0x23: /* APON */
542 case 0x25: /* WRCNTR */
547 case 0x26: /* GAMSET */
549 s->gamma = ffs(s->param[0] & 0xf) - 1;
554 case 0x28: /* DISPOFF */
556 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
558 case 0x29: /* DISPON */
560 fprintf(stderr, "%s: Display on\n", __FUNCTION__);
563 case 0x2a: /* CASET */
564 case 0x2b: /* RASET */
565 case 0x2c: /* RAMWR */
566 case 0x2d: /* RGBSET */
567 case 0x2e: /* RAMRD */
568 case 0x30: /* PTLAR */
569 case 0x33: /* SCRLAR */
572 case 0x34: /* TEOFF */
575 case 0x35: /* TEON */
582 case 0x36: /* MADCTR */
585 case 0x37: /* VSCSAD */
591 case 0x38: /* IDMOFF */
592 case 0x39: /* IDMON */
593 case 0x3a: /* COLMOD */
596 case 0xb0: /* CLKINT / DISCTL */
597 case 0xb1: /* CLKEXT */
602 case 0xb4: /* FRMSEL */
605 case 0xb5: /* FRM8SEL */
606 case 0xb6: /* TMPRNG / INIESC */
607 case 0xb7: /* TMPHIS / NOP2 */
608 case 0xb8: /* TMPREAD / MADCTL */
609 case 0xba: /* DISTCTR */
610 case 0xbb: /* EPVOL */
613 case 0xbd: /* Unknown */
619 case 0xc2: /* IFMOD */
624 case 0xc6: /* PWRCTL */
625 case 0xc7: /* PPWRCTL */
626 case 0xd0: /* EPWROUT */
627 case 0xd1: /* EPWRIN */
628 case 0xd4: /* RDEV */
629 case 0xd5: /* RDRR */
632 case 0xda: /* RDID1 */
634 s->resp[0] = (s->id >> 16) & 0xff;
636 case 0xdb: /* RDID2 */
638 s->resp[0] = (s->id >> 8) & 0xff;
640 case 0xdc: /* RDID3 */
642 s->resp[0] = (s->id >> 0) & 0xff;
647 fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd);
654 static void *mipid_init(void)
656 struct mipid_s *s = (struct mipid_s *) qemu_mallocz(sizeof(*s));
664 static void n8x0_spi_setup(struct n800_s *s)
666 void *tsc = s->ts.opaque;
667 void *mipid = mipid_init();
669 omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0);
670 omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1);
673 /* This task is normally performed by the bootloader. If we're loading
674 * a kernel directly, we need to enable the Blizzard ourselves. */
675 static void n800_dss_init(struct rfbi_chip_s *chip)
679 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
680 chip->write(chip->opaque, 1, 0x64);
681 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
682 chip->write(chip->opaque, 1, 0x1e);
683 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
684 chip->write(chip->opaque, 1, 0xe0);
685 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
686 chip->write(chip->opaque, 1, 0x01);
687 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
688 chip->write(chip->opaque, 1, 0x06);
689 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
690 chip->write(chip->opaque, 1, 1); /* Enable bit */
692 chip->write(chip->opaque, 0, 0x6c);
693 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
694 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
695 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
696 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
697 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
698 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
699 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
700 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
701 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
702 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
703 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
704 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
705 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
706 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
707 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
708 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
709 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
710 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
712 fb_blank = memset(qemu_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
713 /* Display Memory Data Port */
714 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
718 static void n8x0_dss_setup(struct n800_s *s)
720 s->blizzard.opaque = s1d13745_init(0);
721 s->blizzard.block = s1d13745_write_block;
722 s->blizzard.write = s1d13745_write;
723 s->blizzard.read = s1d13745_read;
725 omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard);
728 static void n8x0_cbus_setup(struct n800_s *s)
730 qemu_irq dat_out = omap2_gpio_in_get(s->cpu->gpif, N8X0_CBUS_DAT_GPIO)[0];
731 qemu_irq retu_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_RETU_GPIO)[0];
732 qemu_irq tahvo_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TAHVO_GPIO)[0];
734 struct cbus_s *cbus = cbus_init(dat_out);
736 omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_CLK_GPIO, cbus->clk);
737 omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_DAT_GPIO, cbus->dat);
738 omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_SEL_GPIO, cbus->sel);
740 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
741 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
744 static void n8x0_uart_setup(struct n800_s *s)
746 CharDriverState *radio = uart_hci_init(
747 omap2_gpio_in_get(s->cpu->gpif,
748 N8X0_BT_HOST_WKUP_GPIO)[0]);
750 omap2_gpio_out_set(s->cpu->gpif, N8X0_BT_RESET_GPIO,
751 csrhci_pins_get(radio)[csrhci_pin_reset]);
752 omap2_gpio_out_set(s->cpu->gpif, N8X0_BT_WKUP_GPIO,
753 csrhci_pins_get(radio)[csrhci_pin_wakeup]);
755 omap_uart_attach(s->cpu->uart[BT_UART], radio);
758 static void n8x0_usb_power_cb(void *opaque, int line, int level)
760 struct n800_s *s = opaque;
762 tusb6010_power(s->usb, level);
765 static void n8x0_usb_setup(struct n800_s *s)
767 qemu_irq tusb_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TUSB_INT_GPIO)[0];
768 qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0];
769 struct tusb_s *tusb = tusb6010_init(tusb_irq);
771 /* Using the NOR interface */
772 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS,
773 tusb6010_async_io(tusb), 0, 0, tusb,
775 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS,
776 tusb6010_sync_io(tusb), 0, 0, tusb,
780 omap2_gpio_out_set(s->cpu->gpif, N8X0_TUSB_ENABLE_GPIO, tusb_pwr);
783 /* Setup done before the main bootloader starts by some early setup code
784 * - used when we want to run the main bootloader in emulation. This
785 * isn't documented. */
786 static uint32_t n800_pinout[104] = {
787 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
788 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
789 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
790 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
791 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
792 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
793 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
794 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
795 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
796 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
797 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
798 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
799 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
800 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
801 0x00000000, 0x00000038, 0x00340000, 0x00000000,
802 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
803 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
804 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
805 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
806 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
807 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
808 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
809 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
810 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
811 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
812 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
815 static void n800_setup_nolo_tags(void *sram_base)
818 uint32_t *p = sram_base + 0x8000;
819 uint32_t *v = sram_base + 0xa000;
821 memset(p, 0, 0x3000);
823 strcpy((void *) (p + 0), "QEMU N800");
825 strcpy((void *) (p + 8), "F5");
827 stl_raw(p + 10, 0x04f70000);
828 strcpy((void *) (p + 9), "RX-34");
830 /* RAM size in MB? */
831 stl_raw(p + 12, 0x80);
833 /* Pointer to the list of tags */
834 stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000);
836 /* The NOLO tags start here */
837 p = sram_base + 0x9000;
838 #define ADD_TAG(tag, len) \
839 stw_raw((uint16_t *) p + 0, tag); \
840 stw_raw((uint16_t *) p + 1, len); p ++; \
841 stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
843 /* OMAP STI console? Pin out settings? */
844 ADD_TAG(0x6e01, 414);
845 for (i = 0; i < ARRAY_SIZE(n800_pinout); i ++)
846 stl_raw(v ++, n800_pinout[i]);
848 /* Kernel memsize? */
852 /* NOLO serial console */
854 stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
857 /* CBUS settings (Retu/AVilma) */
859 stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
860 stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
861 stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
865 /* Nokia ASIC BB5 (Retu/Tahvo) */
867 stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
868 stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
873 stw_raw((uint16_t *) v + 0, 30); /* ??? */
874 stw_raw((uint16_t *) v + 1, 24); /* ??? */
880 stw_raw((uint16_t *) (v ++), 15); /* ??? */
883 /* I^2C (Menelaus) */
885 stl_raw(v ++, 0x00720000); /* ??? */
889 stw_raw((uint16_t *) v + 0, 94); /* ??? */
890 stw_raw((uint16_t *) v + 1, 23); /* ??? */
891 stw_raw((uint16_t *) v + 2, 0); /* ??? */
894 /* OMAP gpio switch info */
896 strcpy((void *) v, "bat_cover"); v += 3;
897 stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */
898 stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */
900 strcpy((void *) v, "cam_act"); v += 3;
901 stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */
902 stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */
904 strcpy((void *) v, "cam_turn"); v += 3;
905 stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */
906 stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */
908 strcpy((void *) v, "headphone"); v += 3;
909 stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */
910 stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */
915 stl_raw(v ++, 0x5c623d01); /* ??? */
916 stl_raw(v ++, 0x00000201); /* ??? */
917 stl_raw(v ++, 0x00000000); /* ??? */
919 /* CX3110x WLAN settings */
921 stl_raw(v ++, 0x00610025); /* ??? */
922 stl_raw(v ++, 0xffff0057); /* ??? */
924 /* MMC host settings */
926 stl_raw(v ++, 0xffff000f); /* ??? */
927 stl_raw(v ++, 0xffffffff); /* ??? */
928 stl_raw(v ++, 0x00000060); /* ??? */
930 /* OneNAND chip select */
932 stl_raw(v ++, 0x00000401); /* ??? */
933 stl_raw(v ++, 0x0002003a); /* ??? */
934 stl_raw(v ++, 0x00000002); /* ??? */
936 /* TEA5761 sensor settings */
938 stl_raw(v ++, 93); /* GPIO num ??? */
944 /* Kernel UART / console */
948 /* End of the list */
949 stl_raw(p ++, 0x00000000);
950 stl_raw(p ++, 0x00000000);
953 /* This task is normally performed by the bootloader. If we're loading
954 * a kernel directly, we need to set up GPMC mappings ourselves. */
955 static void n800_gpmc_init(struct n800_s *s)
958 (0xf << 8) | /* MASKADDRESS */
959 (1 << 6) | /* CSVALID */
960 (4 << 0); /* BASEADDRESS */
962 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
963 (void *) &config7, sizeof(config7));
966 /* Setup sequence done by the bootloader */
967 static void n8x0_boot_init(void *opaque)
969 struct n800_s *s = (struct n800_s *) opaque;
973 #define omap_writel(addr, val) \
975 cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf))
977 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
978 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
979 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
980 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
981 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
982 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
983 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
984 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
985 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
986 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
987 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
988 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
989 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
990 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
991 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
992 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
993 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
994 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
995 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
996 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
997 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
998 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
999 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
1000 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
1001 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
1002 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
1003 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
1004 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1005 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1006 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1007 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1008 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1009 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1010 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1011 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1012 (0x78 << 12) | (6 << 8));
1013 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1019 n800_dss_init(&s->blizzard);
1022 s->cpu->env->regs[15] = s->cpu->env->boot_info->loader_start;
1023 s->cpu->env->GE = 0x5;
1025 /* If the machine has a slided keyboard, open it */
1027 qemu_irq_raise(omap2_gpio_in_get(s->cpu->gpif, N810_SLIDE_GPIO)[0]);
1030 #define OMAP_TAG_NOKIA_BT 0x4e01
1031 #define OMAP_TAG_WLAN_CX3110X 0x4e02
1032 #define OMAP_TAG_CBUS 0x4e03
1033 #define OMAP_TAG_EM_ASIC_BB5 0x4e04
1035 static struct omap_gpiosw_info_s {
1039 } n800_gpiosw_info[] = {
1041 "bat_cover", N800_BAT_COVER_GPIO,
1042 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1044 "cam_act", N800_CAM_ACT_GPIO,
1045 OMAP_GPIOSW_TYPE_ACTIVITY,
1047 "cam_turn", N800_CAM_TURN_GPIO,
1048 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1050 "headphone", N8X0_HEADPHONE_GPIO,
1051 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1054 }, n810_gpiosw_info[] = {
1056 "gps_reset", N810_GPS_RESET_GPIO,
1057 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1059 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1060 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1062 "headphone", N8X0_HEADPHONE_GPIO,
1063 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1065 "kb_lock", N810_KB_LOCK_GPIO,
1066 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1068 "sleepx_led", N810_SLEEPX_LED_GPIO,
1069 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1071 "slide", N810_SLIDE_GPIO,
1072 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1077 static struct omap_partition_info_s {
1082 } n800_part_info[] = {
1083 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1084 { 0x00020000, 0x00060000, 0x0, "config" },
1085 { 0x00080000, 0x00200000, 0x0, "kernel" },
1086 { 0x00280000, 0x00200000, 0x3, "initfs" },
1087 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1090 }, n810_part_info[] = {
1091 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1092 { 0x00020000, 0x00060000, 0x0, "config" },
1093 { 0x00080000, 0x00220000, 0x0, "kernel" },
1094 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1095 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1100 static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
1102 static int n8x0_atag_setup(void *p, int model)
1107 struct omap_gpiosw_info_s *gpiosw;
1108 struct omap_partition_info_s *partition;
1113 stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
1114 stw_raw(w ++, 4); /* u16 len */
1115 stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1119 stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
1120 stw_raw(w ++, 4); /* u16 len */
1121 stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */
1122 stw_raw(w ++, 115200); /* u32 console_speed */
1125 stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
1126 stw_raw(w ++, 36); /* u16 len */
1127 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1129 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1131 stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1132 stw_raw(w ++, 24); /* u8 data_lines */
1134 stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
1135 stw_raw(w ++, 8); /* u16 len */
1136 stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1137 stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1138 stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
1141 stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1142 stw_raw(w ++, 4); /* u16 len */
1143 stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1144 stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
1146 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1147 for (; gpiosw->name; gpiosw ++) {
1148 stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1149 stw_raw(w ++, 20); /* u16 len */
1150 strcpy((void *) w, gpiosw->name); /* char name[12] */
1152 stw_raw(w ++, gpiosw->line); /* u16 gpio */
1153 stw_raw(w ++, gpiosw->type);
1158 stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1159 stw_raw(w ++, 12); /* u16 len */
1161 stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */
1162 stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
1163 stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
1164 stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
1165 stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */
1166 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
1168 stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */
1171 stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1172 stw_raw(w ++, 8); /* u16 len */
1173 stw_raw(w ++, 0x25); /* u8 chip_type */
1174 stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1175 stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
1176 stw_raw(w ++, -1); /* s16 spi_cs_gpio */
1178 stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
1179 stw_raw(w ++, 16); /* u16 len */
1181 stw_raw(w ++, 0x23f); /* unsigned flags */
1182 stw_raw(w ++, -1); /* s16 power_pin */
1183 stw_raw(w ++, -1); /* s16 switch_pin */
1184 stw_raw(w ++, -1); /* s16 wp_pin */
1185 stw_raw(w ++, 0x240); /* unsigned flags */
1186 stw_raw(w ++, 0xc000); /* s16 power_pin */
1187 stw_raw(w ++, 0x0248); /* s16 switch_pin */
1188 stw_raw(w ++, 0xc000); /* s16 wp_pin */
1190 stw_raw(w ++, 0xf); /* unsigned flags */
1191 stw_raw(w ++, -1); /* s16 power_pin */
1192 stw_raw(w ++, -1); /* s16 switch_pin */
1193 stw_raw(w ++, -1); /* s16 wp_pin */
1194 stw_raw(w ++, 0); /* unsigned flags */
1195 stw_raw(w ++, 0); /* s16 power_pin */
1196 stw_raw(w ++, 0); /* s16 switch_pin */
1197 stw_raw(w ++, 0); /* s16 wp_pin */
1200 stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
1201 stw_raw(w ++, 4); /* u16 len */
1202 stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
1205 partition = (model == 810) ? n810_part_info : n800_part_info;
1206 for (; partition->name; partition ++) {
1207 stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
1208 stw_raw(w ++, 28); /* u16 len */
1209 strcpy((void *) w, partition->name); /* char name[16] */
1210 l = (void *) (w + 8);
1211 stl_raw(l ++, partition->size); /* unsigned int size */
1212 stl_raw(l ++, partition->offset); /* unsigned int offset */
1213 stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
1217 stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1218 stw_raw(w ++, 12); /* u16 len */
1220 strcpy((void *) w, "por"); /* char reason_str[12] */
1221 strcpy((void *) w, "charger"); /* char reason_str[12] */
1222 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1223 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1224 strcpy((void *) w, "mbus"); /* char reason_str[12] */
1225 strcpy((void *) w, "unknown"); /* char reason_str[12] */
1226 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1227 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1228 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1229 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1231 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1235 tag = (model == 810) ? "RX-44" : "RX-34";
1236 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1237 stw_raw(w ++, 24); /* u16 len */
1238 strcpy((void *) w, "product"); /* char component[12] */
1240 strcpy((void *) w, tag); /* char version[12] */
1243 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1244 stw_raw(w ++, 24); /* u16 len */
1245 strcpy((void *) w, "hw-build"); /* char component[12] */
1247 strcpy((void *) w, "QEMU " QEMU_VERSION); /* char version[12] */
1250 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
1251 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1252 stw_raw(w ++, 24); /* u16 len */
1253 strcpy((void *) w, "nolo"); /* char component[12] */
1255 strcpy((void *) w, tag); /* char version[12] */
1258 return (void *) w - p;
1261 static int n800_atag_setup(struct arm_boot_info *info, void *p)
1263 return n8x0_atag_setup(p, 800);
1266 static int n810_atag_setup(struct arm_boot_info *info, void *p)
1268 return n8x0_atag_setup(p, 810);
1271 static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
1272 const char *kernel_filename,
1273 const char *kernel_cmdline, const char *initrd_filename,
1274 const char *cpu_model, struct arm_boot_info *binfo, int model)
1276 struct n800_s *s = (struct n800_s *) qemu_mallocz(sizeof(*s));
1277 int sdram_size = binfo->ram_size;
1278 int onenandram_size = 0x00010000;
1281 if (ram_size < sdram_size + onenandram_size + OMAP242X_SRAM_SIZE) {
1282 fprintf(stderr, "This architecture uses %i bytes of memory\n",
1283 sdram_size + onenandram_size + OMAP242X_SRAM_SIZE);
1287 s->cpu = omap2420_mpu_init(sdram_size, cpu_model);
1289 /* Setup peripherals
1291 * Believed external peripherals layout in the N810:
1296 * Conexant cx3110x (WLAN)
1297 * optional: pc2400m (WiMAX)
1299 * TLV320AIC33 (audio codec)
1300 * TCM825x (camera by Toshiba)
1301 * lp5521 (clever LEDs)
1302 * tsl2563 (light sensor, hwmon, model 7, rev. 0)
1303 * lm8323 (keypad, manf 00, rev 04)
1305 * tmp105 (temperature sensor, hwmon)
1307 * (somewhere on i2c - maybe N800-only)
1308 * tea5761 (FM tuner)
1311 * (some serial port)
1312 * csr41814 (Bluetooth)
1318 n800_tsc_kbd_setup(s);
1319 else if (model == 810) {
1330 /* Setup initial (reset) machine state */
1332 /* Start at the OneNAND bootloader. */
1333 s->cpu->env->regs[15] = 0;
1335 if (kernel_filename) {
1336 /* Or at the linux loader. */
1337 binfo->kernel_filename = kernel_filename;
1338 binfo->kernel_cmdline = kernel_cmdline;
1339 binfo->initrd_filename = initrd_filename;
1340 arm_load_kernel(s->cpu->env, binfo);
1342 qemu_register_reset(n8x0_boot_init, s);
1346 if (option_rom[0] && (boot_device[0] == 'n' || !kernel_filename)) {
1347 /* No, wait, better start at the ROM. */
1348 s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000;
1350 /* This is intended for loading the `secondary.bin' program from
1351 * Nokia images (the NOLO bootloader). The entry point seems
1352 * to be at OMAP2_Q2_BASE + 0x400000.
1354 * The `2nd.bin' files contain some kind of earlier boot code and
1355 * for them the entry point needs to be set to OMAP2_SRAM_BASE.
1357 * The code above is for loading the `zImage' file from Nokia
1359 printf("%i bytes of image loaded\n", load_image(option_rom[0],
1360 phys_ram_base + 0x400000));
1362 n800_setup_nolo_tags(phys_ram_base + sdram_size);
1364 /* FIXME: We shouldn't really be doing this here. The LCD controller
1365 will set the size once configured, so this just sets an initial
1366 size until the guest activates the display. */
1367 ds = get_displaystate();
1368 ds->surface = qemu_resize_displaysurface(ds->surface, 800, 480, 32, 4 * 800);
1372 static struct arm_boot_info n800_binfo = {
1373 .loader_start = OMAP2_Q2_BASE,
1374 /* Actually two chips of 0x4000000 bytes each */
1375 .ram_size = 0x08000000,
1377 .atag_board = n800_atag_setup,
1380 static struct arm_boot_info n810_binfo = {
1381 .loader_start = OMAP2_Q2_BASE,
1382 /* Actually two chips of 0x4000000 bytes each */
1383 .ram_size = 0x08000000,
1384 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1385 * used by some older versions of the bootloader and 5555 is used
1386 * instead (including versions that shipped with many devices). */
1388 .atag_board = n810_atag_setup,
1391 static void n800_init(ram_addr_t ram_size, int vga_ram_size,
1392 const char *boot_device,
1393 const char *kernel_filename, const char *kernel_cmdline,
1394 const char *initrd_filename, const char *cpu_model)
1396 return n8x0_init(ram_size, boot_device,
1397 kernel_filename, kernel_cmdline, initrd_filename,
1398 cpu_model, &n800_binfo, 800);
1401 static void n810_init(ram_addr_t ram_size, int vga_ram_size,
1402 const char *boot_device,
1403 const char *kernel_filename, const char *kernel_cmdline,
1404 const char *initrd_filename, const char *cpu_model)
1406 return n8x0_init(ram_size, boot_device,
1407 kernel_filename, kernel_cmdline, initrd_filename,
1408 cpu_model, &n810_binfo, 810);
1411 QEMUMachine n800_machine = {
1413 .desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)",
1415 .ram_require = (0x08000000 + 0x00010000 + OMAP242X_SRAM_SIZE) |
1419 QEMUMachine n810_machine = {
1421 .desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)",
1423 .ram_require = (0x08000000 + 0x00010000 + OMAP242X_SRAM_SIZE) |