2 * Texas Instruments OMAP processors.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 # define hw_omap_h "omap.h"
23 # define OMAP_EMIFS_BASE 0x00000000
24 # define OMAP2_Q0_BASE 0x00000000
25 # define OMAP_CS0_BASE 0x00000000
26 # define OMAP_CS1_BASE 0x04000000
27 # define OMAP_CS2_BASE 0x08000000
28 # define OMAP_CS3_BASE 0x0c000000
29 # define OMAP_EMIFF_BASE 0x10000000
30 # define OMAP_IMIF_BASE 0x20000000
31 # define OMAP_LOCALBUS_BASE 0x30000000
32 # define OMAP2_Q1_BASE 0x40000000
33 # define OMAP2_L4_BASE 0x48000000
34 # define OMAP2_SRAM_BASE 0x40200000
35 # define OMAP2_L3_BASE 0x68000000
36 # define OMAP2_Q2_BASE 0x80000000
37 # define OMAP2_Q3_BASE 0xc0000000
38 # define OMAP3_Q1_BASE 0x40000000
39 # define OMAP3_L4_BASE 0x48000000
40 # define OMAP3_SRAM_BASE 0x40200000
41 # define OMAP3_L3_BASE 0x68000000
42 # define OMAP3_Q2_BASE 0x80000000
43 # define OMAP3_Q3_BASE 0xc0000000
44 # define OMAP_MPUI_BASE 0xe1000000
46 # define OMAP730_SRAM_SIZE 0x00032000
47 # define OMAP15XX_SRAM_SIZE 0x00030000
48 # define OMAP16XX_SRAM_SIZE 0x00004000
49 # define OMAP1611_SRAM_SIZE 0x0003e800
50 # define OMAP242X_SRAM_SIZE 0x000a0000
51 # define OMAP243X_SRAM_SIZE 0x00010000
52 # define OMAP3XXX_SRAM_SIZE 0x00010000
53 # define OMAP3XXX_BOOTROM_SIZE 0x00008000
54 # define OMAP_CS0_SIZE 0x04000000
55 # define OMAP_CS1_SIZE 0x04000000
56 # define OMAP_CS2_SIZE 0x04000000
57 # define OMAP_CS3_SIZE 0x04000000
60 struct omap_mpu_state_s;
61 typedef struct clk *omap_clk;
62 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
63 void omap_clk_init(struct omap_mpu_state_s *mpu);
64 void omap_clk_adduser(struct clk *clk, qemu_irq user);
65 void omap_clk_get(omap_clk clk);
66 void omap_clk_put(omap_clk clk);
67 void omap_clk_onoff(omap_clk clk, int on);
68 void omap_clk_canidle(omap_clk clk, int can);
69 void omap_clk_setrate(omap_clk clk, int divide, int multiply);
70 int64_t omap_clk_getrate(omap_clk clk);
71 void omap_clk_reparent(omap_clk clk, omap_clk parent);
76 struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num);
78 struct omap_target_agent_s;
79 struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs);
80 target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
82 target_phys_addr_t omap_l4_base(struct omap_target_agent_s *ta, int region);
83 uint32_t omap_l4_size(struct omap_target_agent_s *ta, int region);
84 # define l4_register_io_memory cpu_register_io_memory
86 struct omap_intr_handler_s;
87 struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
88 unsigned long size, unsigned char nbanks, qemu_irq **pins,
89 qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);
90 struct omap_intr_handler_s *omap2_inth_init(struct omap_mpu_state_s *mpu,
91 target_phys_addr_t base,
92 int size, int nbanks, qemu_irq **pins,
93 qemu_irq parent_irq, qemu_irq parent_fiq,
94 omap_clk fclk, omap_clk iclk);
95 void omap_inth_reset(struct omap_intr_handler_s *s);
98 struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
99 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
100 struct omap_mpu_state_s *mpu);
103 struct omap3_prm_s *omap3_prm_init(struct omap_target_agent_s *ta,
104 qemu_irq mpu_int, qemu_irq iva_int,
105 struct omap_mpu_state_s *mpu);
108 struct omap3_cm_s *omap3_cm_init(struct omap_target_agent_s *ta,
109 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
110 struct omap_mpu_state_s *mpu);
112 struct omap_sysctl_s;
113 struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
114 omap_clk iclk, struct omap_mpu_state_s *mpu);
117 struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
118 void omap_sdrc_write_mcfg(struct omap_sdrc_s *s, uint32_t value, uint32_t cs);
122 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
123 target_phys_addr_t base, qemu_irq irq);
124 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
125 void (*base_upd)(void *opaque, target_phys_addr_t new),
126 void (*unmap)(void *opaque), void *opaque, int devicetype);
129 * Common IRQ numbers for level 1 interrupt handler
130 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
132 # define OMAP_INT_CAMERA 1
133 # define OMAP_INT_FIQ 3
134 # define OMAP_INT_RTDX 6
135 # define OMAP_INT_DSP_MMU_ABORT 7
136 # define OMAP_INT_HOST 8
137 # define OMAP_INT_ABORT 9
138 # define OMAP_INT_BRIDGE_PRIV 13
139 # define OMAP_INT_GPIO_BANK1 14
140 # define OMAP_INT_UART3 15
141 # define OMAP_INT_TIMER3 16
142 # define OMAP_INT_DMA_CH0_6 19
143 # define OMAP_INT_DMA_CH1_7 20
144 # define OMAP_INT_DMA_CH2_8 21
145 # define OMAP_INT_DMA_CH3 22
146 # define OMAP_INT_DMA_CH4 23
147 # define OMAP_INT_DMA_CH5 24
148 # define OMAP_INT_DMA_LCD 25
149 # define OMAP_INT_TIMER1 26
150 # define OMAP_INT_WD_TIMER 27
151 # define OMAP_INT_BRIDGE_PUB 28
152 # define OMAP_INT_TIMER2 30
153 # define OMAP_INT_LCD_CTRL 31
156 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
158 # define OMAP_INT_15XX_IH2_IRQ 0
159 # define OMAP_INT_15XX_LB_MMU 17
160 # define OMAP_INT_15XX_LOCAL_BUS 29
163 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
165 # define OMAP_INT_1510_SPI_TX 4
166 # define OMAP_INT_1510_SPI_RX 5
167 # define OMAP_INT_1510_DSP_MAILBOX1 10
168 # define OMAP_INT_1510_DSP_MAILBOX2 11
171 * OMAP-310 specific IRQ numbers for level 1 interrupt handler
173 # define OMAP_INT_310_McBSP2_TX 4
174 # define OMAP_INT_310_McBSP2_RX 5
175 # define OMAP_INT_310_HSB_MAILBOX1 12
176 # define OMAP_INT_310_HSAB_MMU 18
179 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
181 # define OMAP_INT_1610_IH2_IRQ 0
182 # define OMAP_INT_1610_IH2_FIQ 2
183 # define OMAP_INT_1610_McBSP2_TX 4
184 # define OMAP_INT_1610_McBSP2_RX 5
185 # define OMAP_INT_1610_DSP_MAILBOX1 10
186 # define OMAP_INT_1610_DSP_MAILBOX2 11
187 # define OMAP_INT_1610_LCD_LINE 12
188 # define OMAP_INT_1610_GPTIMER1 17
189 # define OMAP_INT_1610_GPTIMER2 18
190 # define OMAP_INT_1610_SSR_FIFO_0 29
193 * OMAP-730 specific IRQ numbers for level 1 interrupt handler
195 # define OMAP_INT_730_IH2_FIQ 0
196 # define OMAP_INT_730_IH2_IRQ 1
197 # define OMAP_INT_730_USB_NON_ISO 2
198 # define OMAP_INT_730_USB_ISO 3
199 # define OMAP_INT_730_ICR 4
200 # define OMAP_INT_730_EAC 5
201 # define OMAP_INT_730_GPIO_BANK1 6
202 # define OMAP_INT_730_GPIO_BANK2 7
203 # define OMAP_INT_730_GPIO_BANK3 8
204 # define OMAP_INT_730_McBSP2TX 10
205 # define OMAP_INT_730_McBSP2RX 11
206 # define OMAP_INT_730_McBSP2RX_OVF 12
207 # define OMAP_INT_730_LCD_LINE 14
208 # define OMAP_INT_730_GSM_PROTECT 15
209 # define OMAP_INT_730_TIMER3 16
210 # define OMAP_INT_730_GPIO_BANK5 17
211 # define OMAP_INT_730_GPIO_BANK6 18
212 # define OMAP_INT_730_SPGIO_WR 29
215 * Common IRQ numbers for level 2 interrupt handler
217 # define OMAP_INT_KEYBOARD 1
218 # define OMAP_INT_uWireTX 2
219 # define OMAP_INT_uWireRX 3
220 # define OMAP_INT_I2C 4
221 # define OMAP_INT_MPUIO 5
222 # define OMAP_INT_USB_HHC_1 6
223 # define OMAP_INT_McBSP3TX 10
224 # define OMAP_INT_McBSP3RX 11
225 # define OMAP_INT_McBSP1TX 12
226 # define OMAP_INT_McBSP1RX 13
227 # define OMAP_INT_UART1 14
228 # define OMAP_INT_UART2 15
229 # define OMAP_INT_USB_W2FC 20
230 # define OMAP_INT_1WIRE 21
231 # define OMAP_INT_OS_TIMER 22
232 # define OMAP_INT_OQN 23
233 # define OMAP_INT_GAUGE_32K 24
234 # define OMAP_INT_RTC_TIMER 25
235 # define OMAP_INT_RTC_ALARM 26
236 # define OMAP_INT_DSP_MMU 28
239 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
241 # define OMAP_INT_1510_BT_MCSI1TX 16
242 # define OMAP_INT_1510_BT_MCSI1RX 17
243 # define OMAP_INT_1510_SoSSI_MATCH 19
244 # define OMAP_INT_1510_MEM_STICK 27
245 # define OMAP_INT_1510_COM_SPI_RO 31
248 * OMAP-310 specific IRQ numbers for level 2 interrupt handler
250 # define OMAP_INT_310_FAC 0
251 # define OMAP_INT_310_USB_HHC_2 7
252 # define OMAP_INT_310_MCSI1_FE 16
253 # define OMAP_INT_310_MCSI2_FE 17
254 # define OMAP_INT_310_USB_W2FC_ISO 29
255 # define OMAP_INT_310_USB_W2FC_NON_ISO 30
256 # define OMAP_INT_310_McBSP2RX_OF 31
259 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
261 # define OMAP_INT_1610_FAC 0
262 # define OMAP_INT_1610_USB_HHC_2 7
263 # define OMAP_INT_1610_USB_OTG 8
264 # define OMAP_INT_1610_SoSSI 9
265 # define OMAP_INT_1610_BT_MCSI1TX 16
266 # define OMAP_INT_1610_BT_MCSI1RX 17
267 # define OMAP_INT_1610_SoSSI_MATCH 19
268 # define OMAP_INT_1610_MEM_STICK 27
269 # define OMAP_INT_1610_McBSP2RX_OF 31
270 # define OMAP_INT_1610_STI 32
271 # define OMAP_INT_1610_STI_WAKEUP 33
272 # define OMAP_INT_1610_GPTIMER3 34
273 # define OMAP_INT_1610_GPTIMER4 35
274 # define OMAP_INT_1610_GPTIMER5 36
275 # define OMAP_INT_1610_GPTIMER6 37
276 # define OMAP_INT_1610_GPTIMER7 38
277 # define OMAP_INT_1610_GPTIMER8 39
278 # define OMAP_INT_1610_GPIO_BANK2 40
279 # define OMAP_INT_1610_GPIO_BANK3 41
280 # define OMAP_INT_1610_MMC2 42
281 # define OMAP_INT_1610_CF 43
282 # define OMAP_INT_1610_WAKE_UP_REQ 46
283 # define OMAP_INT_1610_GPIO_BANK4 48
284 # define OMAP_INT_1610_SPI 49
285 # define OMAP_INT_1610_DMA_CH6 53
286 # define OMAP_INT_1610_DMA_CH7 54
287 # define OMAP_INT_1610_DMA_CH8 55
288 # define OMAP_INT_1610_DMA_CH9 56
289 # define OMAP_INT_1610_DMA_CH10 57
290 # define OMAP_INT_1610_DMA_CH11 58
291 # define OMAP_INT_1610_DMA_CH12 59
292 # define OMAP_INT_1610_DMA_CH13 60
293 # define OMAP_INT_1610_DMA_CH14 61
294 # define OMAP_INT_1610_DMA_CH15 62
295 # define OMAP_INT_1610_NAND 63
298 * OMAP-730 specific IRQ numbers for level 2 interrupt handler
300 # define OMAP_INT_730_HW_ERRORS 0
301 # define OMAP_INT_730_NFIQ_PWR_FAIL 1
302 # define OMAP_INT_730_CFCD 2
303 # define OMAP_INT_730_CFIREQ 3
304 # define OMAP_INT_730_I2C 4
305 # define OMAP_INT_730_PCC 5
306 # define OMAP_INT_730_MPU_EXT_NIRQ 6
307 # define OMAP_INT_730_SPI_100K_1 7
308 # define OMAP_INT_730_SYREN_SPI 8
309 # define OMAP_INT_730_VLYNQ 9
310 # define OMAP_INT_730_GPIO_BANK4 10
311 # define OMAP_INT_730_McBSP1TX 11
312 # define OMAP_INT_730_McBSP1RX 12
313 # define OMAP_INT_730_McBSP1RX_OF 13
314 # define OMAP_INT_730_UART_MODEM_IRDA_2 14
315 # define OMAP_INT_730_UART_MODEM_1 15
316 # define OMAP_INT_730_MCSI 16
317 # define OMAP_INT_730_uWireTX 17
318 # define OMAP_INT_730_uWireRX 18
319 # define OMAP_INT_730_SMC_CD 19
320 # define OMAP_INT_730_SMC_IREQ 20
321 # define OMAP_INT_730_HDQ_1WIRE 21
322 # define OMAP_INT_730_TIMER32K 22
323 # define OMAP_INT_730_MMC_SDIO 23
324 # define OMAP_INT_730_UPLD 24
325 # define OMAP_INT_730_USB_HHC_1 27
326 # define OMAP_INT_730_USB_HHC_2 28
327 # define OMAP_INT_730_USB_GENI 29
328 # define OMAP_INT_730_USB_OTG 30
329 # define OMAP_INT_730_CAMERA_IF 31
330 # define OMAP_INT_730_RNG 32
331 # define OMAP_INT_730_DUAL_MODE_TIMER 33
332 # define OMAP_INT_730_DBB_RF_EN 34
333 # define OMAP_INT_730_MPUIO_KEYPAD 35
334 # define OMAP_INT_730_SHA1_MD5 36
335 # define OMAP_INT_730_SPI_100K_2 37
336 # define OMAP_INT_730_RNG_IDLE 38
337 # define OMAP_INT_730_MPUIO 39
338 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
339 # define OMAP_INT_730_LLPC_OE_FALLING 41
340 # define OMAP_INT_730_LLPC_OE_RISING 42
341 # define OMAP_INT_730_LLPC_VSYNC 43
342 # define OMAP_INT_730_WAKE_UP_REQ 46
343 # define OMAP_INT_730_DMA_CH6 53
344 # define OMAP_INT_730_DMA_CH7 54
345 # define OMAP_INT_730_DMA_CH8 55
346 # define OMAP_INT_730_DMA_CH9 56
347 # define OMAP_INT_730_DMA_CH10 57
348 # define OMAP_INT_730_DMA_CH11 58
349 # define OMAP_INT_730_DMA_CH12 59
350 # define OMAP_INT_730_DMA_CH13 60
351 # define OMAP_INT_730_DMA_CH14 61
352 # define OMAP_INT_730_DMA_CH15 62
353 # define OMAP_INT_730_NAND 63
356 * OMAP-24xx common IRQ numbers
358 # define OMAP_INT_24XX_STI 4
359 # define OMAP_INT_24XX_SYS_NIRQ 7
360 # define OMAP_INT_24XX_L3_IRQ 10
361 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11
362 # define OMAP_INT_24XX_SDMA_IRQ0 12
363 # define OMAP_INT_24XX_SDMA_IRQ1 13
364 # define OMAP_INT_24XX_SDMA_IRQ2 14
365 # define OMAP_INT_24XX_SDMA_IRQ3 15
366 # define OMAP_INT_243X_MCBSP2_IRQ 16
367 # define OMAP_INT_243X_MCBSP3_IRQ 17
368 # define OMAP_INT_243X_MCBSP4_IRQ 18
369 # define OMAP_INT_243X_MCBSP5_IRQ 19
370 # define OMAP_INT_24XX_GPMC_IRQ 20
371 # define OMAP_INT_24XX_GUFFAW_IRQ 21
372 # define OMAP_INT_24XX_IVA_IRQ 22
373 # define OMAP_INT_24XX_EAC_IRQ 23
374 # define OMAP_INT_24XX_CAM_IRQ 24
375 # define OMAP_INT_24XX_DSS_IRQ 25
376 # define OMAP_INT_24XX_MAIL_U0_MPU 26
377 # define OMAP_INT_24XX_DSP_UMA 27
378 # define OMAP_INT_24XX_DSP_MMU 28
379 # define OMAP_INT_24XX_GPIO_BANK1 29
380 # define OMAP_INT_24XX_GPIO_BANK2 30
381 # define OMAP_INT_24XX_GPIO_BANK3 31
382 # define OMAP_INT_24XX_GPIO_BANK4 32
383 # define OMAP_INT_243X_GPIO_BANK5 33
384 # define OMAP_INT_24XX_MAIL_U3_MPU 34
385 # define OMAP_INT_24XX_WDT3 35
386 # define OMAP_INT_24XX_WDT4 36
387 # define OMAP_INT_24XX_GPTIMER1 37
388 # define OMAP_INT_24XX_GPTIMER2 38
389 # define OMAP_INT_24XX_GPTIMER3 39
390 # define OMAP_INT_24XX_GPTIMER4 40
391 # define OMAP_INT_24XX_GPTIMER5 41
392 # define OMAP_INT_24XX_GPTIMER6 42
393 # define OMAP_INT_24XX_GPTIMER7 43
394 # define OMAP_INT_24XX_GPTIMER8 44
395 # define OMAP_INT_24XX_GPTIMER9 45
396 # define OMAP_INT_24XX_GPTIMER10 46
397 # define OMAP_INT_24XX_GPTIMER11 47
398 # define OMAP_INT_24XX_GPTIMER12 48
399 # define OMAP_INT_24XX_PKA_IRQ 50
400 # define OMAP_INT_24XX_SHA1MD5_IRQ 51
401 # define OMAP_INT_24XX_RNG_IRQ 52
402 # define OMAP_INT_24XX_MG_IRQ 53
403 # define OMAP_INT_24XX_I2C1_IRQ 56
404 # define OMAP_INT_24XX_I2C2_IRQ 57
405 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59
406 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60
407 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62
408 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63
409 # define OMAP_INT_243X_MCBSP1_IRQ 64
410 # define OMAP_INT_24XX_MCSPI1_IRQ 65
411 # define OMAP_INT_24XX_MCSPI2_IRQ 66
412 # define OMAP_INT_24XX_SSI1_IRQ0 67
413 # define OMAP_INT_24XX_SSI1_IRQ1 68
414 # define OMAP_INT_24XX_SSI2_IRQ0 69
415 # define OMAP_INT_24XX_SSI2_IRQ1 70
416 # define OMAP_INT_24XX_SSI_GDD_IRQ 71
417 # define OMAP_INT_24XX_UART1_IRQ 72
418 # define OMAP_INT_24XX_UART2_IRQ 73
419 # define OMAP_INT_24XX_UART3_IRQ 74
420 # define OMAP_INT_24XX_USB_IRQ_GEN 75
421 # define OMAP_INT_24XX_USB_IRQ_NISO 76
422 # define OMAP_INT_24XX_USB_IRQ_ISO 77
423 # define OMAP_INT_24XX_USB_IRQ_HGEN 78
424 # define OMAP_INT_24XX_USB_IRQ_HSOF 79
425 # define OMAP_INT_24XX_USB_IRQ_OTG 80
426 # define OMAP_INT_24XX_VLYNQ_IRQ 81
427 # define OMAP_INT_24XX_MMC_IRQ 83
428 # define OMAP_INT_24XX_MS_IRQ 84
429 # define OMAP_INT_24XX_FAC_IRQ 85
430 # define OMAP_INT_24XX_MCSPI3_IRQ 91
431 # define OMAP_INT_243X_HS_USB_MC 92
432 # define OMAP_INT_243X_HS_USB_DMA 93
433 # define OMAP_INT_243X_CARKIT 94
434 # define OMAP_INT_34XX_GPTIMER12 95
437 * OMAP-3XXX common IRQ numbers
439 #define OMAP_INT_3XXX_EMUINT 0 /* MPU emulation */
440 #define OMAP_INT_3XXX_COMMTX 1 /* MPU emulation */
441 #define OMAP_INT_3XXX_COMMRX 2 /* MPU emulation */
442 #define OMAP_INT_3XXX_BENCH 3 /* MPU emulation */
443 #define OMAP_INT_3XXX_MCBSP2_ST_IRQ 4 /* Sidetone MCBSP2 overflow */
444 #define OMAP_INT_3XXX_MCBSP3_ST_IRQ 5 /* Sidetone MCBSP3 overflow */
445 #define OMAP_INT_3XXX_SSM_ABORT_IRQ 6
446 #define OMAP_INT_3XXX_SYS_NIRQ 7 /* External source (active low) */
447 #define OMAP_INT_3XXX_D2D_FW_IRQ 8
448 #define OMAP_INT_3XXX_SMX_DBG_IRQ 9 /* L3 interconnect error for debug */
449 #define OMAP_INT_3XXX_SMX_APP_IRQ 10 /* L3 interconnect error for application */
450 #define OMAP_INT_3XXX_PRCM_MPU_IRQ 11 /* PRCM module IRQ */
451 #define OMAP_INT_3XXX_SDMA_IRQ0 12 /* System DMA request 0 */
452 #define OMAP_INT_3XXX_SDMA_IRQ1 13 /* System DMA request 1 */
453 #define OMAP_INT_3XXX_SDMA_IRQ2 14 /* System DMA request 2 */
454 #define OMAP_INT_3XXX_SDMA_IRQ3 15 /* System DMA request 3 */
455 #define OMAP_INT_3XXX_MCBSP1_IRQ 16 /* MCBSP module 1 IRQ */
456 #define OMAP_INT_3XXX_MCBSP2_IRQ 17 /* MCBSP module 2 IRQ */
457 /* IRQ18 is reserved */
458 /* IRQ19 is reserved */
459 #define OMAP_INT_3XXX_GPMC_IRQ 20 /* General-purpose memory controller module */
460 #define OMAP_INT_3XXX_SGX_IRQ 21 /* 2D/3D graphics module */
461 #define OMAP_INT_3XXX_MCBSP3_IRQ 22 /* MCBSP module 3 */
462 #define OMAP_INT_3XXX_MCBSP4_IRQ 23 /* MCBSP module 4 */
463 #define OMAP_INT_3XXX_CAM_IRQ0 24 /* Camera interface request 0 */
464 #define OMAP_INT_3XXX_DSS_IRQ 25 /* Display subsystem module */
465 #define OMAP_INT_3XXX_MAIL_U0_MPU 26 /* Mailbox user 0 request */
466 #define OMAP_INT_3XXX_MCBSP5_IRQ 27 /* MCBSP module 5 */
467 #define OMAP_INT_3XXX_IVA2_MMU_IRQ 28 /* IVA2 MMU */
468 #define OMAP_INT_3XXX_GPIO1_MPU_IRQ 29 /* GPIO module 1 */
469 #define OMAP_INT_3XXX_GPIO2_MPU_IRQ 30 /* GPIO module 2 */
470 #define OMAP_INT_3XXX_GPIO3_MPU_IRQ 31 /* GPIO module 3 */
471 #define OMAP_INT_3XXX_GPIO4_MPU_IRQ 32 /* GPIO module 4 */
472 #define OMAP_INT_3XXX_GPIO5_MPU_IRQ 33 /* GPIO module 5 */
473 #define OMAP_INT_3XXX_GPIO6_MPU_IRQ 34 /* GPIO module 6 */
474 #define OMAP_INT_3XXX_USIM_IRQ 35
475 #define OMAP_INT_3XXX_WDT3_IRQ 36 /* Watchdog timer module 3 overflow */
476 #define OMAP_INT_3XXX_GPT1_IRQ 37 /* General-purpose timer module 1 */
477 #define OMAP_INT_3XXX_GPT2_IRQ 38 /* General-purpose timer module 2 */
478 #define OMAP_INT_3XXX_GPT3_IRQ 39 /* General-purpose timer module 3 */
479 #define OMAP_INT_3XXX_GPT4_IRQ 40 /* General-purpose timer module 4 */
480 #define OMAP_INT_3XXX_GPT5_IRQ 41 /* General-purpose timer module 5 */
481 #define OMAP_INT_3XXX_GPT6_IRQ 42 /* General-purpose timer module 6 */
482 #define OMAP_INT_3XXX_GPT7_IRQ 43 /* General-purpose timer module 7 */
483 #define OMAP_INT_3XXX_GPT8_IRQ 44 /* General-purpose timer module 8 */
484 #define OMAP_INT_3XXX_GPT9_IRQ 45 /* General-purpose timer module 9 */
485 #define OMAP_INT_3XXX_GPT10_IRQ 46 /* General-purpose timer module 10 */
486 #define OMAP_INT_3XXX_GPT11_IRQ 47 /* General-purpose timer module 11 */
487 #define OMAP_INT_3XXX_MCSPI4_IRQ 48 /* MCSPI module 4 */
488 #define OMAP_INT_3XXX_SHA1MD52_IRQ 49
489 #define OMAP_INT_3XXX_FPKA_READY 50
490 #define OMAP_INT_3XXX_SHA1MD51_IRQ 51
491 #define OMAP_INT_3XXX_RNG_IRQ 52
492 #define OMAP_INT_3XXX_MG_IRQ 53
493 #define OMAP_INT_3XXX_MCBSP4_IRQ_TX 54 /* MCBSP module 4 transmit */
494 #define OMAP_INT_3XXX_MCBSP4_IRQ_RX 55 /* MCBSP module 4 receive */
495 #define OMAP_INT_3XXX_I2C1_IRQ 56 /* I2C module 1 */
496 #define OMAP_INT_3XXX_I2C2_IRQ 57 /* I2C module 2 */
497 #define OMAP_INT_3XXX_HDQ_IRQ 58 /* HDQ/1-Wire */
498 #define OMAP_INT_3XXX_MCBSP1_IRQ_TX 59 /* MCBSP module 1 transmit */
499 #define OMAP_INT_3XXX_MCBSP1_IRQ_RX 60 /* MCBSP module 1 receive */
500 #define OMAP_INT_3XXX_I2C3_IRQ 61 /* I2C module 3 */
501 #define OMAP_INT_3XXX_MCBSP2_IRQ_TX 62 /* MCBSP module 2 transmit */
502 #define OMAP_INT_3XXX_MCBSP2_IRQ_RX 63 /* MCBSP module 2 receive */
503 #define OMAP_INT_3XXX_FPKA_ERROR 64
504 #define OMAP_INT_3XXX_MCSPI1_IRQ 65 /* MCSPI module 1 */
505 #define OMAP_INT_3XXX_MCSPI2_IRQ 66 /* MCSPI module 2 */
506 /* IRQ67 is reserved */
507 /* IRQ68 is reserved */
508 /* IRQ69 is reserved */
509 /* IRQ70 is reserved */
510 /* IRQ71 is reserved */
511 #define OMAP_INT_3XXX_UART1_IRQ 72 /* UART module 1 */
512 #define OMAP_INT_3XXX_UART2_IRQ 73 /* UART module 2 */
513 #define OMAP_INT_3XXX_UART3_IRQ 74 /* UART module 3 (also infrared)*/
514 #define OMAP_INT_3XXX_PBIAS_IRQ 75 /* Merged interrupt for PBIASlite1 and 2 */
515 #define OMAP_INT_3XXX_OHCI_IRQ 76 /* OHCI controller HSUSB MP Host interrupt */
516 #define OMAP_INT_3XXX_EHCI_IRQ 77 /* EHCI controller HSUSB MP Host interrupt */
517 #define OMAP_INT_3XXX_TLL_IRQ 78 /* HSUSB MP TLL interrupt */
518 /* IRQ79 is reserved */
519 /* IRQ80 is reserved */
520 #define OMAP_INT_3XXX_MCBSP5_IRQ_TX 81 /* MCBSP module 5 transmit */
521 #define OMAP_INT_3XXX_MCBSP5_IRQ_RX 82 /* MCBSP module 5 receive */
522 #define OMAP_INT_3XXX_MMC1_IRQ 83 /* MMC/SD module 1 */
523 #define OMAP_INT_3XXX_MS_IRQ 84
524 /* IRQ85 is reserved */
525 #define OMAP_INT_3XXX_MMC2_IRQ 86 /* MMC/SD module 2 */
526 #define OMAP_INT_3XXX_MPU_ICR_IRQ 87 /* MPU ICR */
527 #define OMAP_INT_3XXX_D2DFRINT 88 /* 3G coprocessor */
528 #define OMAP_INT_3XXX_MCBSP3_IRQ_TX 89 /* MCBSP module 3 transmit */
529 #define OMAP_INT_3XXX_MCBSP3_IRQ_RX 90 /* MCBSP module 3 receive */
530 #define OMAP_INT_3XXX_MCSPI3_IRQ 91 /* MCSPI module 3 */
531 #define OMAP_INT_3XXX_HSUSB_MC 92 /* High-Speed USB OTG controller */
532 #define OMAP_INT_3XXX_HSUSB_DMA 93 /* High-Speed USB OTG DMA controller */
533 #define OMAP_INT_3XXX_MMC3_IRQ 94 /* MMC/SD module 3 */
534 #define OMAP_INT_3XXX_GPT12_IRQ 95 /* General-purpose timer module 12 */
537 enum omap_dma_model {
545 struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
546 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
547 enum omap_dma_model model);
548 struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
549 struct omap_mpu_state_s *mpu, int fifo,
550 int chans, omap_clk iclk, omap_clk fclk);
551 struct soc_dma_s *omap3_dma4_init(struct omap_target_agent_s *ta,
552 struct omap_mpu_state_s *mpu,
553 qemu_irq *irqs, int chans,
554 omap_clk iclk, omap_clk fclk);
555 void omap_dma_reset(struct soc_dma_s *s);
562 /* Only used in OMAP DMA 3.x gigacells */
566 imif, /* omap16xx: ocp_t1 */
568 local, /* omap16xx: ocp_t2 */
570 __omap_dma_port_last,
578 } omap_dma_addressing_t;
580 /* Only used in OMAP DMA 3.x gigacells */
581 struct omap_dma_lcd_channel_s {
582 enum omap_dma_port src;
583 target_phys_addr_t src_f1_top;
584 target_phys_addr_t src_f1_bottom;
585 target_phys_addr_t src_f2_top;
586 target_phys_addr_t src_f2_bottom;
588 /* Used in OMAP DMA 3.2 gigacell */
589 unsigned char brust_f1;
590 unsigned char pack_f1;
591 unsigned char data_type_f1;
592 unsigned char brust_f2;
593 unsigned char pack_f2;
594 unsigned char data_type_f2;
595 unsigned char end_prog;
596 unsigned char repeat;
597 unsigned char auto_init;
598 unsigned char priority;
600 unsigned char running;
602 unsigned char omap_3_1_compatible_disable;
604 unsigned char lch_type;
605 int16_t element_index_f1;
606 int16_t element_index_f2;
607 int32_t frame_index_f1;
608 int32_t frame_index_f2;
609 uint16_t elements_f1;
611 uint16_t elements_f2;
613 omap_dma_addressing_t mode_f1;
614 omap_dma_addressing_t mode_f2;
616 /* Destination port is fixed. */
622 ram_addr_t phys_framebuffer[2];
624 struct omap_mpu_state_s *mpu;
625 } *omap_dma_get_lcdch(struct soc_dma_s *s);
628 * DMA request numbers for OMAP1
629 * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
631 # define OMAP_DMA_NO_DEVICE 0
632 # define OMAP_DMA_MCSI1_TX 1
633 # define OMAP_DMA_MCSI1_RX 2
634 # define OMAP_DMA_I2C_RX 3
635 # define OMAP_DMA_I2C_TX 4
636 # define OMAP_DMA_EXT_NDMA_REQ0 5
637 # define OMAP_DMA_EXT_NDMA_REQ1 6
638 # define OMAP_DMA_UWIRE_TX 7
639 # define OMAP_DMA_MCBSP1_TX 8
640 # define OMAP_DMA_MCBSP1_RX 9
641 # define OMAP_DMA_MCBSP3_TX 10
642 # define OMAP_DMA_MCBSP3_RX 11
643 # define OMAP_DMA_UART1_TX 12
644 # define OMAP_DMA_UART1_RX 13
645 # define OMAP_DMA_UART2_TX 14
646 # define OMAP_DMA_UART2_RX 15
647 # define OMAP_DMA_MCBSP2_TX 16
648 # define OMAP_DMA_MCBSP2_RX 17
649 # define OMAP_DMA_UART3_TX 18
650 # define OMAP_DMA_UART3_RX 19
651 # define OMAP_DMA_CAMERA_IF_RX 20
652 # define OMAP_DMA_MMC_TX 21
653 # define OMAP_DMA_MMC_RX 22
654 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */
655 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
656 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
657 # define OMAP_DMA_USB_W2FC_RX0 26
658 # define OMAP_DMA_USB_W2FC_RX1 27
659 # define OMAP_DMA_USB_W2FC_RX2 28
660 # define OMAP_DMA_USB_W2FC_TX0 29
661 # define OMAP_DMA_USB_W2FC_TX1 30
662 # define OMAP_DMA_USB_W2FC_TX2 31
664 /* These are only for 1610 */
665 # define OMAP_DMA_CRYPTO_DES_IN 32
666 # define OMAP_DMA_SPI_TX 33
667 # define OMAP_DMA_SPI_RX 34
668 # define OMAP_DMA_CRYPTO_HASH 35
669 # define OMAP_DMA_CCP_ATTN 36
670 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
671 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38
672 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39
673 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40
674 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41
675 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42
676 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43
677 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44
678 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45
679 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46
680 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47
681 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48
682 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49
683 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50
684 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51
685 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52
686 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53
687 # define OMAP_DMA_MMC2_TX 54
688 # define OMAP_DMA_MMC2_RX 55
689 # define OMAP_DMA_CRYPTO_DES_OUT 56
692 * DMA request numbers for the OMAP2
694 # define OMAP24XX_DMA_NO_DEVICE 0
695 # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */
696 # define OMAP24XX_DMA_EXT_DMAREQ0 2
697 # define OMAP24XX_DMA_EXT_DMAREQ1 3
698 # define OMAP24XX_DMA_GPMC 4
699 # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */
700 # define OMAP24XX_DMA_DSS 6
701 # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */
702 # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */
703 # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */
704 # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */
705 # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */
706 # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */
707 # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */
708 # define OMAP24XX_DMA_EXT_DMAREQ2 14
709 # define OMAP24XX_DMA_EXT_DMAREQ3 15
710 # define OMAP24XX_DMA_EXT_DMAREQ4 16
711 # define OMAP24XX_DMA_EAC_AC_RD 17
712 # define OMAP24XX_DMA_EAC_AC_WR 18
713 # define OMAP24XX_DMA_EAC_MD_UL_RD 19
714 # define OMAP24XX_DMA_EAC_MD_UL_WR 20
715 # define OMAP24XX_DMA_EAC_MD_DL_RD 21
716 # define OMAP24XX_DMA_EAC_MD_DL_WR 22
717 # define OMAP24XX_DMA_EAC_BT_UL_RD 23
718 # define OMAP24XX_DMA_EAC_BT_UL_WR 24
719 # define OMAP24XX_DMA_EAC_BT_DL_RD 25
720 # define OMAP24XX_DMA_EAC_BT_DL_WR 26
721 # define OMAP24XX_DMA_I2C1_TX 27
722 # define OMAP24XX_DMA_I2C1_RX 28
723 # define OMAP24XX_DMA_I2C2_TX 29
724 # define OMAP24XX_DMA_I2C2_RX 30
725 # define OMAP24XX_DMA_MCBSP1_TX 31
726 # define OMAP24XX_DMA_MCBSP1_RX 32
727 # define OMAP24XX_DMA_MCBSP2_TX 33
728 # define OMAP24XX_DMA_MCBSP2_RX 34
729 # define OMAP24XX_DMA_SPI1_TX0 35
730 # define OMAP24XX_DMA_SPI1_RX0 36
731 # define OMAP24XX_DMA_SPI1_TX1 37
732 # define OMAP24XX_DMA_SPI1_RX1 38
733 # define OMAP24XX_DMA_SPI1_TX2 39
734 # define OMAP24XX_DMA_SPI1_RX2 40
735 # define OMAP24XX_DMA_SPI1_TX3 41
736 # define OMAP24XX_DMA_SPI1_RX3 42
737 # define OMAP24XX_DMA_SPI2_TX0 43
738 # define OMAP24XX_DMA_SPI2_RX0 44
739 # define OMAP24XX_DMA_SPI2_TX1 45
740 # define OMAP24XX_DMA_SPI2_RX1 46
742 # define OMAP24XX_DMA_UART1_TX 49
743 # define OMAP24XX_DMA_UART1_RX 50
744 # define OMAP24XX_DMA_UART2_TX 51
745 # define OMAP24XX_DMA_UART2_RX 52
746 # define OMAP24XX_DMA_UART3_TX 53
747 # define OMAP24XX_DMA_UART3_RX 54
748 # define OMAP24XX_DMA_USB_W2FC_TX0 55
749 # define OMAP24XX_DMA_USB_W2FC_RX0 56
750 # define OMAP24XX_DMA_USB_W2FC_TX1 57
751 # define OMAP24XX_DMA_USB_W2FC_RX1 58
752 # define OMAP24XX_DMA_USB_W2FC_TX2 59
753 # define OMAP24XX_DMA_USB_W2FC_RX2 60
754 # define OMAP24XX_DMA_MMC1_TX 61
755 # define OMAP24XX_DMA_MMC1_RX 62
756 # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */
757 # define OMAP24XX_DMA_EXT_DMAREQ5 64
760 * DMA request numbers for the OMAP3
761 * Note that the numbers have to match the values that are
762 * written to CCRi SYNCHRO_CONTROL bits, i.e. actual line
763 * number plus one! Zero is a reserved value (defined as
764 * NO_DEVICE here). Other missing values are reserved.
766 #define OMAP3XXX_DMA_NO_DEVICE 0
768 #define OMAP3XXX_DMA_EXT_DMAREQ0 2
769 #define OMAP3XXX_DMA_EXT_DMAREQ1 3
770 #define OMAP3XXX_DMA_GPMC 4
772 #define OMAP3XXX_DMA_DSS_LINETRIGGER 6
773 #define OMAP3XXX_DMA_EXT_DMAREQ2 7
775 #define OMAP3XXX_DMA_SPI3_TX0 15
776 #define OMAP3XXX_DMA_SPI3_RX0 16
777 #define OMAP3XXX_DMA_MCBSP3_TX 17
778 #define OMAP3XXX_DMA_MCBSP3_RX 18
779 #define OMAP3XXX_DMA_MCBSP4_TX 19
780 #define OMAP3XXX_DMA_MCBSP4_RX 20
781 #define OMAP3XXX_DMA_MCBSP5_TX 21
782 #define OMAP3XXX_DMA_MCBSP5_RX 22
783 #define OMAP3XXX_DMA_SPI3_TX1 23
784 #define OMAP3XXX_DMA_SPI3_RX1 24
785 #define OMAP3XXX_DMA_I2C3_TX 25
786 #define OMAP3XXX_DMA_I2C3_RX 26
787 #define OMAP3XXX_DMA_I2C1_TX 27
788 #define OMAP3XXX_DMA_I2C1_RX 28
789 #define OMAP3XXX_DMA_I2C2_TX 29
790 #define OMAP3XXX_DMA_I2C2_RX 30
791 #define OMAP3XXX_DMA_MCBSP1_TX 31
792 #define OMAP3XXX_DMA_MCBSP1_RX 32
793 #define OMAP3XXX_DMA_MCBSP2_TX 33
794 #define OMAP3XXX_DMA_MCBSP2_RX 34
795 #define OMAP3XXX_DMA_SPI1_TX0 35
796 #define OMAP3XXX_DMA_SPI1_RX0 36
797 #define OMAP3XXX_DMA_SPI1_TX1 37
798 #define OMAP3XXX_DMA_SPI1_RX1 38
799 #define OMAP3XXX_DMA_SPI1_TX2 39
800 #define OMAP3XXX_DMA_SPI1_RX2 40
801 #define OMAP3XXX_DMA_SPI1_TX3 41
802 #define OMAP3XXX_DMA_SPI1_RX3 42
803 #define OMAP3XXX_DMA_SPI2_TX0 43
804 #define OMAP3XXX_DMA_SPI2_RX0 44
805 #define OMAP3XXX_DMA_SPI2_TX1 45
806 #define OMAP3XXX_DMA_SPI2_RX1 46
807 #define OMAP3XXX_DMA_MMC2_TX 47
808 #define OMAP3XXX_DMA_MMC2_RX 48
809 #define OMAP3XXX_DMA_UART1_TX 49
810 #define OMAP3XXX_DMA_UART1_RX 50
811 #define OMAP3XXX_DMA_UART2_TX 51
812 #define OMAP3XXX_DMA_UART2_RX 52
813 #define OMAP3XXX_DMA_UART3_TX 53
814 #define OMAP3XXX_DMA_UART3_RX 54
816 #define OMAP3XXX_DMA_MMC1_TX 61
817 #define OMAP3XXX_DMA_MMC1_RX 62
818 #define OMAP3XXX_DMA_MS 63
819 #define OMAP3XXX_DMA_EXT_DMAREQ3 64
820 #define OMAP3XXX_DMA_AES2_TX 65
821 #define OMAP3XXX_DMA_AES2_RX 66
822 #define OMAP3XXX_DMA_DES2_TX 67
823 #define OMAP3XXX_DMA_DES2_RX 68
824 #define OMAP3XXX_DMA_SHA1MD5_RX 69
825 #define OMAP3XXX_DMA_SPI4_TX0 70
826 #define OMAP3XXX_DMA_SPI4_RX0 71
827 #define OMAP3XXX_DMA_DSS0 72
828 #define OMAP3XXX_DMA_DSS1 73
829 #define OMAP3XXX_DMA_DSS2 74
830 #define OMAP3XXX_DMA_DSS3 75
832 #define OMAP3XXX_DMA_MMC3_TX 77
833 #define OMAP3XXX_DMA_MMC3_RX 78
834 #define OMAP3XXX_DMA_USIM_TX 79
835 #define OMAP3XXX_DMA_USIM_RX 80
839 struct omap_mpu_timer_s;
840 struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
841 qemu_irq irq, omap_clk clk);
843 struct omap_gp_timer_s;
844 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
845 qemu_irq irq, omap_clk fclk, omap_clk iclk);
846 void omap_gp_timer_change_clk(struct omap_gp_timer_s *timer);
848 struct omap_watchdog_timer_s;
849 struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
850 qemu_irq irq, omap_clk clk);
852 struct omap_32khz_timer_s;
853 struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
854 qemu_irq irq, omap_clk clk);
856 void omap_synctimer_init(struct omap_target_agent_s *ta,
857 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
859 struct omap_tipb_bridge_s;
860 struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
861 qemu_irq abort_irq, omap_clk clk);
864 struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
865 qemu_irq irq, omap_clk fclk, omap_clk iclk,
866 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr);
867 struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
868 qemu_irq irq, omap_clk fclk, omap_clk iclk,
869 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr);
870 void omap_uart_reset(struct omap_uart_s *s);
871 void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
874 struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
875 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
877 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
878 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
879 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
882 struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
883 qemu_irq irq, omap_clk clk);
884 qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);
885 void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler);
888 struct omap_gpif_s *omap2_gpio_init(struct omap_mpu_state_s *mpu,
889 struct omap_target_agent_s *ta,
890 qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules);
891 struct omap_gpif_s *omap3_gpif_init(void);
892 void omap3_gpio_init(struct omap_mpu_state_s *mpu,
893 struct omap_gpif_s *s, struct omap_target_agent_s *ta,
894 qemu_irq irq, omap_clk *fclk, omap_clk iclk, int module_index);
895 qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start);
896 void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler);
898 struct uwire_slave_s {
899 uint16_t (*receive)(void *opaque);
900 void (*send)(void *opaque, uint16_t data);
904 struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
905 qemu_irq *irq, qemu_irq dma, omap_clk clk);
906 void omap_uwire_attach(struct omap_uwire_s *s,
907 struct uwire_slave_s *slave, int chipselect);
910 struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
911 qemu_irq *irq, omap_clk clk);
916 /* The CPU can call this if it is generating the clock signal on the
917 * i2s port. The CODEC can ignore it if it is set up as a clock
918 * master and generates its own clock. */
919 void (*set_rate)(void *opaque, int in, int out);
921 void (*tx_swallow)(void *opaque);
938 struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
939 qemu_irq *irq, qemu_irq *dma, omap_clk clk);
940 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave);
943 struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
945 void omap_tap_init(struct omap_target_agent_s *ta,
946 struct omap_mpu_state_s *mpu);
949 struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
950 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
953 struct omap_lcd_panel_s;
954 void omap_lcdc_reset(struct omap_lcd_panel_s *s);
955 struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
956 struct omap_dma_lcd_channel_s *dma,
957 ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
962 void (*write)(void *opaque, int dc, uint16_t value);
963 void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
964 uint16_t (*read)(void *opaque, int dc);
966 typedef void (*omap3_lcd_panel_fn_t)(uint8_t *, const uint8_t *, unsigned int);
967 struct omap3_lcd_panel_s;
969 void omap_dss_reset(struct omap_dss_s *s);
970 struct omap_dss_s *omap_dss_init(struct omap_mpu_state_s *mpu,
971 struct omap_target_agent_s *ta,
972 qemu_irq irq, qemu_irq drq,
973 omap_clk fck1, omap_clk fck2, omap_clk ck54m,
974 omap_clk ick1, omap_clk ick2);
975 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
976 void omap3_lcd_panel_attach(struct omap_dss_s *s, int cs, struct omap3_lcd_panel_s *lcd_panel);
977 void *omap3_lcd_panel_init(void);
981 struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
982 BlockDriverState *bd,
983 qemu_irq irq, qemu_irq dma[], omap_clk clk);
984 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
985 BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
986 omap_clk fclk, omap_clk iclk);
987 void omap_mmc_reset(struct omap_mmc_s *s);
988 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
989 void omap_mmc_enable(struct omap_mmc_s *s, int enable);
993 struct omap3_mmc_s *omap3_mmc_init(struct omap_target_agent_s *ta,
994 qemu_irq irq, qemu_irq dma[],
995 omap_clk fclk, omap_clk iclk);
996 void omap3_mmc_attach(struct omap3_mmc_s *s,
997 BlockDriverState *bd);
1001 struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
1002 qemu_irq irq, qemu_irq *dma, omap_clk clk);
1003 struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
1004 qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);
1005 struct omap_i2c_s *omap3_i2c_init(struct omap_target_agent_s *ta,
1006 qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk,
1008 void omap_i2c_reset(struct omap_i2c_s *s);
1009 i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
1012 struct omap_mcspi_s;
1013 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta,
1014 struct omap_mpu_state_s *mpu,
1015 int chnum, qemu_irq irq, qemu_irq *drq,
1016 omap_clk fclk, omap_clk iclk);
1017 void omap_mcspi_attach(struct omap_mcspi_s *s,
1018 uint32_t (*txrx)(void *opaque, uint32_t, int),
1019 void *opaque, int chipselect);
1020 void omap_mcspi_reset(struct omap_mcspi_s *s);
1023 struct omap3_hsusb_s;
1024 struct omap3_hsusb_s *omap3_hsusb_init(struct omap_target_agent_s *otg_ta,
1025 struct omap_target_agent_s *host_ta,
1026 struct omap_target_agent_s *tll_ta,
1034 int usb_ohci_init_omap(target_phys_addr_t base, uint32_t region_size,
1035 int num_ports, qemu_irq irq);
1038 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
1039 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
1040 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
1041 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
1042 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
1043 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
1044 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
1045 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
1046 # define cpu_is_omap3530(cpu) (cpu->mpu_model == omap3530)
1048 # define cpu_is_omap15xx(cpu) \
1049 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
1050 # define cpu_is_omap16xx(cpu) \
1051 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
1052 # define cpu_is_omap24xx(cpu) \
1053 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
1055 # define cpu_class_omap1(cpu) \
1056 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
1057 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
1058 # define cpu_class_omap3(cpu) \
1059 (cpu_is_omap3430(cpu) || cpu_is_omap3530(cpu))
1061 struct omap_mpu_state_s {
1062 enum omap_mpu_model {
1083 struct omap_dma_port_if_s {
1084 uint32_t (*read[3])(struct omap_mpu_state_s *s,
1085 target_phys_addr_t offset);
1086 void (*write[3])(struct omap_mpu_state_s *s,
1087 target_phys_addr_t offset, uint32_t value);
1088 int (*addr_valid)(struct omap_mpu_state_s *s,
1089 target_phys_addr_t addr);
1090 } port[__omap_dma_port_last];
1092 unsigned long sdram_size;
1093 unsigned long sram_size;
1095 /* MPUI-TIPB peripherals */
1096 struct omap_uart_s *uart[3];
1098 struct omap_gpio_s *gpio;
1100 struct omap_mcbsp_s *mcbsp1;
1101 struct omap_mcbsp_s *mcbsp3;
1103 /* MPU public TIPB peripherals */
1104 struct omap_32khz_timer_s *os_timer;
1106 struct omap_mmc_s *mmc;
1108 struct omap_mpuio_s *mpuio;
1110 struct omap_uwire_s *microwire;
1126 struct omap_i2c_s *i2c[3];
1128 struct omap_rtc_s *rtc;
1130 struct omap_mcbsp_s *mcbsp2;
1132 struct omap_lpg_s *led[2];
1134 /* MPU private TIPB peripherals */
1135 struct omap_intr_handler_s *ih[2];
1137 struct soc_dma_s *dma;
1139 struct omap_mpu_timer_s *timer[3];
1140 struct omap_watchdog_timer_s *wdt;
1142 struct omap_lcd_panel_s *lcd;
1144 uint32_t ulpd_pm_regs[21];
1145 int64_t ulpd_gauge_start;
1147 uint32_t func_mux_ctrl[14];
1148 uint32_t comp_mode_ctrl[1];
1149 uint32_t pull_dwn_ctrl[4];
1150 uint32_t gate_inh_ctrl[1];
1151 uint32_t voltage_ctrl[1];
1152 uint32_t test_dbg_ctrl[1];
1153 uint32_t mod_conf_ctrl[1];
1158 struct omap_tipb_bridge_s *private_tipb;
1159 struct omap_tipb_bridge_s *public_tipb;
1161 uint32_t tcmi_regs[17];
1171 int clocking_scheme;
1173 uint16_t arm_idlect1;
1174 uint16_t arm_idlect2;
1175 uint16_t arm_ewupct;
1176 uint16_t arm_rstct1;
1177 uint16_t arm_rstct2;
1178 uint16_t arm_ckout1;
1180 uint16_t dsp_idlect1;
1181 uint16_t dsp_idlect2;
1182 uint16_t dsp_rstct2;
1185 /* OMAP2-only peripherals */
1186 struct omap_l4_s *l4;
1188 struct omap_gp_timer_s *gptimer[12];
1190 struct omap_synctimer_s {
1193 uint32_t sysconfig; /*OMAP3*/
1196 struct omap_prcm_s *prcm;
1197 struct omap_sdrc_s *sdrc;
1198 struct omap_gpmc_s *gpmc;
1199 struct omap_sysctl_s *sysc;
1201 struct omap_gpif_s *gpif;
1203 struct omap_mcspi_s *mcspi[4];
1205 struct omap_dss_s *dss;
1207 struct omap_eac_s *eac;
1210 struct omap3_prm_s *omap3_prm;
1211 struct omap3_cm_s *omap3_cm;
1212 struct omap3_wdt_s *omap3_mpu_wdt;
1213 struct omap_l3_s *omap3_l3;
1214 struct omap3_scm_s *omap3_scm;
1215 struct omap3_sms_s *omap3_sms;
1216 struct omap3_mmc_s *omap3_mmc[3];
1217 struct omap3_hsusb_s *omap3_usb;
1220 struct omap_target_agent_s {
1221 struct omap_l4_s *bus;
1223 struct omap_l4_region_s *start;
1224 target_phys_addr_t base;
1227 uint32_t control_h; /* OMAP3 */
1232 target_phys_addr_t base;
1234 struct omap_target_agent_s ta[0];
1237 struct omap_l4_region_s {
1238 target_phys_addr_t offset;
1243 struct omap_l4_agent_info_s {
1251 struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
1255 struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
1259 struct omap_mpu_state_s *omap3530_mpu_init(unsigned long sdram_size,
1260 CharDriverState *chr_uart1,
1261 CharDriverState *chr_uart2,
1262 CharDriverState *chr_uart3);
1263 void omap3_set_mem_type(struct omap_mpu_state_s *s, int bootfrom);
1266 void omap3_boot_rom_emu(struct omap_mpu_state_s *s);
1268 # if TARGET_PHYS_ADDR_BITS == 32
1269 # define OMAP_FMT_plx "0x%08x"
1270 # elif TARGET_PHYS_ADDR_BITS == 64
1271 # define OMAP_FMT_plx "0x%08" PRIx64
1273 # error TARGET_PHYS_ADDR_BITS undefined
1276 uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
1277 void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
1279 uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
1280 void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
1282 uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
1283 void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
1286 void omap_mpu_wakeup(void *opaque, int irq, int req);
1288 # define OMAP_BAD_REG(paddr) \
1289 fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \
1290 __FUNCTION__, paddr)
1291 # define OMAP_BAD_REGV(paddr, value) \
1292 fprintf(stderr, "%s: Bad register " OMAP_FMT_plx " (value 0x%08x)\n", \
1293 __FUNCTION__, paddr, value)
1294 # define OMAP_RO_REG(paddr) \
1295 fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \
1296 __FUNCTION__, paddr)
1297 # define OMAP_RO_REGV(paddr, value) \
1298 fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx " (value 0x%08x)\n", \
1299 __FUNCTION__, paddr, value)
1301 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
1302 (Board-specifc tags are not here) */
1303 #define OMAP_TAG_CLOCK 0x4f01
1304 #define OMAP_TAG_MMC 0x4f02
1305 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03
1306 #define OMAP_TAG_USB 0x4f04
1307 #define OMAP_TAG_LCD 0x4f05
1308 #define OMAP_TAG_GPIO_SWITCH 0x4f06
1309 #define OMAP_TAG_UART 0x4f07
1310 #define OMAP_TAG_FBMEM 0x4f08
1311 #define OMAP_TAG_STI_CONSOLE 0x4f09
1312 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a
1313 #define OMAP_TAG_PARTITION 0x4f0b
1314 #define OMAP_TAG_TEA5761 0x4f10
1315 #define OMAP_TAG_TMP105 0x4f11
1316 #define OMAP_TAG_BOOT_REASON 0x4f80
1317 #define OMAP_TAG_FLASH_PART_STR 0x4f81
1318 #define OMAP_TAG_VERSION_STR 0x4f82
1321 OMAP_GPIOSW_TYPE_COVER = 0 << 4,
1322 OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
1323 OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4,
1326 #define OMAP_GPIOSW_INVERTED 0x0001
1327 #define OMAP_GPIOSW_OUTPUT 0x0002
1329 # define TCMI_VERBOSE 1
1330 //# define MEM_VERBOSE 1
1332 # ifdef TCMI_VERBOSE
1333 # define OMAP_8B_REG(paddr) \
1334 fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \
1335 __FUNCTION__, paddr)
1336 # define OMAP_16B_REG(paddr) \
1337 fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \
1338 __FUNCTION__, paddr)
1339 # define OMAP_32B_REG(paddr) \
1340 fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \
1341 __FUNCTION__, paddr)
1343 # define OMAP_8B_REG(paddr)
1344 # define OMAP_16B_REG(paddr)
1345 # define OMAP_32B_REG(paddr)
1348 # define OMAP_MPUI_REG_MASK 0x000007ff
1352 CPUReadMemoryFunc **mem_read;
1353 CPUWriteMemoryFunc **mem_write;
1358 static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
1360 struct io_fn *s = opaque;
1364 ret = s->mem_read[0](s->opaque, addr);
1367 fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
1370 static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
1372 struct io_fn *s = opaque;
1376 ret = s->mem_read[1](s->opaque, addr);
1379 fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
1382 static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
1384 struct io_fn *s = opaque;
1388 ret = s->mem_read[2](s->opaque, addr);
1391 fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
1394 static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
1396 struct io_fn *s = opaque;
1399 fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
1401 s->mem_write[0](s->opaque, addr, value);
1404 static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
1406 struct io_fn *s = opaque;
1409 fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
1411 s->mem_write[1](s->opaque, addr, value);
1414 static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
1416 struct io_fn *s = opaque;
1419 fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
1421 s->mem_write[2](s->opaque, addr, value);
1425 static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };
1426 static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };
1428 inline static int debug_register_io_memory(int io_index,
1429 CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write,
1432 struct io_fn *s = qemu_malloc(sizeof(struct io_fn));
1434 s->mem_read = mem_read;
1435 s->mem_write = mem_write;
1438 return cpu_register_io_memory(io_index, io_readfn, io_writefn, s);
1440 # define cpu_register_io_memory debug_register_io_memory
1443 /* Define when we want to reduce the number of IO regions registered. */
1444 /*# define L4_MUX_HACK*/
1447 # undef l4_register_io_memory
1448 int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read,
1449 CPUWriteMemoryFunc **mem_write, void *opaque);
1452 #endif /* hw_omap_h */