2 * Texas Instruments OMAP processors.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 # define hw_omap_h "omap.h"
23 # define OMAP_EMIFS_BASE 0x00000000
24 # define OMAP2_Q0_BASE 0x00000000
25 # define OMAP_CS0_BASE 0x00000000
26 # define OMAP_CS1_BASE 0x04000000
27 # define OMAP_CS2_BASE 0x08000000
28 # define OMAP_CS3_BASE 0x0c000000
29 # define OMAP_EMIFF_BASE 0x10000000
30 # define OMAP_IMIF_BASE 0x20000000
31 # define OMAP_LOCALBUS_BASE 0x30000000
32 # define OMAP2_Q1_BASE 0x40000000
33 # define OMAP2_L4_BASE 0x48000000
34 # define OMAP2_SRAM_BASE 0x40200000
35 # define OMAP2_L3_BASE 0x68000000
36 # define OMAP2_Q2_BASE 0x80000000
37 # define OMAP2_Q3_BASE 0xc0000000
38 # define OMAP3_Q1_BASE 0x40000000
39 # define OMAP3_L4_BASE 0x48000000
40 # define OMAP3_SRAM_BASE 0x40200000
41 # define OMAP3_L3_BASE 0x68000000
42 # define OMAP3_Q2_BASE 0x80000000
43 # define OMAP3_Q3_BASE 0xc0000000
44 # define OMAP_MPUI_BASE 0xe1000000
46 # define OMAP730_SRAM_SIZE 0x00032000
47 # define OMAP15XX_SRAM_SIZE 0x00030000
48 # define OMAP16XX_SRAM_SIZE 0x00004000
49 # define OMAP1611_SRAM_SIZE 0x0003e800
50 # define OMAP242X_SRAM_SIZE 0x000a0000
51 # define OMAP243X_SRAM_SIZE 0x00010000
52 # define OMAP3XXX_SRAM_SIZE 0x00010000
53 # define OMAP3XXX_BOOTROM_SIZE 0x00008000
54 # define OMAP_CS0_SIZE 0x04000000
55 # define OMAP_CS1_SIZE 0x04000000
56 # define OMAP_CS2_SIZE 0x04000000
57 # define OMAP_CS3_SIZE 0x04000000
60 struct omap_mpu_state_s;
61 typedef struct clk *omap_clk;
62 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
63 void omap_clk_init(struct omap_mpu_state_s *mpu);
64 void omap_clk_adduser(struct clk *clk, qemu_irq user);
65 void omap_clk_get(omap_clk clk);
66 void omap_clk_put(omap_clk clk);
67 void omap_clk_onoff(omap_clk clk, int on);
68 void omap_clk_canidle(omap_clk clk, int can);
69 void omap_clk_setrate(omap_clk clk, int divide, int multiply);
70 int64_t omap_clk_getrate(omap_clk clk);
71 void omap_clk_reparent(omap_clk clk, omap_clk parent);
76 struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num);
78 struct omap_target_agent_s;
79 struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs);
80 target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
82 # define l4_register_io_memory cpu_register_io_memory
84 struct omap_intr_handler_s;
85 struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
86 unsigned long size, unsigned char nbanks, qemu_irq **pins,
87 qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);
88 struct omap_intr_handler_s *omap2_inth_init(struct omap_mpu_state_s *mpu,
89 target_phys_addr_t base,
90 int size, int nbanks, qemu_irq **pins,
91 qemu_irq parent_irq, qemu_irq parent_fiq,
92 omap_clk fclk, omap_clk iclk);
93 void omap_inth_reset(struct omap_intr_handler_s *s);
96 struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
97 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
98 struct omap_mpu_state_s *mpu);
101 struct omap3_prm_s *omap3_prm_init(struct omap_target_agent_s *ta,
102 qemu_irq mpu_int, qemu_irq iva_int,
103 struct omap_mpu_state_s *mpu);
106 struct omap3_cm_s *omap3_cm_init(struct omap_target_agent_s *ta,
107 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
108 struct omap_mpu_state_s *mpu);
110 struct omap_sysctl_s;
111 struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
112 omap_clk iclk, struct omap_mpu_state_s *mpu);
115 struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
116 void omap_sdrc_write_mcfg(struct omap_sdrc_s *s, uint32_t value, uint32_t cs);
120 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
121 target_phys_addr_t base, qemu_irq irq);
122 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
123 void (*base_upd)(void *opaque, target_phys_addr_t new),
124 void (*unmap)(void *opaque), void *opaque,
125 struct nand_flash_s *nand_s);
128 * Common IRQ numbers for level 1 interrupt handler
129 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
131 # define OMAP_INT_CAMERA 1
132 # define OMAP_INT_FIQ 3
133 # define OMAP_INT_RTDX 6
134 # define OMAP_INT_DSP_MMU_ABORT 7
135 # define OMAP_INT_HOST 8
136 # define OMAP_INT_ABORT 9
137 # define OMAP_INT_BRIDGE_PRIV 13
138 # define OMAP_INT_GPIO_BANK1 14
139 # define OMAP_INT_UART3 15
140 # define OMAP_INT_TIMER3 16
141 # define OMAP_INT_DMA_CH0_6 19
142 # define OMAP_INT_DMA_CH1_7 20
143 # define OMAP_INT_DMA_CH2_8 21
144 # define OMAP_INT_DMA_CH3 22
145 # define OMAP_INT_DMA_CH4 23
146 # define OMAP_INT_DMA_CH5 24
147 # define OMAP_INT_DMA_LCD 25
148 # define OMAP_INT_TIMER1 26
149 # define OMAP_INT_WD_TIMER 27
150 # define OMAP_INT_BRIDGE_PUB 28
151 # define OMAP_INT_TIMER2 30
152 # define OMAP_INT_LCD_CTRL 31
155 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
157 # define OMAP_INT_15XX_IH2_IRQ 0
158 # define OMAP_INT_15XX_LB_MMU 17
159 # define OMAP_INT_15XX_LOCAL_BUS 29
162 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
164 # define OMAP_INT_1510_SPI_TX 4
165 # define OMAP_INT_1510_SPI_RX 5
166 # define OMAP_INT_1510_DSP_MAILBOX1 10
167 # define OMAP_INT_1510_DSP_MAILBOX2 11
170 * OMAP-310 specific IRQ numbers for level 1 interrupt handler
172 # define OMAP_INT_310_McBSP2_TX 4
173 # define OMAP_INT_310_McBSP2_RX 5
174 # define OMAP_INT_310_HSB_MAILBOX1 12
175 # define OMAP_INT_310_HSAB_MMU 18
178 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
180 # define OMAP_INT_1610_IH2_IRQ 0
181 # define OMAP_INT_1610_IH2_FIQ 2
182 # define OMAP_INT_1610_McBSP2_TX 4
183 # define OMAP_INT_1610_McBSP2_RX 5
184 # define OMAP_INT_1610_DSP_MAILBOX1 10
185 # define OMAP_INT_1610_DSP_MAILBOX2 11
186 # define OMAP_INT_1610_LCD_LINE 12
187 # define OMAP_INT_1610_GPTIMER1 17
188 # define OMAP_INT_1610_GPTIMER2 18
189 # define OMAP_INT_1610_SSR_FIFO_0 29
192 * OMAP-730 specific IRQ numbers for level 1 interrupt handler
194 # define OMAP_INT_730_IH2_FIQ 0
195 # define OMAP_INT_730_IH2_IRQ 1
196 # define OMAP_INT_730_USB_NON_ISO 2
197 # define OMAP_INT_730_USB_ISO 3
198 # define OMAP_INT_730_ICR 4
199 # define OMAP_INT_730_EAC 5
200 # define OMAP_INT_730_GPIO_BANK1 6
201 # define OMAP_INT_730_GPIO_BANK2 7
202 # define OMAP_INT_730_GPIO_BANK3 8
203 # define OMAP_INT_730_McBSP2TX 10
204 # define OMAP_INT_730_McBSP2RX 11
205 # define OMAP_INT_730_McBSP2RX_OVF 12
206 # define OMAP_INT_730_LCD_LINE 14
207 # define OMAP_INT_730_GSM_PROTECT 15
208 # define OMAP_INT_730_TIMER3 16
209 # define OMAP_INT_730_GPIO_BANK5 17
210 # define OMAP_INT_730_GPIO_BANK6 18
211 # define OMAP_INT_730_SPGIO_WR 29
214 * Common IRQ numbers for level 2 interrupt handler
216 # define OMAP_INT_KEYBOARD 1
217 # define OMAP_INT_uWireTX 2
218 # define OMAP_INT_uWireRX 3
219 # define OMAP_INT_I2C 4
220 # define OMAP_INT_MPUIO 5
221 # define OMAP_INT_USB_HHC_1 6
222 # define OMAP_INT_McBSP3TX 10
223 # define OMAP_INT_McBSP3RX 11
224 # define OMAP_INT_McBSP1TX 12
225 # define OMAP_INT_McBSP1RX 13
226 # define OMAP_INT_UART1 14
227 # define OMAP_INT_UART2 15
228 # define OMAP_INT_USB_W2FC 20
229 # define OMAP_INT_1WIRE 21
230 # define OMAP_INT_OS_TIMER 22
231 # define OMAP_INT_OQN 23
232 # define OMAP_INT_GAUGE_32K 24
233 # define OMAP_INT_RTC_TIMER 25
234 # define OMAP_INT_RTC_ALARM 26
235 # define OMAP_INT_DSP_MMU 28
238 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
240 # define OMAP_INT_1510_BT_MCSI1TX 16
241 # define OMAP_INT_1510_BT_MCSI1RX 17
242 # define OMAP_INT_1510_SoSSI_MATCH 19
243 # define OMAP_INT_1510_MEM_STICK 27
244 # define OMAP_INT_1510_COM_SPI_RO 31
247 * OMAP-310 specific IRQ numbers for level 2 interrupt handler
249 # define OMAP_INT_310_FAC 0
250 # define OMAP_INT_310_USB_HHC_2 7
251 # define OMAP_INT_310_MCSI1_FE 16
252 # define OMAP_INT_310_MCSI2_FE 17
253 # define OMAP_INT_310_USB_W2FC_ISO 29
254 # define OMAP_INT_310_USB_W2FC_NON_ISO 30
255 # define OMAP_INT_310_McBSP2RX_OF 31
258 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
260 # define OMAP_INT_1610_FAC 0
261 # define OMAP_INT_1610_USB_HHC_2 7
262 # define OMAP_INT_1610_USB_OTG 8
263 # define OMAP_INT_1610_SoSSI 9
264 # define OMAP_INT_1610_BT_MCSI1TX 16
265 # define OMAP_INT_1610_BT_MCSI1RX 17
266 # define OMAP_INT_1610_SoSSI_MATCH 19
267 # define OMAP_INT_1610_MEM_STICK 27
268 # define OMAP_INT_1610_McBSP2RX_OF 31
269 # define OMAP_INT_1610_STI 32
270 # define OMAP_INT_1610_STI_WAKEUP 33
271 # define OMAP_INT_1610_GPTIMER3 34
272 # define OMAP_INT_1610_GPTIMER4 35
273 # define OMAP_INT_1610_GPTIMER5 36
274 # define OMAP_INT_1610_GPTIMER6 37
275 # define OMAP_INT_1610_GPTIMER7 38
276 # define OMAP_INT_1610_GPTIMER8 39
277 # define OMAP_INT_1610_GPIO_BANK2 40
278 # define OMAP_INT_1610_GPIO_BANK3 41
279 # define OMAP_INT_1610_MMC2 42
280 # define OMAP_INT_1610_CF 43
281 # define OMAP_INT_1610_WAKE_UP_REQ 46
282 # define OMAP_INT_1610_GPIO_BANK4 48
283 # define OMAP_INT_1610_SPI 49
284 # define OMAP_INT_1610_DMA_CH6 53
285 # define OMAP_INT_1610_DMA_CH7 54
286 # define OMAP_INT_1610_DMA_CH8 55
287 # define OMAP_INT_1610_DMA_CH9 56
288 # define OMAP_INT_1610_DMA_CH10 57
289 # define OMAP_INT_1610_DMA_CH11 58
290 # define OMAP_INT_1610_DMA_CH12 59
291 # define OMAP_INT_1610_DMA_CH13 60
292 # define OMAP_INT_1610_DMA_CH14 61
293 # define OMAP_INT_1610_DMA_CH15 62
294 # define OMAP_INT_1610_NAND 63
297 * OMAP-730 specific IRQ numbers for level 2 interrupt handler
299 # define OMAP_INT_730_HW_ERRORS 0
300 # define OMAP_INT_730_NFIQ_PWR_FAIL 1
301 # define OMAP_INT_730_CFCD 2
302 # define OMAP_INT_730_CFIREQ 3
303 # define OMAP_INT_730_I2C 4
304 # define OMAP_INT_730_PCC 5
305 # define OMAP_INT_730_MPU_EXT_NIRQ 6
306 # define OMAP_INT_730_SPI_100K_1 7
307 # define OMAP_INT_730_SYREN_SPI 8
308 # define OMAP_INT_730_VLYNQ 9
309 # define OMAP_INT_730_GPIO_BANK4 10
310 # define OMAP_INT_730_McBSP1TX 11
311 # define OMAP_INT_730_McBSP1RX 12
312 # define OMAP_INT_730_McBSP1RX_OF 13
313 # define OMAP_INT_730_UART_MODEM_IRDA_2 14
314 # define OMAP_INT_730_UART_MODEM_1 15
315 # define OMAP_INT_730_MCSI 16
316 # define OMAP_INT_730_uWireTX 17
317 # define OMAP_INT_730_uWireRX 18
318 # define OMAP_INT_730_SMC_CD 19
319 # define OMAP_INT_730_SMC_IREQ 20
320 # define OMAP_INT_730_HDQ_1WIRE 21
321 # define OMAP_INT_730_TIMER32K 22
322 # define OMAP_INT_730_MMC_SDIO 23
323 # define OMAP_INT_730_UPLD 24
324 # define OMAP_INT_730_USB_HHC_1 27
325 # define OMAP_INT_730_USB_HHC_2 28
326 # define OMAP_INT_730_USB_GENI 29
327 # define OMAP_INT_730_USB_OTG 30
328 # define OMAP_INT_730_CAMERA_IF 31
329 # define OMAP_INT_730_RNG 32
330 # define OMAP_INT_730_DUAL_MODE_TIMER 33
331 # define OMAP_INT_730_DBB_RF_EN 34
332 # define OMAP_INT_730_MPUIO_KEYPAD 35
333 # define OMAP_INT_730_SHA1_MD5 36
334 # define OMAP_INT_730_SPI_100K_2 37
335 # define OMAP_INT_730_RNG_IDLE 38
336 # define OMAP_INT_730_MPUIO 39
337 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
338 # define OMAP_INT_730_LLPC_OE_FALLING 41
339 # define OMAP_INT_730_LLPC_OE_RISING 42
340 # define OMAP_INT_730_LLPC_VSYNC 43
341 # define OMAP_INT_730_WAKE_UP_REQ 46
342 # define OMAP_INT_730_DMA_CH6 53
343 # define OMAP_INT_730_DMA_CH7 54
344 # define OMAP_INT_730_DMA_CH8 55
345 # define OMAP_INT_730_DMA_CH9 56
346 # define OMAP_INT_730_DMA_CH10 57
347 # define OMAP_INT_730_DMA_CH11 58
348 # define OMAP_INT_730_DMA_CH12 59
349 # define OMAP_INT_730_DMA_CH13 60
350 # define OMAP_INT_730_DMA_CH14 61
351 # define OMAP_INT_730_DMA_CH15 62
352 # define OMAP_INT_730_NAND 63
355 * OMAP-24xx common IRQ numbers
357 # define OMAP_INT_24XX_STI 4
358 # define OMAP_INT_24XX_SYS_NIRQ 7
359 # define OMAP_INT_24XX_L3_IRQ 10
360 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11
361 # define OMAP_INT_24XX_SDMA_IRQ0 12
362 # define OMAP_INT_24XX_SDMA_IRQ1 13
363 # define OMAP_INT_24XX_SDMA_IRQ2 14
364 # define OMAP_INT_24XX_SDMA_IRQ3 15
365 # define OMAP_INT_243X_MCBSP2_IRQ 16
366 # define OMAP_INT_243X_MCBSP3_IRQ 17
367 # define OMAP_INT_243X_MCBSP4_IRQ 18
368 # define OMAP_INT_243X_MCBSP5_IRQ 19
369 # define OMAP_INT_24XX_GPMC_IRQ 20
370 # define OMAP_INT_24XX_GUFFAW_IRQ 21
371 # define OMAP_INT_24XX_IVA_IRQ 22
372 # define OMAP_INT_24XX_EAC_IRQ 23
373 # define OMAP_INT_24XX_CAM_IRQ 24
374 # define OMAP_INT_24XX_DSS_IRQ 25
375 # define OMAP_INT_24XX_MAIL_U0_MPU 26
376 # define OMAP_INT_24XX_DSP_UMA 27
377 # define OMAP_INT_24XX_DSP_MMU 28
378 # define OMAP_INT_24XX_GPIO_BANK1 29
379 # define OMAP_INT_24XX_GPIO_BANK2 30
380 # define OMAP_INT_24XX_GPIO_BANK3 31
381 # define OMAP_INT_24XX_GPIO_BANK4 32
382 # define OMAP_INT_243X_GPIO_BANK5 33
383 # define OMAP_INT_24XX_MAIL_U3_MPU 34
384 # define OMAP_INT_24XX_WDT3 35
385 # define OMAP_INT_24XX_WDT4 36
386 # define OMAP_INT_24XX_GPTIMER1 37
387 # define OMAP_INT_24XX_GPTIMER2 38
388 # define OMAP_INT_24XX_GPTIMER3 39
389 # define OMAP_INT_24XX_GPTIMER4 40
390 # define OMAP_INT_24XX_GPTIMER5 41
391 # define OMAP_INT_24XX_GPTIMER6 42
392 # define OMAP_INT_24XX_GPTIMER7 43
393 # define OMAP_INT_24XX_GPTIMER8 44
394 # define OMAP_INT_24XX_GPTIMER9 45
395 # define OMAP_INT_24XX_GPTIMER10 46
396 # define OMAP_INT_24XX_GPTIMER11 47
397 # define OMAP_INT_24XX_GPTIMER12 48
398 # define OMAP_INT_24XX_PKA_IRQ 50
399 # define OMAP_INT_24XX_SHA1MD5_IRQ 51
400 # define OMAP_INT_24XX_RNG_IRQ 52
401 # define OMAP_INT_24XX_MG_IRQ 53
402 # define OMAP_INT_24XX_I2C1_IRQ 56
403 # define OMAP_INT_24XX_I2C2_IRQ 57
404 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59
405 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60
406 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62
407 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63
408 # define OMAP_INT_243X_MCBSP1_IRQ 64
409 # define OMAP_INT_24XX_MCSPI1_IRQ 65
410 # define OMAP_INT_24XX_MCSPI2_IRQ 66
411 # define OMAP_INT_24XX_SSI1_IRQ0 67
412 # define OMAP_INT_24XX_SSI1_IRQ1 68
413 # define OMAP_INT_24XX_SSI2_IRQ0 69
414 # define OMAP_INT_24XX_SSI2_IRQ1 70
415 # define OMAP_INT_24XX_SSI_GDD_IRQ 71
416 # define OMAP_INT_24XX_UART1_IRQ 72
417 # define OMAP_INT_24XX_UART2_IRQ 73
418 # define OMAP_INT_24XX_UART3_IRQ 74
419 # define OMAP_INT_24XX_USB_IRQ_GEN 75
420 # define OMAP_INT_24XX_USB_IRQ_NISO 76
421 # define OMAP_INT_24XX_USB_IRQ_ISO 77
422 # define OMAP_INT_24XX_USB_IRQ_HGEN 78
423 # define OMAP_INT_24XX_USB_IRQ_HSOF 79
424 # define OMAP_INT_24XX_USB_IRQ_OTG 80
425 # define OMAP_INT_24XX_VLYNQ_IRQ 81
426 # define OMAP_INT_24XX_MMC_IRQ 83
427 # define OMAP_INT_24XX_MS_IRQ 84
428 # define OMAP_INT_24XX_FAC_IRQ 85
429 # define OMAP_INT_24XX_MCSPI3_IRQ 91
430 # define OMAP_INT_243X_HS_USB_MC 92
431 # define OMAP_INT_243X_HS_USB_DMA 93
432 # define OMAP_INT_243X_CARKIT 94
433 # define OMAP_INT_34XX_GPTIMER12 95
436 * OMAP-3XXX common IRQ numbers
438 #define OMAP_INT_3XXX_EMUINT 0 /* MPU emulation */
439 #define OMAP_INT_3XXX_COMMTX 1 /* MPU emulation */
440 #define OMAP_INT_3XXX_COMMRX 2 /* MPU emulation */
441 #define OMAP_INT_3XXX_BENCH 3 /* MPU emulation */
442 #define OMAP_INT_3XXX_MCBSP2_ST_IRQ 4 /* Sidetone MCBSP2 overflow */
443 #define OMAP_INT_3XXX_MCBSP3_ST_IRQ 5 /* Sidetone MCBSP3 overflow */
444 /* IRQ6 is reserved */
445 #define OMAP_INT_3XXX_SYS_NIRQ 7 /* External source (active low) */
446 /* IRQ8 is reserved */
447 #define OMAP_INT_3XXX_SMX_DBG_IRQ 9 /* L3 interconnect error for debug */
448 #define OMAP_INT_3XXX_SMX_APP_IRQ 10 /* L3 interconnect error for application */
449 #define OMAP_INT_3XXX_PRCM_MPU_IRQ 11 /* PRCM module IRQ */
450 #define OMAP_INT_3XXX_SDMA_IRQ0 12 /* System DMA request 0 */
451 #define OMAP_INT_3XXX_SDMA_IRQ1 13 /* System DMA request 1 */
452 #define OMAP_INT_3XXX_SDMA_IRQ2 14 /* System DMA request 2 */
453 #define OMAP_INT_3XXX_SDMA_IRQ3 15 /* System DMA request 3 */
454 #define OMAP_INT_3XXX_MCBSP1_IRQ 16 /* MCBSP module 1 IRQ */
455 #define OMAP_INT_3XXX_MCBSP2_IRQ 17 /* MCBSP module 2 IRQ */
456 /* IRQ18 is reserved */
457 /* IRQ19 is reserved */
458 #define OMAP_INT_3XXX_GPMC_IRQ 20 /* General-purpose memory controller module */
459 #define OMAP_INT_3XXX_SGX_IRQ 21 /* 2D/3D graphics module */
460 #define OMAP_INT_3XXX_MCBSP3_IRQ 22 /* MCBSP module 3 */
461 #define OMAP_INT_3XXX_MCBSP4_IRQ 23 /* MCBSP module 4 */
462 #define OMAP_INT_3XXX_CAM_IRQ0 24 /* Camera interface request 0 */
463 #define OMAP_INT_3XXX_DSS_IRQ 25 /* Display subsystem module */
464 #define OMAP_INT_3XXX_MAIL_U0_MPU 26 /* Mailbox user 0 request */
465 #define OMAP_INT_3XXX_MCBSP5_IRQ 27 /* MCBSP module 5 */
466 #define OMAP_INT_3XXX_IVA2_MMU_IRQ 28 /* IVA2 MMU */
467 #define OMAP_INT_3XXX_GPIO1_MPU_IRQ 29 /* GPIO module 1 */
468 #define OMAP_INT_3XXX_GPIO2_MPU_IRQ 30 /* GPIO module 2 */
469 #define OMAP_INT_3XXX_GPIO3_MPU_IRQ 31 /* GPIO module 3 */
470 #define OMAP_INT_3XXX_GPIO4_MPU_IRQ 32 /* GPIO module 4 */
471 #define OMAP_INT_3XXX_GPIO5_MPU_IRQ 33 /* GPIO module 5 */
472 #define OMAP_INT_3XXX_GPIO6_MPU_IRQ 34 /* GPIO module 6 */
473 /* IRQ35 is reserved */
474 #define OMAP_INT_3XXX_WDT3_IRQ 36 /* Watchdog timer module 3 overflow */
475 #define OMAP_INT_3XXX_GPT1_IRQ 37 /* General-purpose timer module 1 */
476 #define OMAP_INT_3XXX_GPT2_IRQ 38 /* General-purpose timer module 2 */
477 #define OMAP_INT_3XXX_GPT3_IRQ 39 /* General-purpose timer module 3 */
478 #define OMAP_INT_3XXX_GPT4_IRQ 40 /* General-purpose timer module 4 */
479 #define OMAP_INT_3XXX_GPT5_IRQ 41 /* General-purpose timer module 5 */
480 #define OMAP_INT_3XXX_GPT6_IRQ 42 /* General-purpose timer module 6 */
481 #define OMAP_INT_3XXX_GPT7_IRQ 43 /* General-purpose timer module 7 */
482 #define OMAP_INT_3XXX_GPT8_IRQ 44 /* General-purpose timer module 8 */
483 #define OMAP_INT_3XXX_GPT9_IRQ 45 /* General-purpose timer module 9 */
484 #define OMAP_INT_3XXX_GPT10_IRQ 46 /* General-purpose timer module 10 */
485 #define OMAP_INT_3XXX_GPT11_IRQ 47 /* General-purpose timer module 11 */
486 #define OMAP_INT_3XXX_SPI4_IRQ 48 /* MCSPI module 4 */
487 /* IRQ49 is reserved */
488 /* IRQ50 is reserved */
489 /* IRQ51 is reserved */
490 /* IRQ52 is reserved */
491 #define OMAP_INT_3XXX_MG_IRQ 53
492 #define OMAP_INT_3XXX_MCBSP4_IRQ_TX 54 /* MCBSP module 4 transmit */
493 #define OMAP_INT_3XXX_MCBSP4_IRQ_RX 55 /* MCBSP module 4 receive */
494 #define OMAP_INT_3XXX_I2C1_IRQ 56 /* I2C module 1 */
495 #define OMAP_INT_3XXX_I2C2_IRQ 57 /* I2C module 2 */
496 #define OMAP_INT_3XXX_HDQ_IRQ 58 /* HDQ/1-Wire */
497 #define OMAP_INT_3XXX_MCBSP1_IRQ_TX 59 /* MCBSP module 1 transmit */
498 #define OMAP_INT_3XXX_MCBSP1_IRQ_RX 60 /* MCBSP module 1 receive */
499 #define OMAP_INT_3XXX_I2C3_IRQ 61 /* I2C module 3 */
500 #define OMAP_INT_3XXX_MCBSP2_IRQ_TX 62 /* MCBSP module 2 transmit */
501 #define OMAP_INT_3XXX_MCBSP2_IRQ_RX 63 /* MCBSP module 2 receive */
502 /* IRQ64 is reserved */
503 #define OMAP_INT_3XXX_MCSPI1_IRQ 65 /* MCSPI module 1 */
504 #define OMAP_INT_3XXX_MCSPI2_IRQ 66 /* MCSPI module 2 */
505 /* IRQ67 is reserved */
506 /* IRQ68 is reserved */
507 /* IRQ69 is reserved */
508 /* IRQ70 is reserved */
509 /* IRQ71 is reserved */
510 #define OMAP_INT_3XXX_UART1_IRQ 72 /* UART module 1 */
511 #define OMAP_INT_3XXX_UART2_IRQ 73 /* UART module 2 */
512 #define OMAP_INT_3XXX_UART3_IRQ 74 /* UART module 3 (also infrared)*/
513 #define OMAP_INT_3XXX_PBIAS_IRQ 75 /* Merged interrupt for PBIASlite1 and 2 */
514 #define OMAP_INT_3XXX_OHCI_IRQ 76 /* OHCI controller HSUSB MP Host interrupt */
515 #define OMAP_INT_3XXX_EHCI_IRQ 77 /* EHCI controller HSUSB MP Host interrupt */
516 #define OMAP_INT_3XXX_TLL_IRQ 78 /* HSUSB MP TLL interrupt */
517 /* IRQ79 is reserved */
518 /* IRQ80 is reserved */
519 #define OMAP_INT_3XXX_MCBSP5_IRQ_TX 81 /* MCBSP module 5 transmit */
520 #define OMAP_INT_3XXX_MCBSP5_IRQ_RX 82 /* MCBSP module 5 receive */
521 #define OMAP_INT_3XXX_MMC1_IRQ 83 /* MMC/SD module 1 */
522 #define OMAP_INT_3XXX_MS_IRQ 84
523 /* IRQ85 is reserved */
524 #define OMAP_INT_3XXX_MMC2_IRQ 86 /* MMC/SD module 2 */
525 #define OMAP_INT_3XXX_MPU_ICR_IRQ 87 /* MPU ICR */
526 #define OMAP_INT_3XXX_D2DFRINT 88 /* 3G coprocessor */
527 #define OMAP_INT_3XXX_MCBSP3_IRQ_TX 89 /* MCBSP module 3 transmit */
528 #define OMAP_INT_3XXX_MCBSP3_IRQ_RX 90 /* MCBSP module 3 receive */
529 #define OMAP_INT_3XXX_MCSPI3_IRQ 91 /* MCSPI module 3 */
530 #define OMAP_INT_3XXX_HSUSB_MC 92 /* High-Speed USB OTG controller */
531 #define OMAP_INT_3XXX_HSUSB_DMA 93 /* High-Speed USB OTG DMA controller */
532 #define OMAP_INT_3XXX_MMC3_IRQ 94 /* MMC/SD module 3 */
533 #define OMAP_INT_3XXX_GPT12_IRQ 95 /* General-purpose timer module 12 */
536 enum omap_dma_model {
544 struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
545 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
546 enum omap_dma_model model);
547 struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
548 struct omap_mpu_state_s *mpu, int fifo,
549 int chans, omap_clk iclk, omap_clk fclk);
550 void omap_dma_reset(struct soc_dma_s *s);
557 /* Only used in OMAP DMA 3.x gigacells */
561 imif, /* omap16xx: ocp_t1 */
563 local, /* omap16xx: ocp_t2 */
565 __omap_dma_port_last,
573 } omap_dma_addressing_t;
575 /* Only used in OMAP DMA 3.x gigacells */
576 struct omap_dma_lcd_channel_s {
577 enum omap_dma_port src;
578 target_phys_addr_t src_f1_top;
579 target_phys_addr_t src_f1_bottom;
580 target_phys_addr_t src_f2_top;
581 target_phys_addr_t src_f2_bottom;
583 /* Used in OMAP DMA 3.2 gigacell */
584 unsigned char brust_f1;
585 unsigned char pack_f1;
586 unsigned char data_type_f1;
587 unsigned char brust_f2;
588 unsigned char pack_f2;
589 unsigned char data_type_f2;
590 unsigned char end_prog;
591 unsigned char repeat;
592 unsigned char auto_init;
593 unsigned char priority;
595 unsigned char running;
597 unsigned char omap_3_1_compatible_disable;
599 unsigned char lch_type;
600 int16_t element_index_f1;
601 int16_t element_index_f2;
602 int32_t frame_index_f1;
603 int32_t frame_index_f2;
604 uint16_t elements_f1;
606 uint16_t elements_f2;
608 omap_dma_addressing_t mode_f1;
609 omap_dma_addressing_t mode_f2;
611 /* Destination port is fixed. */
617 ram_addr_t phys_framebuffer[2];
619 struct omap_mpu_state_s *mpu;
620 } *omap_dma_get_lcdch(struct soc_dma_s *s);
623 * DMA request numbers for OMAP1
624 * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
626 # define OMAP_DMA_NO_DEVICE 0
627 # define OMAP_DMA_MCSI1_TX 1
628 # define OMAP_DMA_MCSI1_RX 2
629 # define OMAP_DMA_I2C_RX 3
630 # define OMAP_DMA_I2C_TX 4
631 # define OMAP_DMA_EXT_NDMA_REQ0 5
632 # define OMAP_DMA_EXT_NDMA_REQ1 6
633 # define OMAP_DMA_UWIRE_TX 7
634 # define OMAP_DMA_MCBSP1_TX 8
635 # define OMAP_DMA_MCBSP1_RX 9
636 # define OMAP_DMA_MCBSP3_TX 10
637 # define OMAP_DMA_MCBSP3_RX 11
638 # define OMAP_DMA_UART1_TX 12
639 # define OMAP_DMA_UART1_RX 13
640 # define OMAP_DMA_UART2_TX 14
641 # define OMAP_DMA_UART2_RX 15
642 # define OMAP_DMA_MCBSP2_TX 16
643 # define OMAP_DMA_MCBSP2_RX 17
644 # define OMAP_DMA_UART3_TX 18
645 # define OMAP_DMA_UART3_RX 19
646 # define OMAP_DMA_CAMERA_IF_RX 20
647 # define OMAP_DMA_MMC_TX 21
648 # define OMAP_DMA_MMC_RX 22
649 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */
650 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
651 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
652 # define OMAP_DMA_USB_W2FC_RX0 26
653 # define OMAP_DMA_USB_W2FC_RX1 27
654 # define OMAP_DMA_USB_W2FC_RX2 28
655 # define OMAP_DMA_USB_W2FC_TX0 29
656 # define OMAP_DMA_USB_W2FC_TX1 30
657 # define OMAP_DMA_USB_W2FC_TX2 31
659 /* These are only for 1610 */
660 # define OMAP_DMA_CRYPTO_DES_IN 32
661 # define OMAP_DMA_SPI_TX 33
662 # define OMAP_DMA_SPI_RX 34
663 # define OMAP_DMA_CRYPTO_HASH 35
664 # define OMAP_DMA_CCP_ATTN 36
665 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
666 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38
667 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39
668 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40
669 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41
670 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42
671 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43
672 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44
673 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45
674 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46
675 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47
676 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48
677 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49
678 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50
679 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51
680 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52
681 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53
682 # define OMAP_DMA_MMC2_TX 54
683 # define OMAP_DMA_MMC2_RX 55
684 # define OMAP_DMA_CRYPTO_DES_OUT 56
687 * DMA request numbers for the OMAP2
689 # define OMAP24XX_DMA_NO_DEVICE 0
690 # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */
691 # define OMAP24XX_DMA_EXT_DMAREQ0 2
692 # define OMAP24XX_DMA_EXT_DMAREQ1 3
693 # define OMAP24XX_DMA_GPMC 4
694 # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */
695 # define OMAP24XX_DMA_DSS 6
696 # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */
697 # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */
698 # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */
699 # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */
700 # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */
701 # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */
702 # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */
703 # define OMAP24XX_DMA_EXT_DMAREQ2 14
704 # define OMAP24XX_DMA_EXT_DMAREQ3 15
705 # define OMAP24XX_DMA_EXT_DMAREQ4 16
706 # define OMAP24XX_DMA_EAC_AC_RD 17
707 # define OMAP24XX_DMA_EAC_AC_WR 18
708 # define OMAP24XX_DMA_EAC_MD_UL_RD 19
709 # define OMAP24XX_DMA_EAC_MD_UL_WR 20
710 # define OMAP24XX_DMA_EAC_MD_DL_RD 21
711 # define OMAP24XX_DMA_EAC_MD_DL_WR 22
712 # define OMAP24XX_DMA_EAC_BT_UL_RD 23
713 # define OMAP24XX_DMA_EAC_BT_UL_WR 24
714 # define OMAP24XX_DMA_EAC_BT_DL_RD 25
715 # define OMAP24XX_DMA_EAC_BT_DL_WR 26
716 # define OMAP24XX_DMA_I2C1_TX 27
717 # define OMAP24XX_DMA_I2C1_RX 28
718 # define OMAP24XX_DMA_I2C2_TX 29
719 # define OMAP24XX_DMA_I2C2_RX 30
720 # define OMAP24XX_DMA_MCBSP1_TX 31
721 # define OMAP24XX_DMA_MCBSP1_RX 32
722 # define OMAP24XX_DMA_MCBSP2_TX 33
723 # define OMAP24XX_DMA_MCBSP2_RX 34
724 # define OMAP24XX_DMA_SPI1_TX0 35
725 # define OMAP24XX_DMA_SPI1_RX0 36
726 # define OMAP24XX_DMA_SPI1_TX1 37
727 # define OMAP24XX_DMA_SPI1_RX1 38
728 # define OMAP24XX_DMA_SPI1_TX2 39
729 # define OMAP24XX_DMA_SPI1_RX2 40
730 # define OMAP24XX_DMA_SPI1_TX3 41
731 # define OMAP24XX_DMA_SPI1_RX3 42
732 # define OMAP24XX_DMA_SPI2_TX0 43
733 # define OMAP24XX_DMA_SPI2_RX0 44
734 # define OMAP24XX_DMA_SPI2_TX1 45
735 # define OMAP24XX_DMA_SPI2_RX1 46
737 # define OMAP24XX_DMA_UART1_TX 49
738 # define OMAP24XX_DMA_UART1_RX 50
739 # define OMAP24XX_DMA_UART2_TX 51
740 # define OMAP24XX_DMA_UART2_RX 52
741 # define OMAP24XX_DMA_UART3_TX 53
742 # define OMAP24XX_DMA_UART3_RX 54
743 # define OMAP24XX_DMA_USB_W2FC_TX0 55
744 # define OMAP24XX_DMA_USB_W2FC_RX0 56
745 # define OMAP24XX_DMA_USB_W2FC_TX1 57
746 # define OMAP24XX_DMA_USB_W2FC_RX1 58
747 # define OMAP24XX_DMA_USB_W2FC_TX2 59
748 # define OMAP24XX_DMA_USB_W2FC_RX2 60
749 # define OMAP24XX_DMA_MMC1_TX 61
750 # define OMAP24XX_DMA_MMC1_RX 62
751 # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */
752 # define OMAP24XX_DMA_EXT_DMAREQ5 64
755 * DMA request numbers for the OMAP3
756 * Note that the numbers have to match the values that are
757 * written to CCRi SYNCHRO_CONTROL bits, i.e. actual line
758 * number plus one! Zero is a reserved value (defined as
759 * NO_DEVICE here). Other missing values are reserved.
761 #define OMAP3XXX_DMA_NO_DEVICE 0
763 #define OMAP3XXX_DMA_EXT_DMAREQ0 2
764 #define OMAP3XXX_DMA_EXT_DMAREQ1 3
765 #define OMAP3XXX_DMA_GPMC 4
767 #define OMAP3XXX_DMA_DSS_LINETRIGGER 6
768 #define OMAP3XXX_DMA_EXT_DMAREQ2 7
770 #define OMAP3XXX_DMA_SPI3_TX0 15
771 #define OMAP3XXX_DMA_SPI3_RX0 16
772 #define OMAP3XXX_DMA_MCBSP3_TX 17
773 #define OMAP3XXX_DMA_MCBSP3_RX 18
774 #define OMAP3XXX_DMA_MCBSP4_TX 19
775 #define OMAP3XXX_DMA_MCBSP4_RX 20
776 #define OMAP3XXX_DMA_MCBSP5_TX 21
777 #define OMAP3XXX_DMA_MCBSP5_RX 22
778 #define OMAP3XXX_DMA_SPI3_TX1 23
779 #define OMAP3XXX_DMA_SPI3_RX1 24
780 #define OMAP3XXX_DMA_I2C3_TX 25
781 #define OMAP3XXX_DMA_I2C3_RX 26
782 #define OMAP3XXX_DMA_I2C1_TX 27
783 #define OMAP3XXX_DMA_I2C1_RX 28
784 #define OMAP3XXX_DMA_I2C2_TX 29
785 #define OMAP3XXX_DMA_I2C2_RX 30
786 #define OMAP3XXX_DMA_MCBSP1_TX 31
787 #define OMAP3XXX_DMA_MCBSP1_RX 32
788 #define OMAP3XXX_DMA_MCBSP2_TX 33
789 #define OMAP3XXX_DMA_MCBSP2_RX 34
790 #define OMAP3XXX_DMA_SPI1_TX0 35
791 #define OMAP3XXX_DMA_SPI1_RX0 36
792 #define OMAP3XXX_DMA_SPI1_TX1 37
793 #define OMAP3XXX_DMA_SPI1_RX1 38
794 #define OMAP3XXX_DMA_SPI1_TX2 39
795 #define OMAP3XXX_DMA_SPI1_RX2 40
796 #define OMAP3XXX_DMA_SPI1_TX3 41
797 #define OMAP3XXX_DMA_SPI1_RX4 42
798 #define OMAP3XXX_DMA_SPI2_TX0 43
799 #define OMAP3XXX_DMA_SPI2_RX0 44
800 #define OMAP3XXX_DMA_SPI2_TX1 45
801 #define OMAP3XXX_DMA_SPI2_RX1 46
802 #define OMAP3XXX_DMA_MMC2_TX 47
803 #define OMAP3XXX_DMA_MMC2_RX 48
804 #define OMAP3XXX_DMA_UART1_TX 49
805 #define OMAP3XXX_DMA_UART1_RX 50
806 #define OMAP3XXX_DMA_UART2_TX 51
807 #define OMAP3XXX_DMA_UART2_RX 52
808 #define OMAP3XXX_DMA_UART3_TX 53
809 #define OMAP3XXX_DMA_UART3_RX 54
811 #define OMAP3XXX_DMA_MMC1_TX 61
812 #define OMAP3XXX_DMA_MMC1_RX 62
813 #define OMAP3XXX_DMA_MS 63
814 #define OMAP3XXX_DMA_EXT_DMAREQ3 64
816 #define OMAP3XXX_DMA_SPI4_TX0 70
817 #define OMAP3XXX_DMA_SPI4_RX0 71
818 #define OMAP3XXX_DMA_DSS0 72
819 #define OMAP3XXX_DMA_DSS1 73
820 #define OMAP3XXX_DMA_DSS2 74
821 #define OMAP3XXX_DMA_DSS3 75
823 #define OMAP3XXX_DMA_MMC3_TX 77
824 #define OMAP3XXX_DMA_MMC3_RX 78
828 struct omap_mpu_timer_s;
829 struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
830 qemu_irq irq, omap_clk clk);
832 struct omap_gp_timer_s;
833 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
834 qemu_irq irq, omap_clk fclk, omap_clk iclk);
835 void omap_gp_timer_change_clk(struct omap_gp_timer_s *timer);
837 struct omap_watchdog_timer_s;
838 struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
839 qemu_irq irq, omap_clk clk);
841 struct omap_32khz_timer_s;
842 struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
843 qemu_irq irq, omap_clk clk);
845 void omap_synctimer_init(struct omap_target_agent_s *ta,
846 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
848 struct omap_tipb_bridge_s;
849 struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
850 qemu_irq abort_irq, omap_clk clk);
853 struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
854 qemu_irq irq, omap_clk fclk, omap_clk iclk,
855 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr);
856 struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
857 qemu_irq irq, omap_clk fclk, omap_clk iclk,
858 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr);
859 void omap_uart_reset(struct omap_uart_s *s);
860 void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
863 struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
864 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
866 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
867 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
868 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
871 struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
872 qemu_irq irq, omap_clk clk);
873 qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);
874 void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler);
877 struct omap_gpif_s *omap2_gpio_init(struct omap_mpu_state_s *mpu,
878 struct omap_target_agent_s *ta,
879 qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules);
880 struct omap_gpif_s *omap3_gpif_init(void);
881 void omap3_gpio_init(struct omap_mpu_state_s *mpu,
882 struct omap_gpif_s *s, struct omap_target_agent_s *ta,
883 qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int module_index);
884 qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start);
885 void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler);
887 struct uwire_slave_s {
888 uint16_t (*receive)(void *opaque);
889 void (*send)(void *opaque, uint16_t data);
893 struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
894 qemu_irq *irq, qemu_irq dma, omap_clk clk);
895 void omap_uwire_attach(struct omap_uwire_s *s,
896 struct uwire_slave_s *slave, int chipselect);
899 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
900 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
901 void omap_mcspi_attach(struct omap_mcspi_s *s,
902 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
906 struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
907 qemu_irq *irq, omap_clk clk);
912 /* The CPU can call this if it is generating the clock signal on the
913 * i2s port. The CODEC can ignore it if it is set up as a clock
914 * master and generates its own clock. */
915 void (*set_rate)(void *opaque, int in, int out);
917 void (*tx_swallow)(void *opaque);
934 struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
935 qemu_irq *irq, qemu_irq *dma, omap_clk clk);
936 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave);
939 struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
941 void omap_tap_init(struct omap_target_agent_s *ta,
942 struct omap_mpu_state_s *mpu);
945 struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
946 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
949 struct omap_lcd_panel_s;
950 void omap_lcdc_reset(struct omap_lcd_panel_s *s);
951 struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
952 struct omap_dma_lcd_channel_s *dma,
953 ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
958 void (*write)(void *opaque, int dc, uint16_t value);
959 void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
960 uint16_t (*read)(void *opaque, int dc);
962 typedef void (*omap3_lcd_panel_fn_t)(uint8_t *, const uint8_t *, unsigned int);
963 struct omap3_lcd_panel_s;
965 void omap_dss_reset(struct omap_dss_s *s);
966 struct omap_dss_s *omap_dss_init(struct omap_mpu_state_s *mpu,
967 struct omap_target_agent_s *ta,
968 qemu_irq irq, qemu_irq drq,
969 omap_clk fck1, omap_clk fck2, omap_clk ck54m,
970 omap_clk ick1, omap_clk ick2);
971 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
972 void omap3_lcd_panel_attach(struct omap_dss_s *s, int cs, struct omap3_lcd_panel_s *lcd_panel);
973 void *omap3_lcd_panel_init(void);
977 struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
978 BlockDriverState *bd,
979 qemu_irq irq, qemu_irq dma[], omap_clk clk);
980 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
981 BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
982 omap_clk fclk, omap_clk iclk);
983 void omap_mmc_reset(struct omap_mmc_s *s);
984 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
985 void omap_mmc_enable(struct omap_mmc_s *s, int enable);
989 struct omap3_mmc_s *omap3_mmc_init(struct omap_target_agent_s *ta,
990 qemu_irq irq, qemu_irq dma[],
991 omap_clk fclk, omap_clk iclk);
992 void omap3_mmc_attach(struct omap3_mmc_s *s,
993 BlockDriverState *bd);
997 struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
998 qemu_irq irq, qemu_irq *dma, omap_clk clk);
999 struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
1000 qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);
1001 struct omap_i2c_s *omap3_i2c_init(struct omap_target_agent_s *ta,
1002 qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk,
1004 void omap_i2c_reset(struct omap_i2c_s *s);
1005 i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
1008 struct omap3_hsusb_s;
1009 struct omap3_hsusb_s *omap3_hsusb_init(struct omap_target_agent_s *otg_ta,
1010 struct omap_target_agent_s *host_ta,
1011 struct omap_target_agent_s *tll_ta,
1018 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
1019 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
1020 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
1021 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
1022 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
1023 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
1024 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
1025 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
1026 # define cpu_is_omap3530(cpu) (cpu->mpu_model == omap3530)
1028 # define cpu_is_omap15xx(cpu) \
1029 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
1030 # define cpu_is_omap16xx(cpu) \
1031 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
1032 # define cpu_is_omap24xx(cpu) \
1033 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
1035 # define cpu_class_omap1(cpu) \
1036 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
1037 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
1038 # define cpu_class_omap3(cpu) \
1039 (cpu_is_omap3430(cpu) || cpu_is_omap3530(cpu))
1041 struct omap_mpu_state_s {
1042 enum omap_mpu_model {
1063 struct omap_dma_port_if_s {
1064 uint32_t (*read[3])(struct omap_mpu_state_s *s,
1065 target_phys_addr_t offset);
1066 void (*write[3])(struct omap_mpu_state_s *s,
1067 target_phys_addr_t offset, uint32_t value);
1068 int (*addr_valid)(struct omap_mpu_state_s *s,
1069 target_phys_addr_t addr);
1070 } port[__omap_dma_port_last];
1072 unsigned long sdram_size;
1073 unsigned long sram_size;
1075 /* MPUI-TIPB peripherals */
1076 struct omap_uart_s *uart[3];
1078 struct omap_gpio_s *gpio;
1080 struct omap_mcbsp_s *mcbsp1;
1081 struct omap_mcbsp_s *mcbsp3;
1083 /* MPU public TIPB peripherals */
1084 struct omap_32khz_timer_s *os_timer;
1086 struct omap_mmc_s *mmc;
1088 struct omap_mpuio_s *mpuio;
1090 struct omap_uwire_s *microwire;
1106 struct omap_i2c_s *i2c[3];
1108 struct omap_rtc_s *rtc;
1110 struct omap_mcbsp_s *mcbsp2;
1112 struct omap_lpg_s *led[2];
1114 /* MPU private TIPB peripherals */
1115 struct omap_intr_handler_s *ih[2];
1117 struct soc_dma_s *dma;
1119 struct omap_mpu_timer_s *timer[3];
1120 struct omap_watchdog_timer_s *wdt;
1122 struct omap_lcd_panel_s *lcd;
1124 uint32_t ulpd_pm_regs[21];
1125 int64_t ulpd_gauge_start;
1127 uint32_t func_mux_ctrl[14];
1128 uint32_t comp_mode_ctrl[1];
1129 uint32_t pull_dwn_ctrl[4];
1130 uint32_t gate_inh_ctrl[1];
1131 uint32_t voltage_ctrl[1];
1132 uint32_t test_dbg_ctrl[1];
1133 uint32_t mod_conf_ctrl[1];
1138 struct omap_tipb_bridge_s *private_tipb;
1139 struct omap_tipb_bridge_s *public_tipb;
1141 uint32_t tcmi_regs[17];
1151 int clocking_scheme;
1153 uint16_t arm_idlect1;
1154 uint16_t arm_idlect2;
1155 uint16_t arm_ewupct;
1156 uint16_t arm_rstct1;
1157 uint16_t arm_rstct2;
1158 uint16_t arm_ckout1;
1160 uint16_t dsp_idlect1;
1161 uint16_t dsp_idlect2;
1162 uint16_t dsp_rstct2;
1165 /* OMAP2-only peripherals */
1166 struct omap_l4_s *l4;
1168 struct omap_gp_timer_s *gptimer[12];
1170 struct omap_synctimer_s {
1173 uint32_t sysconfig; /*OMAP3*/
1176 struct omap_prcm_s *prcm;
1177 struct omap_sdrc_s *sdrc;
1178 struct omap_gpmc_s *gpmc;
1179 struct omap_sysctl_s *sysc;
1181 struct omap_gpif_s *gpif;
1183 struct omap_mcspi_s *mcspi[2];
1185 struct omap_dss_s *dss;
1187 struct omap_eac_s *eac;
1190 struct omap3_prm_s *omap3_prm;
1191 struct omap3_cm_s *omap3_cm;
1192 struct omap3_wdt_s *omap3_mpu_wdt;
1193 struct omap_l3_s *omap3_l3;
1194 struct omap3_scm_s *omap3_scm;
1195 struct omap3_sms_s *omap3_sms;
1196 struct omap3_mmc_s *omap3_mmc[3];
1197 struct omap3_hsusb_s *omap3_usb;
1200 struct omap_target_agent_s {
1201 struct omap_l4_s *bus;
1203 struct omap_l4_region_s *start;
1204 target_phys_addr_t base;
1207 uint32_t control_h; /* OMAP3 */
1212 target_phys_addr_t base;
1214 struct omap_target_agent_s ta[0];
1217 struct omap_l4_region_s {
1218 target_phys_addr_t offset;
1223 struct omap_l4_agent_info_s {
1231 struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
1235 struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
1239 struct omap_mpu_state_s *omap3530_mpu_init(unsigned long sdram_size,
1241 void omap3_set_mem_type(struct omap_mpu_state_s *s, int bootfrom);
1244 void omap3_boot_rom_emu(struct omap_mpu_state_s *s);
1246 # if TARGET_PHYS_ADDR_BITS == 32
1247 # define OMAP_FMT_plx "0x%08x"
1248 # elif TARGET_PHYS_ADDR_BITS == 64
1249 # define OMAP_FMT_plx "0x%08" PRIx64
1251 # error TARGET_PHYS_ADDR_BITS undefined
1254 uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
1255 void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
1257 uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
1258 void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
1260 uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
1261 void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
1264 void omap_mpu_wakeup(void *opaque, int irq, int req);
1266 # define OMAP_BAD_REG(paddr) \
1267 fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \
1268 __FUNCTION__, paddr)
1269 # define OMAP_BAD_REGV(paddr, value) \
1270 fprintf(stderr, "%s: Bad register " OMAP_FMT_plx " (value 0x%08x)\n", \
1271 __FUNCTION__, paddr, value)
1272 # define OMAP_RO_REG(paddr) \
1273 fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \
1274 __FUNCTION__, paddr)
1275 # define OMAP_RO_REGV(paddr, value) \
1276 fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx " (value 0x%08x)\n", \
1277 __FUNCTION__, paddr, value)
1279 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
1280 (Board-specifc tags are not here) */
1281 #define OMAP_TAG_CLOCK 0x4f01
1282 #define OMAP_TAG_MMC 0x4f02
1283 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03
1284 #define OMAP_TAG_USB 0x4f04
1285 #define OMAP_TAG_LCD 0x4f05
1286 #define OMAP_TAG_GPIO_SWITCH 0x4f06
1287 #define OMAP_TAG_UART 0x4f07
1288 #define OMAP_TAG_FBMEM 0x4f08
1289 #define OMAP_TAG_STI_CONSOLE 0x4f09
1290 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a
1291 #define OMAP_TAG_PARTITION 0x4f0b
1292 #define OMAP_TAG_TEA5761 0x4f10
1293 #define OMAP_TAG_TMP105 0x4f11
1294 #define OMAP_TAG_BOOT_REASON 0x4f80
1295 #define OMAP_TAG_FLASH_PART_STR 0x4f81
1296 #define OMAP_TAG_VERSION_STR 0x4f82
1299 OMAP_GPIOSW_TYPE_COVER = 0 << 4,
1300 OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
1301 OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4,
1304 #define OMAP_GPIOSW_INVERTED 0x0001
1305 #define OMAP_GPIOSW_OUTPUT 0x0002
1307 # define TCMI_VERBOSE 1
1308 //# define MEM_VERBOSE 1
1310 # ifdef TCMI_VERBOSE
1311 # define OMAP_8B_REG(paddr) \
1312 fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \
1313 __FUNCTION__, paddr)
1314 # define OMAP_16B_REG(paddr) \
1315 fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \
1316 __FUNCTION__, paddr)
1317 # define OMAP_32B_REG(paddr) \
1318 fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \
1319 __FUNCTION__, paddr)
1321 # define OMAP_8B_REG(paddr)
1322 # define OMAP_16B_REG(paddr)
1323 # define OMAP_32B_REG(paddr)
1326 # define OMAP_MPUI_REG_MASK 0x000007ff
1330 CPUReadMemoryFunc **mem_read;
1331 CPUWriteMemoryFunc **mem_write;
1336 static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
1338 struct io_fn *s = opaque;
1342 ret = s->mem_read[0](s->opaque, addr);
1345 fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
1348 static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
1350 struct io_fn *s = opaque;
1354 ret = s->mem_read[1](s->opaque, addr);
1357 fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
1360 static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
1362 struct io_fn *s = opaque;
1366 ret = s->mem_read[2](s->opaque, addr);
1369 fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
1372 static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
1374 struct io_fn *s = opaque;
1377 fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
1379 s->mem_write[0](s->opaque, addr, value);
1382 static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
1384 struct io_fn *s = opaque;
1387 fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
1389 s->mem_write[1](s->opaque, addr, value);
1392 static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
1394 struct io_fn *s = opaque;
1397 fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
1399 s->mem_write[2](s->opaque, addr, value);
1403 static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };
1404 static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };
1406 inline static int debug_register_io_memory(int io_index,
1407 CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write,
1410 struct io_fn *s = qemu_malloc(sizeof(struct io_fn));
1412 s->mem_read = mem_read;
1413 s->mem_write = mem_write;
1416 return cpu_register_io_memory(io_index, io_readfn, io_writefn, s);
1418 # define cpu_register_io_memory debug_register_io_memory
1421 /* Define when we want to reduce the number of IO regions registered. */
1422 /*# define L4_MUX_HACK*/
1425 # undef l4_register_io_memory
1426 int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read,
1427 CPUWriteMemoryFunc **mem_write, void *opaque);
1430 #endif /* hw_omap_h */