2 * Texas Instruments OMAP processors.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 # define hw_omap_h "omap.h"
23 # define OMAP_EMIFS_BASE 0x00000000
24 # define OMAP2_Q0_BASE 0x00000000
25 # define OMAP_CS0_BASE 0x00000000
26 # define OMAP_CS1_BASE 0x04000000
27 # define OMAP_CS2_BASE 0x08000000
28 # define OMAP_CS3_BASE 0x0c000000
29 # define OMAP_EMIFF_BASE 0x10000000
30 # define OMAP_IMIF_BASE 0x20000000
31 # define OMAP_LOCALBUS_BASE 0x30000000
32 # define OMAP2_Q1_BASE 0x40000000
33 # define OMAP2_L4_BASE 0x48000000
34 # define OMAP2_SRAM_BASE 0x40200000
35 # define OMAP2_L3_BASE 0x68000000
36 # define OMAP2_Q2_BASE 0x80000000
37 # define OMAP2_Q3_BASE 0xc0000000
38 # define OMAP3_Q1_BASE 0x40000000
39 # define OMAP3_L4_BASE 0x48000000
40 # define OMAP3_SRAM_BASE 0x40200000
41 # define OMAP3_L3_BASE 0x68000000
42 # define OMAP3_Q2_BASE 0x80000000
43 # define OMAP3_Q3_BASE 0xc0000000
44 # define OMAP_MPUI_BASE 0xe1000000
46 # define OMAP730_SRAM_SIZE 0x00032000
47 # define OMAP15XX_SRAM_SIZE 0x00030000
48 # define OMAP16XX_SRAM_SIZE 0x00004000
49 # define OMAP1611_SRAM_SIZE 0x0003e800
50 # define OMAP242X_SRAM_SIZE 0x000a0000
51 # define OMAP243X_SRAM_SIZE 0x00010000
52 # define OMAP3530_SRAM_SIZE 0x00010000
53 # define OMAP_CS0_SIZE 0x04000000
54 # define OMAP_CS1_SIZE 0x04000000
55 # define OMAP_CS2_SIZE 0x04000000
56 # define OMAP_CS3_SIZE 0x04000000
59 struct omap_mpu_state_s;
60 typedef struct clk *omap_clk;
61 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
62 void omap_clk_init(struct omap_mpu_state_s *mpu);
63 void omap_clk_adduser(struct clk *clk, qemu_irq user);
64 void omap_clk_get(omap_clk clk);
65 void omap_clk_put(omap_clk clk);
66 void omap_clk_onoff(omap_clk clk, int on);
67 void omap_clk_canidle(omap_clk clk, int can);
68 void omap_clk_setrate(omap_clk clk, int divide, int multiply);
69 int64_t omap_clk_getrate(omap_clk clk);
70 void omap_clk_reparent(omap_clk clk, omap_clk parent);
74 struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num);
76 struct omap_target_agent_s;
77 struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs);
78 target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
80 # define l4_register_io_memory cpu_register_io_memory
82 struct omap_intr_handler_s;
83 struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
84 unsigned long size, unsigned char nbanks, qemu_irq **pins,
85 qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);
86 struct omap_intr_handler_s *omap2_inth_init(struct omap_mpu_state_s *mpu,
87 target_phys_addr_t base,
88 int size, int nbanks, qemu_irq **pins,
89 qemu_irq parent_irq, qemu_irq parent_fiq,
90 omap_clk fclk, omap_clk iclk);
91 void omap_inth_reset(struct omap_intr_handler_s *s);
94 struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
95 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
96 struct omap_mpu_state_s *mpu);
99 struct omap3_prm_s *omap3_prm_init(struct omap_target_agent_s *ta,
100 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
101 struct omap_mpu_state_s *mpu);
104 struct omap3_cm_s *omap3_cm_init(struct omap_target_agent_s *ta,
105 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
106 struct omap_mpu_state_s *mpu);
108 struct omap_sysctl_s;
109 struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
110 omap_clk iclk, struct omap_mpu_state_s *mpu);
113 struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
114 void omap_sdrc_write_mcfg(struct omap_sdrc_s *s, uint32_t value, uint32_t cs);
117 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
118 target_phys_addr_t base, qemu_irq irq);
119 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
120 void (*base_upd)(void *opaque, target_phys_addr_t new),
121 void (*unmap)(void *opaque), void *opaque,
122 CPUReadMemoryFunc **nand_readfn,
123 CPUWriteMemoryFunc **nand_writefn);
126 * Common IRQ numbers for level 1 interrupt handler
127 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
129 # define OMAP_INT_CAMERA 1
130 # define OMAP_INT_FIQ 3
131 # define OMAP_INT_RTDX 6
132 # define OMAP_INT_DSP_MMU_ABORT 7
133 # define OMAP_INT_HOST 8
134 # define OMAP_INT_ABORT 9
135 # define OMAP_INT_BRIDGE_PRIV 13
136 # define OMAP_INT_GPIO_BANK1 14
137 # define OMAP_INT_UART3 15
138 # define OMAP_INT_TIMER3 16
139 # define OMAP_INT_DMA_CH0_6 19
140 # define OMAP_INT_DMA_CH1_7 20
141 # define OMAP_INT_DMA_CH2_8 21
142 # define OMAP_INT_DMA_CH3 22
143 # define OMAP_INT_DMA_CH4 23
144 # define OMAP_INT_DMA_CH5 24
145 # define OMAP_INT_DMA_LCD 25
146 # define OMAP_INT_TIMER1 26
147 # define OMAP_INT_WD_TIMER 27
148 # define OMAP_INT_BRIDGE_PUB 28
149 # define OMAP_INT_TIMER2 30
150 # define OMAP_INT_LCD_CTRL 31
153 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
155 # define OMAP_INT_15XX_IH2_IRQ 0
156 # define OMAP_INT_15XX_LB_MMU 17
157 # define OMAP_INT_15XX_LOCAL_BUS 29
160 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
162 # define OMAP_INT_1510_SPI_TX 4
163 # define OMAP_INT_1510_SPI_RX 5
164 # define OMAP_INT_1510_DSP_MAILBOX1 10
165 # define OMAP_INT_1510_DSP_MAILBOX2 11
168 * OMAP-310 specific IRQ numbers for level 1 interrupt handler
170 # define OMAP_INT_310_McBSP2_TX 4
171 # define OMAP_INT_310_McBSP2_RX 5
172 # define OMAP_INT_310_HSB_MAILBOX1 12
173 # define OMAP_INT_310_HSAB_MMU 18
176 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
178 # define OMAP_INT_1610_IH2_IRQ 0
179 # define OMAP_INT_1610_IH2_FIQ 2
180 # define OMAP_INT_1610_McBSP2_TX 4
181 # define OMAP_INT_1610_McBSP2_RX 5
182 # define OMAP_INT_1610_DSP_MAILBOX1 10
183 # define OMAP_INT_1610_DSP_MAILBOX2 11
184 # define OMAP_INT_1610_LCD_LINE 12
185 # define OMAP_INT_1610_GPTIMER1 17
186 # define OMAP_INT_1610_GPTIMER2 18
187 # define OMAP_INT_1610_SSR_FIFO_0 29
190 * OMAP-730 specific IRQ numbers for level 1 interrupt handler
192 # define OMAP_INT_730_IH2_FIQ 0
193 # define OMAP_INT_730_IH2_IRQ 1
194 # define OMAP_INT_730_USB_NON_ISO 2
195 # define OMAP_INT_730_USB_ISO 3
196 # define OMAP_INT_730_ICR 4
197 # define OMAP_INT_730_EAC 5
198 # define OMAP_INT_730_GPIO_BANK1 6
199 # define OMAP_INT_730_GPIO_BANK2 7
200 # define OMAP_INT_730_GPIO_BANK3 8
201 # define OMAP_INT_730_McBSP2TX 10
202 # define OMAP_INT_730_McBSP2RX 11
203 # define OMAP_INT_730_McBSP2RX_OVF 12
204 # define OMAP_INT_730_LCD_LINE 14
205 # define OMAP_INT_730_GSM_PROTECT 15
206 # define OMAP_INT_730_TIMER3 16
207 # define OMAP_INT_730_GPIO_BANK5 17
208 # define OMAP_INT_730_GPIO_BANK6 18
209 # define OMAP_INT_730_SPGIO_WR 29
212 * Common IRQ numbers for level 2 interrupt handler
214 # define OMAP_INT_KEYBOARD 1
215 # define OMAP_INT_uWireTX 2
216 # define OMAP_INT_uWireRX 3
217 # define OMAP_INT_I2C 4
218 # define OMAP_INT_MPUIO 5
219 # define OMAP_INT_USB_HHC_1 6
220 # define OMAP_INT_McBSP3TX 10
221 # define OMAP_INT_McBSP3RX 11
222 # define OMAP_INT_McBSP1TX 12
223 # define OMAP_INT_McBSP1RX 13
224 # define OMAP_INT_UART1 14
225 # define OMAP_INT_UART2 15
226 # define OMAP_INT_USB_W2FC 20
227 # define OMAP_INT_1WIRE 21
228 # define OMAP_INT_OS_TIMER 22
229 # define OMAP_INT_OQN 23
230 # define OMAP_INT_GAUGE_32K 24
231 # define OMAP_INT_RTC_TIMER 25
232 # define OMAP_INT_RTC_ALARM 26
233 # define OMAP_INT_DSP_MMU 28
236 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
238 # define OMAP_INT_1510_BT_MCSI1TX 16
239 # define OMAP_INT_1510_BT_MCSI1RX 17
240 # define OMAP_INT_1510_SoSSI_MATCH 19
241 # define OMAP_INT_1510_MEM_STICK 27
242 # define OMAP_INT_1510_COM_SPI_RO 31
245 * OMAP-310 specific IRQ numbers for level 2 interrupt handler
247 # define OMAP_INT_310_FAC 0
248 # define OMAP_INT_310_USB_HHC_2 7
249 # define OMAP_INT_310_MCSI1_FE 16
250 # define OMAP_INT_310_MCSI2_FE 17
251 # define OMAP_INT_310_USB_W2FC_ISO 29
252 # define OMAP_INT_310_USB_W2FC_NON_ISO 30
253 # define OMAP_INT_310_McBSP2RX_OF 31
256 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
258 # define OMAP_INT_1610_FAC 0
259 # define OMAP_INT_1610_USB_HHC_2 7
260 # define OMAP_INT_1610_USB_OTG 8
261 # define OMAP_INT_1610_SoSSI 9
262 # define OMAP_INT_1610_BT_MCSI1TX 16
263 # define OMAP_INT_1610_BT_MCSI1RX 17
264 # define OMAP_INT_1610_SoSSI_MATCH 19
265 # define OMAP_INT_1610_MEM_STICK 27
266 # define OMAP_INT_1610_McBSP2RX_OF 31
267 # define OMAP_INT_1610_STI 32
268 # define OMAP_INT_1610_STI_WAKEUP 33
269 # define OMAP_INT_1610_GPTIMER3 34
270 # define OMAP_INT_1610_GPTIMER4 35
271 # define OMAP_INT_1610_GPTIMER5 36
272 # define OMAP_INT_1610_GPTIMER6 37
273 # define OMAP_INT_1610_GPTIMER7 38
274 # define OMAP_INT_1610_GPTIMER8 39
275 # define OMAP_INT_1610_GPIO_BANK2 40
276 # define OMAP_INT_1610_GPIO_BANK3 41
277 # define OMAP_INT_1610_MMC2 42
278 # define OMAP_INT_1610_CF 43
279 # define OMAP_INT_1610_WAKE_UP_REQ 46
280 # define OMAP_INT_1610_GPIO_BANK4 48
281 # define OMAP_INT_1610_SPI 49
282 # define OMAP_INT_1610_DMA_CH6 53
283 # define OMAP_INT_1610_DMA_CH7 54
284 # define OMAP_INT_1610_DMA_CH8 55
285 # define OMAP_INT_1610_DMA_CH9 56
286 # define OMAP_INT_1610_DMA_CH10 57
287 # define OMAP_INT_1610_DMA_CH11 58
288 # define OMAP_INT_1610_DMA_CH12 59
289 # define OMAP_INT_1610_DMA_CH13 60
290 # define OMAP_INT_1610_DMA_CH14 61
291 # define OMAP_INT_1610_DMA_CH15 62
292 # define OMAP_INT_1610_NAND 63
295 * OMAP-730 specific IRQ numbers for level 2 interrupt handler
297 # define OMAP_INT_730_HW_ERRORS 0
298 # define OMAP_INT_730_NFIQ_PWR_FAIL 1
299 # define OMAP_INT_730_CFCD 2
300 # define OMAP_INT_730_CFIREQ 3
301 # define OMAP_INT_730_I2C 4
302 # define OMAP_INT_730_PCC 5
303 # define OMAP_INT_730_MPU_EXT_NIRQ 6
304 # define OMAP_INT_730_SPI_100K_1 7
305 # define OMAP_INT_730_SYREN_SPI 8
306 # define OMAP_INT_730_VLYNQ 9
307 # define OMAP_INT_730_GPIO_BANK4 10
308 # define OMAP_INT_730_McBSP1TX 11
309 # define OMAP_INT_730_McBSP1RX 12
310 # define OMAP_INT_730_McBSP1RX_OF 13
311 # define OMAP_INT_730_UART_MODEM_IRDA_2 14
312 # define OMAP_INT_730_UART_MODEM_1 15
313 # define OMAP_INT_730_MCSI 16
314 # define OMAP_INT_730_uWireTX 17
315 # define OMAP_INT_730_uWireRX 18
316 # define OMAP_INT_730_SMC_CD 19
317 # define OMAP_INT_730_SMC_IREQ 20
318 # define OMAP_INT_730_HDQ_1WIRE 21
319 # define OMAP_INT_730_TIMER32K 22
320 # define OMAP_INT_730_MMC_SDIO 23
321 # define OMAP_INT_730_UPLD 24
322 # define OMAP_INT_730_USB_HHC_1 27
323 # define OMAP_INT_730_USB_HHC_2 28
324 # define OMAP_INT_730_USB_GENI 29
325 # define OMAP_INT_730_USB_OTG 30
326 # define OMAP_INT_730_CAMERA_IF 31
327 # define OMAP_INT_730_RNG 32
328 # define OMAP_INT_730_DUAL_MODE_TIMER 33
329 # define OMAP_INT_730_DBB_RF_EN 34
330 # define OMAP_INT_730_MPUIO_KEYPAD 35
331 # define OMAP_INT_730_SHA1_MD5 36
332 # define OMAP_INT_730_SPI_100K_2 37
333 # define OMAP_INT_730_RNG_IDLE 38
334 # define OMAP_INT_730_MPUIO 39
335 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
336 # define OMAP_INT_730_LLPC_OE_FALLING 41
337 # define OMAP_INT_730_LLPC_OE_RISING 42
338 # define OMAP_INT_730_LLPC_VSYNC 43
339 # define OMAP_INT_730_WAKE_UP_REQ 46
340 # define OMAP_INT_730_DMA_CH6 53
341 # define OMAP_INT_730_DMA_CH7 54
342 # define OMAP_INT_730_DMA_CH8 55
343 # define OMAP_INT_730_DMA_CH9 56
344 # define OMAP_INT_730_DMA_CH10 57
345 # define OMAP_INT_730_DMA_CH11 58
346 # define OMAP_INT_730_DMA_CH12 59
347 # define OMAP_INT_730_DMA_CH13 60
348 # define OMAP_INT_730_DMA_CH14 61
349 # define OMAP_INT_730_DMA_CH15 62
350 # define OMAP_INT_730_NAND 63
353 * OMAP-24xx common IRQ numbers
355 # define OMAP_INT_24XX_STI 4
356 # define OMAP_INT_24XX_SYS_NIRQ 7
357 # define OMAP_INT_24XX_L3_IRQ 10
358 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11
359 # define OMAP_INT_24XX_SDMA_IRQ0 12
360 # define OMAP_INT_24XX_SDMA_IRQ1 13
361 # define OMAP_INT_24XX_SDMA_IRQ2 14
362 # define OMAP_INT_24XX_SDMA_IRQ3 15
363 # define OMAP_INT_243X_MCBSP2_IRQ 16
364 # define OMAP_INT_243X_MCBSP3_IRQ 17
365 # define OMAP_INT_243X_MCBSP4_IRQ 18
366 # define OMAP_INT_243X_MCBSP5_IRQ 19
367 # define OMAP_INT_24XX_GPMC_IRQ 20
368 # define OMAP_INT_24XX_GUFFAW_IRQ 21
369 # define OMAP_INT_24XX_IVA_IRQ 22
370 # define OMAP_INT_24XX_EAC_IRQ 23
371 # define OMAP_INT_24XX_CAM_IRQ 24
372 # define OMAP_INT_24XX_DSS_IRQ 25
373 # define OMAP_INT_24XX_MAIL_U0_MPU 26
374 # define OMAP_INT_24XX_DSP_UMA 27
375 # define OMAP_INT_24XX_DSP_MMU 28
376 # define OMAP_INT_24XX_GPIO_BANK1 29
377 # define OMAP_INT_24XX_GPIO_BANK2 30
378 # define OMAP_INT_24XX_GPIO_BANK3 31
379 # define OMAP_INT_24XX_GPIO_BANK4 32
380 # define OMAP_INT_243X_GPIO_BANK5 33
381 # define OMAP_INT_24XX_MAIL_U3_MPU 34
382 # define OMAP_INT_24XX_WDT3 35
383 # define OMAP_INT_24XX_WDT4 36
384 # define OMAP_INT_24XX_GPTIMER1 37
385 # define OMAP_INT_24XX_GPTIMER2 38
386 # define OMAP_INT_24XX_GPTIMER3 39
387 # define OMAP_INT_24XX_GPTIMER4 40
388 # define OMAP_INT_24XX_GPTIMER5 41
389 # define OMAP_INT_24XX_GPTIMER6 42
390 # define OMAP_INT_24XX_GPTIMER7 43
391 # define OMAP_INT_24XX_GPTIMER8 44
392 # define OMAP_INT_24XX_GPTIMER9 45
393 # define OMAP_INT_24XX_GPTIMER10 46
394 # define OMAP_INT_24XX_GPTIMER11 47
395 # define OMAP_INT_24XX_GPTIMER12 48
396 # define OMAP_INT_24XX_PKA_IRQ 50
397 # define OMAP_INT_24XX_SHA1MD5_IRQ 51
398 # define OMAP_INT_24XX_RNG_IRQ 52
399 # define OMAP_INT_24XX_MG_IRQ 53
400 # define OMAP_INT_24XX_I2C1_IRQ 56
401 # define OMAP_INT_24XX_I2C2_IRQ 57
402 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59
403 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60
404 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62
405 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63
406 # define OMAP_INT_243X_MCBSP1_IRQ 64
407 # define OMAP_INT_24XX_MCSPI1_IRQ 65
408 # define OMAP_INT_24XX_MCSPI2_IRQ 66
409 # define OMAP_INT_24XX_SSI1_IRQ0 67
410 # define OMAP_INT_24XX_SSI1_IRQ1 68
411 # define OMAP_INT_24XX_SSI2_IRQ0 69
412 # define OMAP_INT_24XX_SSI2_IRQ1 70
413 # define OMAP_INT_24XX_SSI_GDD_IRQ 71
414 # define OMAP_INT_24XX_UART1_IRQ 72
415 # define OMAP_INT_24XX_UART2_IRQ 73
416 # define OMAP_INT_24XX_UART3_IRQ 74
417 # define OMAP_INT_24XX_USB_IRQ_GEN 75
418 # define OMAP_INT_24XX_USB_IRQ_NISO 76
419 # define OMAP_INT_24XX_USB_IRQ_ISO 77
420 # define OMAP_INT_24XX_USB_IRQ_HGEN 78
421 # define OMAP_INT_24XX_USB_IRQ_HSOF 79
422 # define OMAP_INT_24XX_USB_IRQ_OTG 80
423 # define OMAP_INT_24XX_VLYNQ_IRQ 81
424 # define OMAP_INT_24XX_MMC_IRQ 83
425 # define OMAP_INT_24XX_MS_IRQ 84
426 # define OMAP_INT_24XX_FAC_IRQ 85
427 # define OMAP_INT_24XX_MCSPI3_IRQ 91
428 # define OMAP_INT_243X_HS_USB_MC 92
429 # define OMAP_INT_243X_HS_USB_DMA 93
430 # define OMAP_INT_243X_CARKIT 94
431 # define OMAP_INT_34XX_GPTIMER12 95
434 * OMAP-35XX common IRQ numbers
436 # define OMAP_INT_35XX_SYS_NIRQ 7
437 # define OMAP_INT_35XX_PRCM_MPU_IRQ 11
438 # define OMAP_INT_35XX_SDMA_IRQ0 12
439 # define OMAP_INT_35XX_SDMA_IRQ1 13
440 # define OMAP_INT_35XX_SDMA_IRQ2 14
441 # define OMAP_INT_35XX_SDMA_IRQ3 15
442 # define OMAP_INT_35XX_MCBSP1_IRQ 16
443 # define OMAP_INT_35XX_MCBSP2_IRQ 17
444 # define OMAP_INT_35XX_GPMC_IRQ 20
445 # define OMAP_INT_35XX_MCBSP3_IRQ 22
446 # define OMAP_INT_35XX_MCBSP4_IRQ 23
447 # define OMAP_INT_35XX_CAM_IRQ 24
448 # define OMAP_INT_35XX_DSS_IRQ 25
449 # define OMAP_INT_35XX_MAIL_U0_MPU 26
450 # define OMAP_INT_35XX_MCBSP5_IRQ 27
451 # define OMAP_INT_35XX_DSP_MMU 28
452 # define OMAP_INT_35XX_GPIO_BANK1 29
453 # define OMAP_INT_35XX_GPIO_BANK2 30
454 # define OMAP_INT_35XX_GPIO_BANK3 31
455 # define OMAP_INT_35XX_GPIO_BANK4 32
456 # define OMAP_INT_35XX_GPIO_BANK5 33
457 # define OMAP_INT_35XX_GPIO_BANK6 34
458 # define OMAP_INT_35XX_WDT3 36
459 # define OMAP_INT_35XX_GPTIMER1 37
460 # define OMAP_INT_35XX_GPTIMER2 38
461 # define OMAP_INT_35XX_GPTIMER3 39
462 # define OMAP_INT_35XX_GPTIMER4 40
463 # define OMAP_INT_35XX_GPTIMER5 41
464 # define OMAP_INT_35XX_GPTIMER6 42
465 # define OMAP_INT_35XX_GPTIMER7 43
466 # define OMAP_INT_35XX_GPTIMER8 44
467 # define OMAP_INT_35XX_GPTIMER9 45
468 # define OMAP_INT_35XX_GPTIMER10 46
469 # define OMAP_INT_35XX_GPTIMER11 47
470 # define OMAP_INT_35XX_MG_IRQ 53
471 # define OMAP_INT_35XX_MCBSP4_IRQ_TX 54
472 # define OMAP_INT_35XX_MCBSP4_IRQ_RX 55
473 # define OMAP_INT_35XX_I2C1_IRQ 56
474 # define OMAP_INT_35XX_I2C2_IRQ 57
475 # define OMAP_INT_35XX_MCBSP1_IRQ_TX 59
476 # define OMAP_INT_35XX_MCBSP1_IRQ_RX 60
477 # define OMAP_INT_35XX_I2C3_IRQ 61
478 # define OMAP_INT_35XX_MCBSP2_IRQ_TX 62
479 # define OMAP_INT_35XX_MCBSP2_IRQ_RX 63
480 # define OMAP_INT_35XX_MCSPI1_IRQ 65
481 # define OMAP_INT_35XX_MCSPI2_IRQ 66
482 # define OMAP_INT_35XX_UART1_IRQ 72
483 # define OMAP_INT_35XX_UART2_IRQ 73
484 # define OMAP_INT_35XX_UART3_IRQ 74
485 # define OMAP_INT_35XX_MCBSP5_IRQ_TX 81
486 # define OMAP_INT_35XX_MCBSP5_IRQ_RX 82
487 # define OMAP_INT_35XX_MMC1_IRQ 83
488 # define OMAP_INT_35XX_MS_IRQ 84
489 # define OMAP_INT_35XX_MMC2_IRQ 86
490 # define OMAP_INT_35XX_MCBSP3_IRQ_TX 89
491 # define OMAP_INT_35XX_MCBSP3_IRQ_RX 90
492 # define OMAP_INT_35XX_MCSPI3_IRQ 91
493 # define OMAP_INT_35XX_HS_USB_MC 92
494 # define OMAP_INT_35XX_HS_USB_DMA 93
495 # define OMAP_INT_35XX_MMC3_IRQ 94
496 # define OMAP_INT_35XX_GPTIMER12 95
499 enum omap_dma_model {
507 struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
508 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
509 enum omap_dma_model model);
510 struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
511 struct omap_mpu_state_s *mpu, int fifo,
512 int chans, omap_clk iclk, omap_clk fclk);
513 void omap_dma_reset(struct soc_dma_s *s);
520 /* Only used in OMAP DMA 3.x gigacells */
524 imif, /* omap16xx: ocp_t1 */
526 local, /* omap16xx: ocp_t2 */
528 __omap_dma_port_last,
536 } omap_dma_addressing_t;
538 /* Only used in OMAP DMA 3.x gigacells */
539 struct omap_dma_lcd_channel_s {
540 enum omap_dma_port src;
541 target_phys_addr_t src_f1_top;
542 target_phys_addr_t src_f1_bottom;
543 target_phys_addr_t src_f2_top;
544 target_phys_addr_t src_f2_bottom;
546 /* Used in OMAP DMA 3.2 gigacell */
547 unsigned char brust_f1;
548 unsigned char pack_f1;
549 unsigned char data_type_f1;
550 unsigned char brust_f2;
551 unsigned char pack_f2;
552 unsigned char data_type_f2;
553 unsigned char end_prog;
554 unsigned char repeat;
555 unsigned char auto_init;
556 unsigned char priority;
558 unsigned char running;
560 unsigned char omap_3_1_compatible_disable;
562 unsigned char lch_type;
563 int16_t element_index_f1;
564 int16_t element_index_f2;
565 int32_t frame_index_f1;
566 int32_t frame_index_f2;
567 uint16_t elements_f1;
569 uint16_t elements_f2;
571 omap_dma_addressing_t mode_f1;
572 omap_dma_addressing_t mode_f2;
574 /* Destination port is fixed. */
580 ram_addr_t phys_framebuffer[2];
582 struct omap_mpu_state_s *mpu;
583 } *omap_dma_get_lcdch(struct soc_dma_s *s);
586 * DMA request numbers for OMAP1
587 * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
589 # define OMAP_DMA_NO_DEVICE 0
590 # define OMAP_DMA_MCSI1_TX 1
591 # define OMAP_DMA_MCSI1_RX 2
592 # define OMAP_DMA_I2C_RX 3
593 # define OMAP_DMA_I2C_TX 4
594 # define OMAP_DMA_EXT_NDMA_REQ0 5
595 # define OMAP_DMA_EXT_NDMA_REQ1 6
596 # define OMAP_DMA_UWIRE_TX 7
597 # define OMAP_DMA_MCBSP1_TX 8
598 # define OMAP_DMA_MCBSP1_RX 9
599 # define OMAP_DMA_MCBSP3_TX 10
600 # define OMAP_DMA_MCBSP3_RX 11
601 # define OMAP_DMA_UART1_TX 12
602 # define OMAP_DMA_UART1_RX 13
603 # define OMAP_DMA_UART2_TX 14
604 # define OMAP_DMA_UART2_RX 15
605 # define OMAP_DMA_MCBSP2_TX 16
606 # define OMAP_DMA_MCBSP2_RX 17
607 # define OMAP_DMA_UART3_TX 18
608 # define OMAP_DMA_UART3_RX 19
609 # define OMAP_DMA_CAMERA_IF_RX 20
610 # define OMAP_DMA_MMC_TX 21
611 # define OMAP_DMA_MMC_RX 22
612 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */
613 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
614 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
615 # define OMAP_DMA_USB_W2FC_RX0 26
616 # define OMAP_DMA_USB_W2FC_RX1 27
617 # define OMAP_DMA_USB_W2FC_RX2 28
618 # define OMAP_DMA_USB_W2FC_TX0 29
619 # define OMAP_DMA_USB_W2FC_TX1 30
620 # define OMAP_DMA_USB_W2FC_TX2 31
622 /* These are only for 1610 */
623 # define OMAP_DMA_CRYPTO_DES_IN 32
624 # define OMAP_DMA_SPI_TX 33
625 # define OMAP_DMA_SPI_RX 34
626 # define OMAP_DMA_CRYPTO_HASH 35
627 # define OMAP_DMA_CCP_ATTN 36
628 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
629 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38
630 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39
631 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40
632 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41
633 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42
634 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43
635 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44
636 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45
637 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46
638 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47
639 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48
640 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49
641 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50
642 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51
643 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52
644 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53
645 # define OMAP_DMA_MMC2_TX 54
646 # define OMAP_DMA_MMC2_RX 55
647 # define OMAP_DMA_CRYPTO_DES_OUT 56
650 * DMA request numbers for the OMAP2
652 # define OMAP24XX_DMA_NO_DEVICE 0
653 # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */
654 # define OMAP24XX_DMA_EXT_DMAREQ0 2
655 # define OMAP24XX_DMA_EXT_DMAREQ1 3
656 # define OMAP24XX_DMA_GPMC 4
657 # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */
658 # define OMAP24XX_DMA_DSS 6
659 # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */
660 # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */
661 # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */
662 # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */
663 # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */
664 # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */
665 # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */
666 # define OMAP24XX_DMA_EXT_DMAREQ2 14
667 # define OMAP24XX_DMA_EXT_DMAREQ3 15
668 # define OMAP24XX_DMA_EXT_DMAREQ4 16
669 # define OMAP24XX_DMA_EAC_AC_RD 17
670 # define OMAP24XX_DMA_EAC_AC_WR 18
671 # define OMAP24XX_DMA_EAC_MD_UL_RD 19
672 # define OMAP24XX_DMA_EAC_MD_UL_WR 20
673 # define OMAP24XX_DMA_EAC_MD_DL_RD 21
674 # define OMAP24XX_DMA_EAC_MD_DL_WR 22
675 # define OMAP24XX_DMA_EAC_BT_UL_RD 23
676 # define OMAP24XX_DMA_EAC_BT_UL_WR 24
677 # define OMAP24XX_DMA_EAC_BT_DL_RD 25
678 # define OMAP24XX_DMA_EAC_BT_DL_WR 26
679 # define OMAP24XX_DMA_I2C1_TX 27
680 # define OMAP24XX_DMA_I2C1_RX 28
681 # define OMAP24XX_DMA_I2C2_TX 29
682 # define OMAP24XX_DMA_I2C2_RX 30
683 # define OMAP24XX_DMA_MCBSP1_TX 31
684 # define OMAP24XX_DMA_MCBSP1_RX 32
685 # define OMAP24XX_DMA_MCBSP2_TX 33
686 # define OMAP24XX_DMA_MCBSP2_RX 34
687 # define OMAP24XX_DMA_SPI1_TX0 35
688 # define OMAP24XX_DMA_SPI1_RX0 36
689 # define OMAP24XX_DMA_SPI1_TX1 37
690 # define OMAP24XX_DMA_SPI1_RX1 38
691 # define OMAP24XX_DMA_SPI1_TX2 39
692 # define OMAP24XX_DMA_SPI1_RX2 40
693 # define OMAP24XX_DMA_SPI1_TX3 41
694 # define OMAP24XX_DMA_SPI1_RX3 42
695 # define OMAP24XX_DMA_SPI2_TX0 43
696 # define OMAP24XX_DMA_SPI2_RX0 44
697 # define OMAP24XX_DMA_SPI2_TX1 45
698 # define OMAP24XX_DMA_SPI2_RX1 46
700 # define OMAP24XX_DMA_UART1_TX 49
701 # define OMAP24XX_DMA_UART1_RX 50
702 # define OMAP24XX_DMA_UART2_TX 51
703 # define OMAP24XX_DMA_UART2_RX 52
704 # define OMAP24XX_DMA_UART3_TX 53
705 # define OMAP24XX_DMA_UART3_RX 54
706 # define OMAP24XX_DMA_USB_W2FC_TX0 55
707 # define OMAP24XX_DMA_USB_W2FC_RX0 56
708 # define OMAP24XX_DMA_USB_W2FC_TX1 57
709 # define OMAP24XX_DMA_USB_W2FC_RX1 58
710 # define OMAP24XX_DMA_USB_W2FC_TX2 59
711 # define OMAP24XX_DMA_USB_W2FC_RX2 60
712 # define OMAP24XX_DMA_MMC1_TX 61
713 # define OMAP24XX_DMA_MMC1_RX 62
714 # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */
715 # define OMAP24XX_DMA_EXT_DMAREQ5 64
718 * DMA request numbers for the OMAP3
720 # define OMAP35XX_DMA_NO_DEVICE 0
721 # define OMAP35XX_DMA_EXT_DMAREQ0 1
722 # define OMAP35XX_DMA_EXT_DMAREQ1 2
723 # define OMAP35XX_DMA_GPMC 3
725 # define OMAP35XX_DMA_DSS_LINETRIGGER 5
726 # define OMAP35XX_DMA_EXT_DMAREQ2 6
728 # define OMAP35XX_DMA_AES1_TX 8
729 # define OMAP35XX_DMA_AES1_RX 9
730 # define OMAP35XX_DMA_DES1_TX 10
731 # define OMAP35XX_DMA_DES1_RX 11
732 # define OMAP35XX_DMA_SHA2MD5_RX 12
734 # define OMAP35XX_DMA_SPI3_TX0 14
735 # define OMAP35XX_DMA_SPI3_RX0 15
736 # define OMAP35XX_DMA_MCBSP3_TX 16
737 # define OMAP35XX_DMA_MCBSP3_RX 17
738 # define OMAP35XX_DMA_MCBSP4_TX 18
739 # define OMAP35XX_DMA_MCBSP4_RX 19
740 # define OMAP35XX_DMA_MCBSP5_TX 20
741 # define OMAP35XX_DMA_MCBSP5_RX 21
742 # define OMAP35XX_DMA_SPI3_TX1 22
743 # define OMAP35XX_DMA_SPI3_RX1 23
744 # define OMAP35XX_DMA_I2C3_TX 24
745 # define OMAP35XX_DMA_I2C3_RX 25
746 # define OMAP35XX_DMA_I2C1_TX 26
747 # define OMAP35XX_DMA_I2C1_RX 27
748 # define OMAP35XX_DMA_I2C2_TX 28
749 # define OMAP35XX_DMA_I2C2_RX 29
750 # define OMAP35XX_DMA_MCBSP1_TX 30
751 # define OMAP35XX_DMA_MCBSP1_RX 31
752 # define OMAP35XX_DMA_MCBSP2_TX 32
753 # define OMAP35XX_DMA_MCBSP2_RX 33
754 # define OMAP35XX_DMA_SPI1_TX0 34
755 # define OMAP35XX_DMA_SPI1_RX0 35
756 # define OMAP35XX_DMA_SPI1_TX1 36
757 # define OMAP35XX_DMA_SPI1_RX1 37
758 # define OMAP35XX_DMA_SPI1_TX2 38
759 # define OMAP35XX_DMA_SPI1_RX2 39
760 # define OMAP35XX_DMA_SPI1_TX3 40
761 # define OMAP35XX_DMA_SPI1_RX4 41
762 # define OMAP35XX_DMA_SPI2_TX0 42
763 # define OMAP35XX_DMA_SPI2_RX0 43
764 # define OMAP35XX_DMA_SPI2_TX1 44
765 # define OMAP35XX_DMA_SPI2_RX1 45
766 # define OMAP35XX_DMA_MMC2_TX 46
767 # define OMAP35XX_DMA_MMC2_RX 47
768 # define OMAP35XX_DMA_UART1_TX 48
769 # define OMAP35XX_DMA_UART1_RX 49
770 # define OMAP35XX_DMA_UART2_TX 50
771 # define OMAP35XX_DMA_UART2_RX 51
772 # define OMAP35XX_DMA_UART3_TX 52
773 # define OMAP35XX_DMA_UART3_RX 53
774 # define OMAP35XX_DMA_MMC1_TX 60
775 # define OMAP35XX_DMA_MMC1_RX 61
776 # define OMAP35XX_DMA_MS 62
777 # define OMAP35XX_DMA_EXT_DMAREQ3 63
778 # define OMAP35XX_DMA_AES2_TX 64
779 # define OMAP35XX_DMA_AES2_RX 65
780 # define OMAP35XX_DMA_DES2_TX 66
781 # define OMAP35XX_DMA_DES2_RX 67
782 # define OMAP35XX_DMA_SHA1MD5_RX 68
783 # define OMAP35XX_DMA_SPI4_TX0 69
784 # define OMAP35XX_DMA_SPI4_RX0 70
785 # define OMAP35XX_DMA_DSS0 71
786 # define OMAP35XX_DMA_DSS1 72
787 # define OMAP35XX_DMA_DSS2 73
788 # define OMAP35XX_DMA_DSS3 74
790 # define OMAP35XX_DMA_MMC3_TX 76
791 # define OMAP35XX_DMA_MMC3_RX 77
792 # define OMAP35XX_DMA_USIM_TX 78
793 # define OMAP35XX_DMA_USIM_RX 79
796 struct omap_mpu_timer_s;
797 struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
798 qemu_irq irq, omap_clk clk);
800 struct omap_gp_timer_s;
801 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
802 qemu_irq irq, omap_clk fclk, omap_clk iclk);
803 void omap_gp_timer_change_clk(struct omap_gp_timer_s *timer);
805 struct omap_watchdog_timer_s;
806 struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
807 qemu_irq irq, omap_clk clk);
809 struct omap_32khz_timer_s;
810 struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
811 qemu_irq irq, omap_clk clk);
813 void omap_synctimer_init(struct omap_target_agent_s *ta,
814 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
816 struct omap_tipb_bridge_s;
817 struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
818 qemu_irq abort_irq, omap_clk clk);
821 struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
822 qemu_irq irq, omap_clk fclk, omap_clk iclk,
823 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr);
824 struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
825 qemu_irq irq, omap_clk fclk, omap_clk iclk,
826 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr);
827 void omap_uart_reset(struct omap_uart_s *s);
828 void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
831 struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
832 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
834 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
835 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
836 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
839 struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
840 qemu_irq irq, omap_clk clk);
841 qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);
842 void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler);
845 struct omap_gpif_s *omap2_gpio_init(struct omap_mpu_state_s *mpu,
846 struct omap_target_agent_s *ta,
847 qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules);
848 struct omap_gpif_s *omap3_gpif_init(void);
849 void omap3_gpio_init(struct omap_mpu_state_s *mpu,
850 struct omap_gpif_s *s, struct omap_target_agent_s *ta,
851 qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int module_index);
852 qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start);
853 void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler);
855 struct uwire_slave_s {
856 uint16_t (*receive)(void *opaque);
857 void (*send)(void *opaque, uint16_t data);
861 struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
862 qemu_irq *irq, qemu_irq dma, omap_clk clk);
863 void omap_uwire_attach(struct omap_uwire_s *s,
864 struct uwire_slave_s *slave, int chipselect);
867 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
868 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
869 void omap_mcspi_attach(struct omap_mcspi_s *s,
870 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
874 struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
875 qemu_irq *irq, omap_clk clk);
880 /* The CPU can call this if it is generating the clock signal on the
881 * i2s port. The CODEC can ignore it if it is set up as a clock
882 * master and generates its own clock. */
883 void (*set_rate)(void *opaque, int in, int out);
885 void (*tx_swallow)(void *opaque);
902 struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
903 qemu_irq *irq, qemu_irq *dma, omap_clk clk);
904 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave);
907 struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
909 void omap_tap_init(struct omap_target_agent_s *ta,
910 struct omap_mpu_state_s *mpu);
913 struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
914 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
917 struct omap_lcd_panel_s;
918 void omap_lcdc_reset(struct omap_lcd_panel_s *s);
919 struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
920 struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
921 ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
926 void (*write)(void *opaque, int dc, uint16_t value);
927 void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
928 uint16_t (*read)(void *opaque, int dc);
930 typedef void (*omap3_lcd_panel_fn_t)(uint8_t *, const uint8_t *, unsigned int);
931 struct omap3_lcd_panel_s {
932 struct omap_dss_s *dss;
934 QEMUConsole *console;
935 omap3_lcd_panel_fn_t *line_fn_tab[2];
936 omap3_lcd_panel_fn_t line_fn;
940 void omap_dss_reset(struct omap_dss_s *s);
941 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
942 target_phys_addr_t l3_base, DisplayState *ds,
943 qemu_irq irq, qemu_irq drq,
944 omap_clk fck1, omap_clk fck2, omap_clk ck54m,
945 omap_clk ick1, omap_clk ick2);
946 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
947 void omap3_lcd_panel_attach(struct omap_dss_s *s, int cs, struct omap3_lcd_panel_s *lcd_panel);
948 void *omap3_lcd_panel_init(DisplayState *ds);
952 struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
953 BlockDriverState *bd,
954 qemu_irq irq, qemu_irq dma[], omap_clk clk);
955 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
956 BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
957 omap_clk fclk, omap_clk iclk);
958 void omap_mmc_reset(struct omap_mmc_s *s);
959 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
960 void omap_mmc_enable(struct omap_mmc_s *s, int enable);
964 struct omap3_mmc_s *omap3_mmc_init(struct omap_target_agent_s *ta,
965 BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
966 omap_clk fclk, omap_clk iclk);
970 struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
971 qemu_irq irq, qemu_irq *dma, omap_clk clk);
972 struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
973 qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);
974 void omap_i2c_reset(struct omap_i2c_s *s);
975 i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
978 struct omap3_i2c_s *omap3_i2c_init(struct omap_target_agent_s *ta,
979 qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);
980 i2c_bus *omap3_i2c_bus(struct omap3_i2c_s *s);
983 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
984 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
985 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
986 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
987 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
988 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
989 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
990 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
991 # define cpu_is_omap3530(cpu) (cpu->mpu_model == omap3530)
993 # define cpu_is_omap15xx(cpu) \
994 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
995 # define cpu_is_omap16xx(cpu) \
996 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
997 # define cpu_is_omap24xx(cpu) \
998 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
1000 # define cpu_class_omap1(cpu) \
1001 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
1002 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
1003 # define cpu_class_omap3(cpu) \
1004 (cpu_is_omap3430(cpu) || cpu_is_omap3530(cpu))
1006 struct omap_mpu_state_s {
1007 enum omap_mpu_model {
1028 struct omap_dma_port_if_s {
1029 uint32_t (*read[3])(struct omap_mpu_state_s *s,
1030 target_phys_addr_t offset);
1031 void (*write[3])(struct omap_mpu_state_s *s,
1032 target_phys_addr_t offset, uint32_t value);
1033 int (*addr_valid)(struct omap_mpu_state_s *s,
1034 target_phys_addr_t addr);
1035 } port[__omap_dma_port_last];
1037 unsigned long sdram_size;
1038 unsigned long sram_size;
1040 /* MPUI-TIPB peripherals */
1041 struct omap_uart_s *uart[3];
1043 struct omap_gpio_s *gpio;
1045 struct omap_mcbsp_s *mcbsp1;
1046 struct omap_mcbsp_s *mcbsp3;
1048 /* MPU public TIPB peripherals */
1049 struct omap_32khz_timer_s *os_timer;
1051 struct omap_mmc_s *mmc;
1053 struct omap_mpuio_s *mpuio;
1055 struct omap_uwire_s *microwire;
1071 struct omap_i2c_s *i2c[2];
1073 struct omap_rtc_s *rtc;
1075 struct omap_mcbsp_s *mcbsp2;
1077 struct omap_lpg_s *led[2];
1079 /* MPU private TIPB peripherals */
1080 struct omap_intr_handler_s *ih[2];
1082 struct soc_dma_s *dma;
1084 struct omap_mpu_timer_s *timer[3];
1085 struct omap_watchdog_timer_s *wdt;
1087 struct omap_lcd_panel_s *lcd;
1089 uint32_t ulpd_pm_regs[21];
1090 int64_t ulpd_gauge_start;
1092 uint32_t func_mux_ctrl[14];
1093 uint32_t comp_mode_ctrl[1];
1094 uint32_t pull_dwn_ctrl[4];
1095 uint32_t gate_inh_ctrl[1];
1096 uint32_t voltage_ctrl[1];
1097 uint32_t test_dbg_ctrl[1];
1098 uint32_t mod_conf_ctrl[1];
1103 struct omap_tipb_bridge_s *private_tipb;
1104 struct omap_tipb_bridge_s *public_tipb;
1106 uint32_t tcmi_regs[17];
1116 int clocking_scheme;
1118 uint16_t arm_idlect1;
1119 uint16_t arm_idlect2;
1120 uint16_t arm_ewupct;
1121 uint16_t arm_rstct1;
1122 uint16_t arm_rstct2;
1123 uint16_t arm_ckout1;
1125 uint16_t dsp_idlect1;
1126 uint16_t dsp_idlect2;
1127 uint16_t dsp_rstct2;
1130 /* OMAP2-only peripherals */
1131 struct omap_l4_s *l4;
1133 struct omap_gp_timer_s *gptimer[12];
1135 struct omap_synctimer_s {
1138 uint32_t sysconfig; /*OMAP3*/
1141 struct omap_prcm_s *prcm;
1142 struct omap_sdrc_s *sdrc;
1143 struct omap_gpmc_s *gpmc;
1144 struct omap_sysctl_s *sysc;
1146 struct omap_gpif_s *gpif;
1148 struct omap_mcspi_s *mcspi[2];
1150 struct omap_dss_s *dss;
1152 struct omap_eac_s *eac;
1155 struct omap3_prm_s *omap3_prm;
1156 struct omap3_cm_s *omap3_cm;
1157 struct omap3_wdt_s *omap3_mpu_wdt;
1158 struct omap3_scm_s *omap3_scm;
1159 struct omap3_pm_s *omap3_pm;
1160 struct omap3_sms_s *omap3_sms;
1161 struct omap3_i2c_s *omap3_i2c[3];
1162 struct omap3_mmc_s *omap3_mmc;
1165 struct omap_target_agent_s {
1166 struct omap_l4_s *bus;
1168 struct omap_l4_region_s *start;
1169 target_phys_addr_t base;
1172 uint32_t control_h; /* OMAP3 */
1177 target_phys_addr_t base;
1179 struct omap_target_agent_s ta[0];
1182 struct omap_l4_region_s {
1183 target_phys_addr_t offset;
1188 struct omap_l4_agent_info_s {
1196 struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
1197 DisplayState *ds, const char *core);
1200 struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
1201 DisplayState *ds, const char *core);
1204 struct omap_mpu_state_s *omap3530_mpu_init(unsigned long sdram_size,
1205 DisplayState *ds, const char *core);
1206 void omap3_set_mem_type(struct omap_mpu_state_s *s, int bootfrom);
1207 void omap3_set_device_type(struct omap_mpu_state_s *s, int device_type);
1209 # if TARGET_PHYS_ADDR_BITS == 32
1210 # define OMAP_FMT_plx "0x%08x"
1211 # elif TARGET_PHYS_ADDR_BITS == 64
1212 # define OMAP_FMT_plx "0x%08" PRIx64
1214 # error TARGET_PHYS_ADDR_BITS undefined
1217 uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
1218 void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
1220 uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
1221 void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
1223 uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
1224 void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
1227 void omap_mpu_wakeup(void *opaque, int irq, int req);
1229 # define OMAP_BAD_REG(paddr) \
1230 fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \
1231 __FUNCTION__, paddr)
1232 # define OMAP_BAD_REGV(paddr, value) \
1233 fprintf(stderr, "%s: Bad register " OMAP_FMT_plx " (value " OMAP_FMT_plx ")\n", \
1234 __FUNCTION__, paddr, value)
1235 # define OMAP_RO_REG(paddr) \
1236 fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \
1237 __FUNCTION__, paddr)
1238 # define OMAP_RO_REGV(paddr, value) \
1239 fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx " (value " OMAP_FMT_plx ")\n", \
1240 __FUNCTION__, paddr, value)
1242 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
1243 (Board-specifc tags are not here) */
1244 #define OMAP_TAG_CLOCK 0x4f01
1245 #define OMAP_TAG_MMC 0x4f02
1246 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03
1247 #define OMAP_TAG_USB 0x4f04
1248 #define OMAP_TAG_LCD 0x4f05
1249 #define OMAP_TAG_GPIO_SWITCH 0x4f06
1250 #define OMAP_TAG_UART 0x4f07
1251 #define OMAP_TAG_FBMEM 0x4f08
1252 #define OMAP_TAG_STI_CONSOLE 0x4f09
1253 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a
1254 #define OMAP_TAG_PARTITION 0x4f0b
1255 #define OMAP_TAG_TEA5761 0x4f10
1256 #define OMAP_TAG_TMP105 0x4f11
1257 #define OMAP_TAG_BOOT_REASON 0x4f80
1258 #define OMAP_TAG_FLASH_PART_STR 0x4f81
1259 #define OMAP_TAG_VERSION_STR 0x4f82
1262 OMAP_GPIOSW_TYPE_COVER = 0 << 4,
1263 OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
1264 OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4,
1267 #define OMAP_GPIOSW_INVERTED 0x0001
1268 #define OMAP_GPIOSW_OUTPUT 0x0002
1270 # define TCMI_VERBOSE 1
1271 //# define MEM_VERBOSE 1
1273 # ifdef TCMI_VERBOSE
1274 # define OMAP_8B_REG(paddr) \
1275 fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \
1276 __FUNCTION__, paddr)
1277 # define OMAP_16B_REG(paddr) \
1278 fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \
1279 __FUNCTION__, paddr)
1280 # define OMAP_32B_REG(paddr) \
1281 fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \
1282 __FUNCTION__, paddr)
1284 # define OMAP_8B_REG(paddr)
1285 # define OMAP_16B_REG(paddr)
1286 # define OMAP_32B_REG(paddr)
1289 # define OMAP_MPUI_REG_MASK 0x000007ff
1293 CPUReadMemoryFunc **mem_read;
1294 CPUWriteMemoryFunc **mem_write;
1299 static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
1301 struct io_fn *s = opaque;
1305 ret = s->mem_read[0](s->opaque, addr);
1308 fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
1311 static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
1313 struct io_fn *s = opaque;
1317 ret = s->mem_read[1](s->opaque, addr);
1320 fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
1323 static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
1325 struct io_fn *s = opaque;
1329 ret = s->mem_read[2](s->opaque, addr);
1332 fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
1335 static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
1337 struct io_fn *s = opaque;
1340 fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
1342 s->mem_write[0](s->opaque, addr, value);
1345 static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
1347 struct io_fn *s = opaque;
1350 fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
1352 s->mem_write[1](s->opaque, addr, value);
1355 static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
1357 struct io_fn *s = opaque;
1360 fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
1362 s->mem_write[2](s->opaque, addr, value);
1366 static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };
1367 static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };
1369 inline static int debug_register_io_memory(int io_index,
1370 CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write,
1373 struct io_fn *s = qemu_malloc(sizeof(struct io_fn));
1375 s->mem_read = mem_read;
1376 s->mem_write = mem_write;
1379 return cpu_register_io_memory(io_index, io_readfn, io_writefn, s);
1381 # define cpu_register_io_memory debug_register_io_memory
1384 /* Define when we want to reduce the number of IO regions registered. */
1385 /*# define L4_MUX_HACK*/
1388 # undef l4_register_io_memory
1389 int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read,
1390 CPUWriteMemoryFunc **mem_write, void *opaque);
1393 #endif /* hw_omap_h */