2 * TI OMAP3 processors emulation.
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4 * Copyright (C) 2008 yajin <yajin@vm-kernel.org>
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6 * This program is free software; you can redistribute it and/or
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7 * modify it under the terms of the GNU General Public License as
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8 * published by the Free Software Foundation; either version 2 or
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9 * (at your option) version 3 of the License.
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11 * This program is distributed in the hope that it will be useful,
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 * GNU General Public License for more details.
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16 * You should have received a copy of the GNU General Public License
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17 * along with this program; if not, write to the Free Software
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18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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23 #include "arm-misc.h"
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26 #include "qemu-timer.h"
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27 #include "qemu-char.h"
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29 #include "soc_dma.h"
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30 #include "audio/audio.h"
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32 //#define OMAP3_DEBUG_
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35 #define TRACE(fmt, ...) fprintf(stderr, "%s " fmt "\n", __FUNCTION__, ##__VA_ARGS__)
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40 static uint32_t omap3_l4ta_read(void *opaque, target_phys_addr_t addr)
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42 struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
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45 case 0x00: /* COMPONENT_L */
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46 return s->component;
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47 case 0x04: /* COMPONENT_H */
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49 case 0x18: /* CORE_L */
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50 return s->component;
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51 case 0x1c: /* CORE_H */
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52 return (s->component >> 16);
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53 case 0x20: /* AGENT_CONTROL_L */
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55 case 0x24: /* AGENT_CONTROL_H */
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56 return s->control_h;
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57 case 0x28: /* AGENT_STATUS_L */
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59 case 0x2c: /* AGENT_STATUS_H */
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65 OMAP_BAD_REG(s->base + addr);
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69 static void omap3_l4ta_write(void *opaque, target_phys_addr_t addr,
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72 struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
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75 case 0x00: /* COMPONENT_L */
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76 case 0x04: /* COMPONENT_H */
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77 case 0x18: /* CORE_L */
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78 case 0x1c: /* CORE_H */
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79 OMAP_RO_REG(s->base + addr);
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81 case 0x20: /* AGENT_CONTROL_L */
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82 s->control = value & 0x00000701;
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84 case 0x24: /* AGENT_CONTROL_H */
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85 s->control_h = value & 0x100; /* TODO: shouldn't this be read-only? */
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87 case 0x28: /* AGENT_STATUS_L */
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89 s->status &= ~0x100; /* REQ_TIMEOUT */
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91 case 0x2c: /* AGENT_STATUS_H */
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92 /* no writable bits although the register is listed as RW */
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95 OMAP_BAD_REG(s->base + addr);
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100 static CPUReadMemoryFunc *omap3_l4ta_readfn[] = {
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101 omap_badwidth_read16,
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103 omap_badwidth_read16,
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106 static CPUWriteMemoryFunc *omap3_l4ta_writefn[] = {
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107 omap_badwidth_write32,
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108 omap_badwidth_write32,
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112 static struct omap_l4_region_s omap3_l4_region[158] = {
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114 [ 0] = {0x00002000, 0x1000, 32 | 16 | 8}, /* SCM */
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115 [ 1] = {0x00003000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
116 [ 2] = {0x00004000, 0x2000, 32 }, /* CM Region A */
\r
117 [ 3] = {0x00006000, 0x0800, 32 }, /* CM Region B */
\r
118 [ 4] = {0x00007000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
119 [ 5] = {0x00040000, 0x0800, 32 }, /* AP */
\r
120 [ 6] = {0x00040800, 0x0800, 32 }, /* IP */
\r
121 [ 7] = {0x00041000, 0x1000, 32 }, /* LA */
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122 [ 8] = {0x0004fc00, 0x0400, 32 | 16 | 8}, /* DSI */
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123 [ 9] = {0x00050000, 0x0400, 32 | 16 | 8}, /* DISS */
\r
124 [ 10] = {0x00050400, 0x0400, 32 | 16 | 8}, /* DISPC */
\r
125 [ 11] = {0x00050800, 0x0400, 32 | 16 | 8}, /* RFBI */
\r
126 [ 12] = {0x00050c00, 0x0400, 32 | 16 | 8}, /* VENC */
\r
127 [ 13] = {0x00051000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
128 [ 14] = {0x00056000, 0x1000, 32 }, /* SDMA */
\r
129 [ 15] = {0x00057000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
130 [ 16] = {0x00060000, 0x1000, 16 | 8}, /* I2C3 */
\r
131 [ 17] = {0x00061000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
132 [ 18] = {0x00062000, 0x1000, 32 }, /* USBTLL */
\r
133 [ 19] = {0x00063000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
134 [ 20] = {0x00064000, 0x1000, 32 }, /* HS USB HOST */
\r
135 [ 21] = {0x00065000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
136 [ 22] = {0x0006a000, 0x1000, 32 | 16 | 8}, /* UART1 */
\r
137 [ 23] = {0x0006b000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
138 [ 24] = {0x0006c000, 0x1000, 32 | 16 | 8}, /* UART2 */
\r
139 [ 25] = {0x0006d000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
140 [ 26] = {0x00070000, 0x1000, 16 | 8}, /* I2C1 */
\r
141 [ 27] = {0x00071000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
142 [ 28] = {0x00072000, 0x1000, 16 | 8}, /* I2C2 */
\r
143 [ 29] = {0x00073000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
144 [ 30] = {0x00074000, 0x1000, 32 }, /* McBSP1 */
\r
145 [ 31] = {0x00075000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
146 [ 32] = {0x00086000, 0x1000, 32 | 16 }, /* GPTIMER10 */
\r
147 [ 33] = {0x00087000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
148 [ 34] = {0x00088000, 0x1000, 32 | 16 }, /* GPTIMER11 */
\r
149 [ 35] = {0x00089000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
150 [ 36] = {0x00094000, 0x1000, 32 | 16 | 8}, /* MAILBOX */
\r
151 [ 37] = {0x00095000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
152 [ 38] = {0x00096000, 0x1000, 32 }, /* McBSP5 */
\r
153 [ 39] = {0x00097000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
154 [ 40] = {0x00098000, 0x1000, 32 | 16 | 8}, /* McSPI1 */
\r
155 [ 41] = {0x00099000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
156 [ 42] = {0x0009a000, 0x1000, 32 | 16 | 8}, /* McSPI2 */
\r
157 [ 43] = {0x0009b000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
158 [ 44] = {0x0009c000, 0x1000, 32 }, /* MMC/SD/SDIO1 */
\r
159 [ 45] = {0x0009d000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
160 [ 46] = {0x0009e000, 0x1000, 32 }, /* MS-PRO */
\r
161 [ 47] = {0x0009f000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
162 [ 48] = {0x000ab000, 0x1000, 32 }, /* HS USB OTG */
\r
163 [ 49] = {0x000ac000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
164 [ 50] = {0x000ad000, 0x1000, 32 }, /* MMC/SD/SDIO3 */
\r
165 [ 51] = {0x000ae000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
166 [ 52] = {0x000b2000, 0x1000, 32 }, /* HDQ/1-Wire */
\r
167 [ 53] = {0x000b3000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
168 [ 54] = {0x000b4000, 0x1000, 32 }, /* MMC/SD/SDIO2 */
\r
169 [ 55] = {0x000b5000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
170 [ 56] = {0x000b6000, 0x1000, 32 }, /* ICR MPU Port */
\r
171 [ 57] = {0x000b7000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
172 [ 58] = {0x000b8000, 0x1000, 32 | 16 | 8}, /* McSPI3 */
\r
173 [ 59] = {0x000b9000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
174 [ 60] = {0x000ba000, 0x1000, 32 | 16 | 8}, /* McSPI4 */
\r
175 [ 61] = {0x000bb000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
176 [ 62] = {0x000bc000, 0x4000, 32 | 16 | 8}, /* Camera ISP */
\r
177 [ 63] = {0x000c0000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
178 [ 64] = {0x000c7000, 0x1000, 32 }, /* Modem */
\r
179 [ 65] = {0x000c8000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
180 [ 66] = {0x000cd000, 0x1000, 32 }, /* ICR modem port */
\r
181 [ 67] = {0x000ce000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
182 /* L4-Wakeup interconnect region A */
\r
183 [ 68] = {0x00304000, 0x1000, 32 | 16 }, /* GPTIMER12 */
\r
184 [ 69] = {0x00305000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
185 [ 70] = {0x00306000, 0x2000, 32 }, /* PRM region A */
\r
186 [ 71] = {0x00308000, 0x0800, 32 }, /* PRM region B */
\r
187 [ 72] = {0x00309000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
189 [ 73] = {0x0030a000, 0x0800, 32 | 16 | 8}, /* TAP */
\r
190 [ 74] = {0x0030b000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
191 /* L4-Wakeup interconnect region B */
\r
192 [ 75] = {0x00310000, 0x1000, 32 | 16 | 8}, /* GPIO1 */
\r
193 [ 76] = {0x00311000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
194 [ 77] = {0x00314000, 0x1000, 32 | 16 }, /* WDTIMER2 */
\r
195 [ 78] = {0x00315000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
196 [ 79] = {0x00318000, 0x1000, 32 | 16 }, /* GPTIMER1 */
\r
197 [ 80] = {0x00319000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
198 [ 81] = {0x00320000, 0x1000, 32 | 16 }, /* 32K Timer */
\r
199 [ 82] = {0x00321000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
200 [ 83] = {0x00328000, 0x0800, 32 | 16 | 8}, /* L4-Wakeup config AP */
\r
201 [ 84] = {0x00328800, 0x0800, 32 | 16 | 8}, /* L4-Wakeup config IP L4-Core */
\r
202 [ 85] = {0x00329000, 0x1000, 32 | 16 | 8}, /* L4-Wakeup config LA */
\r
203 [ 86] = {0x0032a000, 0x0800, 32 | 16 | 8}, /* L4-Wakeup config IP L4-Emu */
\r
204 [ 87] = {0x00340000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
206 [ 88] = {0x01000000, 0x0800, 32 | 16 | 8}, /* AP */
\r
207 [ 89] = {0x01000800, 0x0800, 32 | 16 | 8}, /* IP */
\r
208 [ 90] = {0x01001000, 0x1000, 32 | 16 | 8}, /* LA */
\r
209 [ 91] = {0x01020000, 0x1000, 32 | 16 | 8}, /* UART3 */
\r
210 [ 92] = {0x01021000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
211 [ 93] = {0x01022000, 0x1000, 32 }, /* McBSP2 */
\r
212 [ 94] = {0x01023000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
213 [ 95] = {0x01024000, 0x1000, 32 }, /* McBSP3 */
\r
214 [ 96] = {0x01025000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
215 [ 97] = {0x01026000, 0x1000, 32 }, /* McBSP4 */
\r
216 [ 98] = {0x01027000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
217 [ 99] = {0x01028000, 0x1000, 32 }, /* McBSP2 (sidetone) */
\r
218 [100] = {0x01029000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
219 [101] = {0x0102a000, 0x1000, 32 }, /* McBSP3 (sidetone) */
\r
220 [102] = {0x0102b000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
221 [103] = {0x01030000, 0x1000, 32 | 16 }, /* WDTIMER3 */
\r
222 [104] = {0x01031000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
223 [105] = {0x01032000, 0x1000, 32 | 16 }, /* GPTIMER2 */
\r
224 [106] = {0x01033000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
225 [107] = {0x01034000, 0x1000, 32 | 16 }, /* GPTIMER3 */
\r
226 [108] = {0x01035000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
227 [109] = {0x01036000, 0x1000, 32 | 16 }, /* GPTIMER4 */
\r
228 [110] = {0x01037000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
229 [111] = {0x01038000, 0x1000, 32 | 16 }, /* GPTIMER5 */
\r
230 [112] = {0x01039000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
231 [113] = {0x0103a000, 0x1000, 32 | 16 }, /* GPTIMER6 */
\r
232 [114] = {0x0103b000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
233 [115] = {0x0103c000, 0x1000, 32 | 16 }, /* GPTIMER7 */
\r
234 [116] = {0x0103d000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
235 [117] = {0x0103e000, 0x1000, 32 | 16 }, /* GPTIMER8 */
\r
236 [118] = {0x0103f000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
237 [119] = {0x01040000, 0x1000, 32 | 16 }, /* GPTIMER9 */
\r
238 [120] = {0x01041000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
239 [121] = {0x01050000, 0x1000, 32 | 16 | 8}, /* GPIO2 */
\r
240 [122] = {0x01051000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
241 [123] = {0x01052000, 0x1000, 32 | 16 | 8}, /* GPIO3 */
\r
242 [124] = {0x01053000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
243 [125] = {0x01054000, 0x1000, 32 | 16 | 8}, /* GPIO4 */
\r
244 [126] = {0x01055000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
245 [127] = {0x01056000, 0x1000, 32 | 16 | 8}, /* GPIO5 */
\r
246 [128] = {0x01057000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
247 [129] = {0x01058000, 0x1000, 32 | 16 | 8}, /* GPIO6 */
\r
248 [130] = {0x01059000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
250 [131] = {0x0c006000, 0x0800, 32 | 16 | 8}, /* AP */
\r
251 [132] = {0x0c006800, 0x0800, 32 | 16 | 8}, /* IP L4-Core */
\r
252 [133] = {0x0c007000, 0x1000, 32 | 16 | 8}, /* LA */
\r
253 [134] = {0x0c008000, 0x0800, 32 | 16 | 8}, /* IP DAP */
\r
254 [135] = {0x0c010000, 0x8000, 32 | 16 | 8}, /* MPU Emulation */
\r
255 [136] = {0x0c018000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
256 [137] = {0x0c019000, 0x1000, 32 }, /* TPIU */
\r
257 [138] = {0x0c01a000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
258 [139] = {0x0c01b000, 0x1000, 32 }, /* ETB */
\r
259 [140] = {0x0c01c000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
260 [141] = {0x0c01d000, 0x1000, 32 }, /* DAPCTL */
\r
261 [142] = {0x0c01e000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
262 [143] = {0x0c706000, 0x2000, 32 }, /* PRM Region A */
\r
263 [144] = {0x0c706800, 0x0800, 32 }, /* PRM Region B */
\r
264 [145] = {0x0c709000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
265 [146] = {0x0c710000, 0x1000, 32 | 16 | 8}, /* GPIO1 */
\r
266 [147] = {0x0c711000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
267 [148] = {0x0c714000, 0x1000, 32 | 16 }, /* WDTIMER2 */
\r
268 [149] = {0x0c715000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
269 [150] = {0x0c718000, 0x1000, 32 | 16 | 8}, /* GPTIMER1 */
\r
270 [151] = {0x0c719000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
271 [152] = {0x0c720000, 0x1000, 32 | 16 }, /* 32k timer */
\r
272 [153] = {0x0c721000, 0x1000, 32 | 16 | 8}, /* L4IC */
\r
273 [154] = {0x0c728000, 0x0800, 32 | 16 | 8}, /* L4-Wakeup config AP */
\r
274 [155] = {0x0c728800, 0x0800, 32 | 16 | 8}, /* L4-Wakeup config IP L4-Core */
\r
275 [156] = {0x0c729000, 0x1000, 32 | 16 | 8}, /* L4-Wakeup config LA */
\r
276 [157] = {0x0c72a000, 0x0800, 32 | 16 | 8}, /* L4-Wakeup config IP L4-Emu */
\r
279 static struct omap_l4_agent_info_s omap3_l4_agent_info[] = {
\r
280 { 0, 0, 2, 1}, /* SCM */
\r
281 { 1, 1, 3, 2}, /* CM */
\r
282 { 2, 70, 3, 2}, /* PRM */
\r
283 { 3, 77, 2, 1}, /* WDTIMER2 */
\r
284 { 4, 79, 2, 1}, /* GPTIMER1 */
\r
285 { 5, 105, 2, 1}, /* GPTIMER2 */
\r
286 { 6, 107, 2, 1}, /* GPTIMER3 */
\r
287 { 7, 108, 2, 1}, /* GPTIMER4 */
\r
288 { 8, 111, 2, 1}, /* GPTIMER5 */
\r
289 { 9, 113, 2, 1}, /* GPTIMER6 */
\r
290 {10, 115, 2, 1}, /* GPTIMER7 */
\r
291 {11, 116, 2, 1}, /* GPTIMER8 */
\r
292 {12, 119, 2, 1}, /* GPTIMER9 */
\r
293 {13, 32, 2, 1}, /* GPTIMER10 */
\r
294 {14, 34, 2, 1}, /* GPTIMER11 */
\r
295 {15, 68, 2, 1}, /* GPTIMER12 */
\r
296 {16, 81, 2, 1}, /* 32K Sync timer */
\r
297 {17, 22, 2, 1}, /* UART1 */
\r
298 {18, 24, 2, 1}, /* UART2 */
\r
299 {19, 91, 2, 1}, /* UART3 */
\r
300 {20, 8, 6, 4}, /* DSS */
\r
301 {21, 75, 2, 1}, /* GPIO1 */
\r
302 {22, 121, 2, 1}, /* GPIO2 */
\r
303 {23, 123, 2, 1}, /* GPIO3 */
\r
304 {24, 125, 2, 1}, /* GPIO4 */
\r
305 {25, 127, 2, 1}, /* GPIO5 */
\r
306 {26, 129, 2, 1}, /* GPIO6 */
\r
307 {27, 73, 2, 1}, /* TAP */
\r
308 {28, 44, 2, 1}, /* MMC1 */
\r
309 {29, 54, 2, 1}, /* MMC2 */
\r
310 {30, 50, 2, 1}, /* MMC3 */
\r
311 {31, 26, 2, 1}, /* I2C1 */
\r
312 {32, 28, 2, 1}, /* I2C2 */
\r
313 {33, 16, 2, 1}, /* I2C3 */
\r
316 static struct omap_target_agent_s *omap3_l4ta_get(struct omap_l4_s *bus, int cs)
\r
319 struct omap_target_agent_s *ta = 0;
\r
320 struct omap_l4_agent_info_s *info = 0;
\r
322 for (i = 0; i < bus->ta_num; i++)
\r
323 if (omap3_l4_agent_info[i].ta == cs)
\r
326 info = &omap3_l4_agent_info[i];
\r
331 fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs);
\r
336 ta->start = &omap3_l4_region[info->region];
\r
337 ta->regions = info->regions;
\r
339 ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
\r
340 ta->status = 0x00000000;
\r
341 ta->control = 0x00000200; /* XXX 01000200 for L4TAO */
\r
343 iomemtype = l4_register_io_memory(0, omap3_l4ta_readfn,
\r
344 omap3_l4ta_writefn, ta);
\r
345 ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);
\r
354 struct omap_mpu_state_s *mpu;
\r
356 /*IVA2_PRM Register */
\r
357 uint32_t rm_rstctrl_iva2; /*0x4830 6050 */
\r
358 uint32_t rm_rstst_iva2; /*0x4830 6058 */
\r
359 uint32_t pm_wkdep_iva2; /*0x4830 60C8 */
\r
360 uint32_t pm_pwstctrl_iva2; /*0x4830 60E0 */
\r
361 uint32_t pm_pwstst_iva2; /*0x4830 60E4 */
\r
362 uint32_t pm_prepwstst_iva2; /*0x4830 60E8 */
\r
363 uint32_t prm_irqstatus_iva2; /*0x4830 60F8 */
\r
364 uint32_t prm_irqenable_iva2; /*0x4830 60FC */
\r
366 /*OCP_System_Reg_PRM Registerr */
\r
367 uint32_t prm_revision; /*0x4830 6804 */
\r
368 uint32_t prm_sysconfig; /*0x4830 6814 */
\r
369 uint32_t prm_irqstatus_mpu; /*0x4830 6818 */
\r
370 uint32_t prm_irqenable_mpu; /*0x4830 681c */
\r
372 /*MPU_PRM Register */
\r
373 uint32_t rm_rstst_mpu; /*0x4830 6958 */
\r
374 uint32_t pm_wkdep_mpu; /*0x4830 69c8 */
\r
375 uint32_t pm_evgenctrl_mpu; /*0x4830 69d4 */
\r
376 uint32_t pm_evgenontim_mpu; /*0x4830 69d8 */
\r
377 uint32_t pm_evgenofftim_mpu; /*0x4830 69dc */
\r
378 uint32_t pm_pwstctrl_mpu; /*0x4830 69e0 */
\r
379 uint32_t pm_pwstst_mpu; /*0x4830 69e4 */
\r
380 uint32_t pm_perpwstst_mpu; /*0x4830 69e8 */
\r
382 /*CORE_PRM Register */
\r
383 uint32_t rm_rstst_core; /*0x4830 6a58 */
\r
384 uint32_t pm_wken1_core; /*0x4830 6aa0 */
\r
385 uint32_t pm_mpugrpsel1_core; /*0x4830 6aa4 */
\r
386 uint32_t pm_iva2grpsel1_core; /*0x4830 6aa8 */
\r
387 uint32_t pm_wkst1_core; /*0x4830 6ab0 */
\r
388 uint32_t pm_wkst3_core; /*0x4830 6ab8 */
\r
389 uint32_t pm_pwstctrl_core; /*0x4830 6ae0 */
\r
390 uint32_t pm_pwstst_core; /*0x4830 6ae4 */
\r
391 uint32_t pm_prepwstst_core; /*0x4830 6ae8 */
\r
392 uint32_t pm_wken3_core; /*0x4830 6af0 */
\r
393 uint32_t pm_iva2grpsel3_core; /*0x4830 6af4 */
\r
394 uint32_t pm_mpugrpsel3_core; /*0x4830 6af8 */
\r
396 /*SGX_PRM Register */
\r
397 uint32_t rm_rstst_sgx; /*0x4830 6b58 */
\r
398 uint32_t pm_wkdep_sgx; /*0x4830 6bc8 */
\r
399 uint32_t pm_pwstctrl_sgx; /*0x4830 6be0 */
\r
400 uint32_t pm_pwstst_sgx; /*0x4830 6be4 */
\r
401 uint32_t pm_prepwstst_sgx; /*0x4830 6be8 */
\r
403 /*WKUP_PRM Register */
\r
404 uint32_t pm_wken_wkup; /*0x4830 6ca0 */
\r
405 uint32_t pm_mpugrpsel_wkup; /*0x4830 6ca4 */
\r
406 uint32_t pm_iva2grpsel_wkup; /*0x4830 6ca8 */
\r
407 uint32_t pm_wkst_wkup; /*0x4830 6cb0 */
\r
409 /*Clock_Control_Reg_PRM Register */
\r
410 uint32_t prm_clksel; /*0x4830 6D40 */
\r
411 uint32_t prm_clkout_ctrl; /*0x4830 6D70 */
\r
413 /*DSS_PRM Register */
\r
414 uint32_t rm_rstst_dss; /*0x4830 6e58 */
\r
415 uint32_t pm_wken_dss; /*0x4830 6ea0 */
\r
416 uint32_t pm_wkdep_dss; /*0x4830 6ec8 */
\r
417 uint32_t pm_pwstctrl_dss; /*0x4830 6ee0 */
\r
418 uint32_t pm_pwstst_dss; /*0x4830 6ee4 */
\r
419 uint32_t pm_prepwstst_dss; /*0x4830 6ee8 */
\r
421 /*CAM_PRM Register */
\r
422 uint32_t rm_rstst_cam; /*0x4830 6f58 */
\r
423 uint32_t pm_wkdep_cam; /*0x4830 6fc8 */
\r
424 uint32_t pm_pwstctrl_cam; /*0x4830 6fe0 */
\r
425 uint32_t pm_pwstst_cam; /*0x4830 6fe4 */
\r
426 uint32_t pm_prepwstst_cam; /*0x4830 6fe8 */
\r
428 /*PER_PRM Register */
\r
429 uint32_t rm_rstst_per; /*0x4830 7058 */
\r
430 uint32_t pm_wken_per; /*0x4830 70a0 */
\r
431 uint32_t pm_mpugrpsel_per; /*0x4830 70a4 */
\r
432 uint32_t pm_iva2grpsel_per; /*0x4830 70a8 */
\r
433 uint32_t pm_wkst_per; /*0x4830 70b0 */
\r
434 uint32_t pm_wkdep_per; /*0x4830 70c8 */
\r
435 uint32_t pm_pwstctrl_per; /*0x4830 70e0 */
\r
436 uint32_t pm_pwstst_per; /*0x4830 70e4 */
\r
437 uint32_t pm_perpwstst_per; /*0x4830 70e8 */
\r
439 /*EMU_PRM Register */
\r
440 uint32_t rm_rstst_emu; /*0x4830 7158 */
\r
441 uint32_t pm_pwstst_emu; /*0x4830 71e4 */
\r
443 /*Global_Reg_PRM Register */
\r
444 uint32_t prm_vc_smps_sa; /*0x4830 7220 */
\r
445 uint32_t prm_vc_smps_vol_ra; /*0x4830 7224 */
\r
446 uint32_t prm_vc_smps_cmd_ra; /*0x4830 7228 */
\r
447 uint32_t prm_vc_cmd_val_0; /*0x4830 722c */
\r
448 uint32_t prm_vc_cmd_val_1; /*0x4830 7230 */
\r
449 uint32_t prm_vc_hc_conf; /*0x4830 7234 */
\r
450 uint32_t prm_vc_i2c_cfg; /*0x4830 7238 */
\r
451 uint32_t prm_vc_bypass_val; /*0x4830 723c */
\r
452 uint32_t prm_rstctrl; /*0x4830 7250 */
\r
453 uint32_t prm_rsttimer; /*0x4830 7254 */
\r
454 uint32_t prm_rstst; /*0x4830 7258 */
\r
455 uint32_t prm_voltctrl; /*0x4830 7260 */
\r
456 uint32_t prm_sram_pcharge; /*0x4830 7264 */
\r
457 uint32_t prm_clksrc_ctrl; /*0x4830 7270 */
\r
458 uint32_t prm_obs; /*0x4830 7280 */
\r
459 uint32_t prm_voltsetup1; /*0x4830 7290 */
\r
460 uint32_t prm_voltoffset; /*0x4830 7294 */
\r
461 uint32_t prm_clksetup; /*0x4830 7298 */
\r
462 uint32_t prm_polctrl; /*0x4830 729c */
\r
463 uint32_t prm_voltsetup2; /*0x4830 72a0 */
\r
465 /*NEON_PRM Register */
\r
466 uint32_t rm_rstst_neon; /*0x4830 7358 */
\r
467 uint32_t pm_wkdep_neon; /*0x4830 73c8 */
\r
468 uint32_t pm_pwstctrl_neon; /*0x4830 73e0 */
\r
469 uint32_t pm_pwstst_neon; /*0x4830 73e4 */
\r
470 uint32_t pm_prepwstst_neon; /*0x4830 73e8 */
\r
472 /*USBHOST_PRM Register */
\r
473 uint32_t rm_rstst_usbhost; /*0x4830 7458 */
\r
474 uint32_t pm_wken_usbhost; /*0x4830 74a0 */
\r
475 uint32_t pm_mpugrpsel_usbhost; /*0x4830 74a4 */
\r
476 uint32_t pm_iva2grpsel_usbhost; /*0x4830 74a8 */
\r
477 uint32_t pm_wkst_usbhost; /*0x4830 74b0 */
\r
478 uint32_t pm_wkdep_usbhost; /*0x4830 74c8 */
\r
479 uint32_t pm_pwstctrl_usbhost; /*0x4830 74e0 */
\r
480 uint32_t pm_pwstst_usbhost; /*0x4830 74e4 */
\r
481 uint32_t pm_prepwstst_usbhost; /*0x4830 74e8 */
\r
485 static void omap3_prm_reset(struct omap3_prm_s *s)
\r
487 s->rm_rstctrl_iva2 = 0x7;
\r
488 s->rm_rstst_iva2 = 0x1;
\r
489 s->pm_wkdep_iva2 = 0xb3;
\r
490 s->pm_pwstctrl_iva2 = 0xff0f07;
\r
491 s->pm_pwstst_iva2 = 0xff7;
\r
492 s->pm_prepwstst_iva2 = 0x0;
\r
493 s->prm_irqstatus_iva2 = 0x0;
\r
494 s->prm_irqenable_iva2 = 0x0;
\r
496 s->prm_revision = 0x10;
\r
497 s->prm_sysconfig = 0x1;
\r
498 s->prm_irqstatus_mpu = 0x0;
\r
499 s->prm_irqenable_mpu = 0x0;
\r
501 s->rm_rstst_mpu = 0x1;
\r
502 s->pm_wkdep_mpu = 0xa5;
\r
503 s->pm_evgenctrl_mpu = 0x12;
\r
504 s->pm_evgenontim_mpu = 0x0;
\r
505 s->pm_evgenofftim_mpu = 0x0;
\r
506 s->pm_pwstctrl_mpu = 0x30107;
\r
507 s->pm_pwstst_mpu = 0xc7;
\r
508 s->pm_pwstst_mpu = 0x0;
\r
510 s->rm_rstst_core = 0x1;
\r
511 s->pm_wken1_core = 0xc33ffe18;
\r
512 s->pm_mpugrpsel1_core = 0xc33ffe18;
\r
513 s->pm_iva2grpsel1_core = 0xc33ffe18;
\r
514 s->pm_wkst1_core = 0x0;
\r
515 s->pm_wkst3_core = 0x0;
\r
516 s->pm_pwstctrl_core = 0xf0307;
\r
517 s->pm_pwstst_core = 0xf7;
\r
518 s->pm_prepwstst_core = 0x0;
\r
519 s->pm_wken3_core = 0x4;
\r
520 s->pm_iva2grpsel3_core = 0x4;
\r
521 s->pm_mpugrpsel3_core = 0x4;
\r
523 s->rm_rstst_sgx = 0x1;
\r
524 s->pm_wkdep_sgx = 0x16;
\r
525 s->pm_pwstctrl_sgx = 0x30107;
\r
526 s->pm_pwstst_sgx = 0x3;
\r
527 s->pm_prepwstst_sgx = 0x0;
\r
529 s->pm_wken_wkup = 0x3cb;
\r
530 s->pm_mpugrpsel_wkup = 0x3cb;
\r
531 s->pm_iva2grpsel_wkup = 0x0;
\r
532 s->pm_wkst_wkup = 0x0;
\r
534 s->prm_clksel = 0x4;
\r
535 s->prm_clkout_ctrl = 0x80;
\r
537 s->rm_rstst_dss = 0x1;
\r
538 s->pm_wken_dss = 0x1;
\r
539 s->pm_wkdep_dss = 0x16;
\r
540 s->pm_pwstctrl_dss = 0x30107;
\r
541 s->pm_pwstst_dss = 0x3;
\r
542 s->pm_prepwstst_dss = 0x0;
\r
544 s->rm_rstst_cam = 0x1;
\r
545 s->pm_wkdep_cam = 0x16;
\r
546 s->pm_pwstctrl_cam = 0x30107;
\r
547 s->pm_pwstst_cam = 0x3;
\r
548 s->pm_prepwstst_cam = 0x0;
\r
550 s->rm_rstst_per = 0x1;
\r
551 s->pm_wken_per = 0x3efff;
\r
552 s->pm_mpugrpsel_per = 0x3efff;
\r
553 s->pm_iva2grpsel_per = 0x3efff;
\r
554 s->pm_wkst_per = 0x0;
\r
555 s->pm_wkdep_per = 0x17;
\r
556 s->pm_pwstctrl_per = 0x30107;
\r
557 s->pm_pwstst_per = 0x7;
\r
558 s->pm_perpwstst_per = 0x0;
\r
560 s->rm_rstst_emu = 0x1;
\r
561 s->pm_pwstst_emu = 0x13;
\r
563 s->prm_vc_smps_sa = 0x0;
\r
564 s->prm_vc_smps_vol_ra = 0x0;
\r
565 s->prm_vc_smps_cmd_ra = 0x0;
\r
566 s->prm_vc_cmd_val_0 = 0x0;
\r
567 s->prm_vc_cmd_val_1 = 0x0;
\r
568 s->prm_vc_hc_conf = 0x0;
\r
569 s->prm_vc_i2c_cfg = 0x18;
\r
570 s->prm_vc_bypass_val = 0x0;
\r
571 s->prm_rstctrl = 0x0;
\r
572 s->prm_rsttimer = 0x1006;
\r
573 s->prm_rstst = 0x1;
\r
574 s->prm_voltctrl = 0x0;
\r
575 s->prm_sram_pcharge = 0x50;
\r
576 s->prm_clksrc_ctrl = 0x43;
\r
578 s->prm_voltsetup1 = 0x0;
\r
579 s->prm_voltoffset = 0x0;
\r
580 s->prm_clksetup = 0x0;
\r
581 s->prm_polctrl = 0xa;
\r
582 s->prm_voltsetup2 = 0x0;
\r
584 s->rm_rstst_neon = 0x1;
\r
585 s->pm_wkdep_neon = 0x2;
\r
586 s->pm_pwstctrl_neon = 0x7;
\r
587 s->pm_pwstst_neon = 0x3;
\r
588 s->pm_prepwstst_neon = 0x0;
\r
590 s->rm_rstst_usbhost = 0x1;
\r
591 s->pm_wken_usbhost = 0x1;
\r
592 s->pm_mpugrpsel_usbhost = 0x1;
\r
593 s->pm_iva2grpsel_usbhost = 0x1;
\r
594 s->pm_wkst_usbhost = 0x0;
\r
595 s->pm_wkdep_usbhost = 0x17;
\r
596 s->pm_pwstctrl_usbhost = 0x30107;
\r
597 s->pm_pwstst_usbhost = 0x3;
\r
598 s->pm_prepwstst_usbhost = 0x0;
\r
602 static uint32_t omap3_prm_read(void *opaque, target_phys_addr_t addr)
\r
604 struct omap3_prm_s *s = (struct omap3_prm_s *)opaque;
\r
606 TRACE("%04x", addr);
\r
609 case 0x0050: return s->rm_rstctrl_iva2;
\r
610 case 0x0058: return s->rm_rstst_iva2;
\r
611 case 0x00c8: return s->pm_wkdep_iva2;
\r
612 case 0x00e0: return s->pm_pwstctrl_iva2;
\r
613 case 0x00e4: return s->pm_pwstst_iva2;
\r
614 case 0x00e8: return s->pm_prepwstst_iva2;
\r
615 case 0x00f8: return s->prm_irqstatus_iva2;
\r
616 case 0x00fc: return s->prm_irqenable_iva2;
\r
617 /* OCP_System_Reg_PRM */
\r
618 case 0x0804: return s->prm_revision;
\r
619 case 0x0814: return s->prm_sysconfig;
\r
620 case 0x0818: return s->prm_irqstatus_mpu;
\r
621 case 0x081c: return s->prm_irqenable_mpu;
\r
623 case 0x0958: return s->rm_rstst_mpu;
\r
624 case 0x09c8: return s->pm_wkdep_mpu;
\r
625 case 0x09d4: return s->pm_evgenctrl_mpu;
\r
626 case 0x09d8: return s->pm_evgenontim_mpu;
\r
627 case 0x09dc: return s->pm_evgenofftim_mpu;
\r
628 case 0x09e0: return s->pm_pwstctrl_mpu;
\r
629 case 0x09e4: return s->pm_pwstst_mpu;
\r
630 case 0x09e8: return s->pm_perpwstst_mpu;
\r
632 case 0x0a58: return s->rm_rstst_core;
\r
633 case 0x0aa0: return s->pm_wken1_core;
\r
634 case 0x0aa4: return s->pm_mpugrpsel1_core;
\r
635 case 0x0aa8: return s->pm_iva2grpsel1_core;
\r
636 case 0x0ab0: return s->pm_wkst1_core;
\r
637 case 0x0ab8: return s->pm_wkst3_core;
\r
638 case 0x0ae0: return s->pm_pwstctrl_core;
\r
639 case 0x0ae4: return s->pm_pwstst_core;
\r
640 case 0x0ae8: return s->pm_prepwstst_core;
\r
641 case 0x0af0: return s->pm_wken3_core;
\r
642 case 0x0af4: return s->pm_iva2grpsel3_core;
\r
643 case 0x0af8: return s->pm_mpugrpsel3_core;
\r
645 case 0x0b58: return s->rm_rstst_sgx;
\r
646 case 0x0bc8: return s->pm_wkdep_sgx;
\r
647 case 0x0be0: return s->pm_pwstctrl_sgx;
\r
648 case 0x0be4: return s->pm_pwstst_sgx;
\r
649 case 0x0be8: return s->pm_prepwstst_sgx;
\r
651 case 0x0ca0: return s->pm_wken_wkup;
\r
652 case 0x0ca4: return s->pm_mpugrpsel_wkup;
\r
653 case 0x0ca8: return s->pm_iva2grpsel_wkup;
\r
654 case 0x0cb0: return s->pm_wkst_wkup;
\r
655 /* Clock_Control_Reg_PRM */
\r
656 case 0x0d40: return s->prm_clksel;
\r
657 case 0x0d70: return s->prm_clkout_ctrl;
\r
659 case 0x0e58: return s->rm_rstst_dss;
\r
660 case 0x0ea0: return s->pm_wken_dss;
\r
661 case 0x0ec8: return s->pm_wkdep_dss;
\r
662 case 0x0ee0: return s->pm_pwstctrl_dss;
\r
663 case 0x0ee4: return s->pm_pwstst_dss;
\r
664 case 0x0ee8: return s->pm_prepwstst_dss;
\r
666 case 0x0f58: return s->rm_rstst_cam;
\r
667 case 0x0fc8: return s->pm_wkdep_cam;
\r
668 case 0x0fe0: return s->pm_pwstctrl_cam;
\r
669 case 0x0fe4: return s->pm_pwstst_cam;
\r
670 case 0x0fe8: return s->pm_prepwstst_cam;
\r
672 case 0x1058: return s->rm_rstst_per;
\r
673 case 0x10a0: return s->pm_wken_per;
\r
674 case 0x10a4: return s->pm_mpugrpsel_per;
\r
675 case 0x10a8: return s->pm_iva2grpsel_per;
\r
676 case 0x10b0: return s->pm_wkst_per;
\r
677 case 0x10c8: return s->pm_wkdep_per;
\r
678 case 0x10e0: return s->pm_pwstctrl_per;
\r
679 case 0x10e4: return s->pm_pwstst_per;
\r
680 case 0x10e8: return s->pm_perpwstst_per;
\r
682 case 0x1158: return s->rm_rstst_emu;
\r
683 case 0x11e4: return s->pm_pwstst_emu;
\r
684 /* Global_Reg_PRM */
\r
685 case 0x1220: return s->prm_vc_smps_sa;
\r
686 case 0x1224: return s->prm_vc_smps_vol_ra;
\r
687 case 0x1228: return s->prm_vc_smps_cmd_ra;
\r
688 case 0x122c: return s->prm_vc_cmd_val_0;
\r
689 case 0x1230: return s->prm_vc_cmd_val_1;
\r
690 case 0x1234: return s->prm_vc_hc_conf;
\r
691 case 0x1238: return s->prm_vc_i2c_cfg;
\r
692 case 0x123c: return s->prm_vc_bypass_val;
\r
693 case 0x1250: return s->prm_rstctrl;
\r
694 case 0x1254: return s->prm_rsttimer;
\r
695 case 0x1258: return s->prm_rstst;
\r
696 case 0x1260: return s->prm_voltctrl;
\r
697 case 0x1264: return s->prm_sram_pcharge;
\r
698 case 0x1270: return s->prm_clksrc_ctrl;
\r
699 case 0x1280: return s->prm_obs;
\r
700 case 0x1290: return s->prm_voltsetup1;
\r
701 case 0x1294: return s->prm_voltoffset;
\r
702 case 0x1298: return s->prm_clksetup;
\r
703 case 0x129c: return s->prm_polctrl;
\r
704 case 0x12a0: return s->prm_voltsetup2;
\r
706 case 0x1358: return s->rm_rstst_neon;
\r
707 case 0x13c8: return s->pm_wkdep_neon;
\r
708 case 0x13e0: return s->pm_pwstctrl_neon;
\r
709 case 0x13e4: return s->pm_pwstst_neon;
\r
710 case 0x13e8: return s->pm_prepwstst_neon;
\r
712 case 0x1458: return s->rm_rstst_usbhost;
\r
713 case 0x14a0: return s->pm_wken_usbhost;
\r
714 case 0x14a4: return s->pm_mpugrpsel_usbhost;
\r
715 case 0x14a8: return s->pm_iva2grpsel_usbhost;
\r
716 case 0x14b0: return s->pm_wkst_usbhost;
\r
717 case 0x14c8: return s->pm_wkdep_usbhost;
\r
718 case 0x14e0: return s->pm_pwstctrl_usbhost;
\r
719 case 0x14e4: return s->pm_pwstst_usbhost;
\r
720 case 0x14e8: return s->pm_prepwstst_usbhost;
\r
722 OMAP_BAD_REG(addr);
\r
727 static inline void omap3_prm_clksrc_ctrl_update(struct omap3_prm_s *s,
\r
730 if ((value & 0xd0) == 0x40)
\r
731 omap_clk_setrate(omap_findclk(s->mpu, "omap3_sys_clk"), 1, 1);
\r
732 else if ((value & 0xd0) == 0x80)
\r
733 omap_clk_setrate(omap_findclk(s->mpu, "omap3_sys_clk"), 2, 1);
\r
736 static void omap3_prm_write(void *opaque, target_phys_addr_t addr,
\r
739 struct omap3_prm_s *s = (struct omap3_prm_s *)opaque;
\r
741 TRACE("%04x = %08x", addr, value);
\r
744 case 0x0050: s->rm_rstctrl_iva2 = value & 0x7; break;
\r
745 case 0x0058: s->rm_rstst_iva2 &= ~(value & 0x3f0f); break;
\r
746 case 0x00c8: s->pm_wkdep_iva2 = value & 0xb3; break;
\r
747 case 0x00e0: s->pm_pwstctrl_iva2 = 0xcff000 | (value & 0x300f0f); break;
\r
748 case 0x00e4: OMAP_RO_REG(addr); break;
\r
749 case 0x00e8: s->pm_prepwstst_iva2 = value & 0xff7;
\r
750 case 0x00f8: s->prm_irqstatus_iva2 &= ~(value & 0x7); break;
\r
751 case 0x00fc: s->prm_irqenable_iva2 = value & 0x7; break;
\r
752 /* OCP_System_Reg_PRM */
\r
753 case 0x0804: OMAP_RO_REG(addr); break;
\r
754 case 0x0814: s->prm_sysconfig = value & 0x1; break;
\r
755 case 0x0818: s->prm_irqstatus_mpu &= ~(value & 0x03c003fd); break;
\r
756 case 0x081c: s->prm_irqenable_mpu = value & 0x03c003fd; break;
\r
758 case 0x0958: s->rm_rstst_mpu &= ~(value & 0x080f); break;
\r
759 case 0x09c8: s->pm_wkdep_mpu = value & 0xa5; break;
\r
760 case 0x09d4: s->pm_evgenctrl_mpu = value & 0x1f; break;
\r
761 case 0x09d8: s->pm_evgenontim_mpu = value; break;
\r
762 case 0x09dc: s->pm_evgenofftim_mpu = value; break;
\r
763 case 0x09e0: s->pm_pwstctrl_mpu = value & 0x3010f; break;
\r
764 case 0x09e4: OMAP_RO_REG(addr); break;
\r
765 case 0x09e8: s->pm_perpwstst_mpu = value & 0xc7; break;
\r
767 case 0x0a58: s->rm_rstst_core &= ~(value & 0x7); break;
\r
768 case 0x0aa0: s->pm_wken1_core = 0x80000008 | (value & 0x433ffe10); break;
\r
769 case 0x0aa4: s->pm_mpugrpsel1_core = 0x80000008 | (value & 0x433ffe10); break;
\r
770 case 0x0aa8: s->pm_iva2grpsel1_core = 0x80000008 | (value & 0x433ffe10); break;
\r
771 case 0x0ab0: s->pm_wkst1_core = value & 0x433ffe10; break;
\r
772 case 0x0ab8: s->pm_wkst3_core &= ~(value & 0x4); break;
\r
773 case 0x0ae0: s->pm_pwstctrl_core = (value & 0x0f031f); break;
\r
774 case 0x0ae4: OMAP_RO_REG(addr); break;
\r
775 case 0x0ae8: s->pm_prepwstst_core = value & 0xf7; break;
\r
776 case 0x0af0: s->pm_wken3_core = value & 0x4; break;
\r
777 case 0x0af4: s->pm_iva2grpsel3_core = value & 0x4; break;
\r
778 case 0x0af8: s->pm_mpugrpsel3_core = value & 0x4; break;
\r
780 case 0x0b58: s->rm_rstst_sgx &= ~(value & 0xf); break;
\r
781 case 0x0bc8: s->pm_wkdep_sgx = value & 0x16; break;
\r
782 case 0x0be0: s->pm_pwstctrl_sgx = 0x030104 | (value & 0x3); break;
\r
783 case 0x0be4: OMAP_RO_REG(addr); break;
\r
784 case 0x0be8: s->pm_prepwstst_sgx = value & 0x3; break;
\r
786 case 0x0ca0: s->pm_wken_wkup = 0x2 | (value & 0x0103c9); break;
\r
787 case 0x0ca4: s->pm_mpugrpsel_wkup = 0x0102 | (value & 0x02c9); break;
\r
788 case 0x0ca8: s->pm_iva2grpsel_wkup = value & 0x03cb; break;
\r
789 case 0x0cb0: s->pm_wkst_wkup &= ~(value & 0x0103cb); break;
\r
790 /* Clock_Control_Reg_PRM */
\r
792 s->prm_clksel = value & 0x7;
\r
793 fprintf(stderr, "%s PRM_CLKSEL = 0x%x\n", __FUNCTION__,
\r
795 /* TODO: update clocks */
\r
798 s->prm_clkout_ctrl = value & 0x80;
\r
799 fprintf(stderr, "%s PRM_CLKOUT_CTRL = 0x%x\n", __FUNCTION__,
\r
800 s->prm_clkout_ctrl);
\r
801 /* TODO: check do we need to update something */
\r
804 case 0x0e58: s->rm_rstst_dss &= ~(value & 0xf); break;
\r
805 case 0x0ea0: s->pm_wken_dss = value & 1; break;
\r
806 case 0x0ec8: s->pm_wkdep_dss = value & 0x16; break;
\r
807 case 0x0ee0: s->pm_pwstctrl_dss = 0x030104 | (value & 3); break;
\r
808 case 0x0ee4: OMAP_RO_REG(addr); break;
\r
809 case 0x0ee8: s->pm_prepwstst_dss = value & 3; break;
\r
811 case 0x0f58: s->rm_rstst_cam &= (value & 0xf); break;
\r
812 case 0x0fc8: s->pm_wkdep_cam = value & 0x16; break;
\r
813 case 0x0fe0: s->pm_pwstctrl_cam = 0x030104 | (value & 3); break;
\r
814 case 0x0fe4: OMAP_RO_REG(addr); break;
\r
815 case 0x0fe8: s->pm_prepwstst_cam = value & 0x3; break;
\r
817 case 0x1058: s->rm_rstst_per &= ~(value & 0xf); break;
\r
818 case 0x10a0: s->pm_wken_per = value & 0x03efff; break;
\r
819 case 0x10a4: s->pm_mpugrpsel_per = value & 0x03efff; break;
\r
820 case 0x10a8: s->pm_iva2grpsel_per = value & 0x03efff; break;
\r
821 case 0x10b0: s->pm_wkst_per &= ~(value & 0x03efff); break;
\r
822 case 0x10c8: s->pm_wkdep_per = value & 0x17; break;
\r
823 case 0x10e0: s->pm_pwstctrl_per = 0x030100 | (value & 7); break;
\r
824 case 0x10e4: OMAP_RO_REG(addr); break;
\r
825 case 0x10e8: s->pm_perpwstst_per = value & 0x7; break;
\r
827 case 0x1158: s->rm_rstst_emu &= ~(value & 7); break;
\r
828 case 0x11e4: OMAP_RO_REG(addr); break;
\r
829 /* Global_Reg_PRM */
\r
830 case 0x1220: s->prm_vc_smps_sa = value & 0x7f007f; break;
\r
831 case 0x1224: s->prm_vc_smps_vol_ra = value & 0xff00ff; break;
\r
832 case 0x1228: s->prm_vc_smps_cmd_ra = value & 0xff00ff; break;
\r
833 case 0x122c: s->prm_vc_cmd_val_0 = value; break;
\r
834 case 0x1230: s->prm_vc_cmd_val_1 = value; break;
\r
835 case 0x1234: s->prm_vc_hc_conf = value & 0x1f001f; break;
\r
836 case 0x1238: s->prm_vc_i2c_cfg = value & 0x3f; break;
\r
837 case 0x123c: s->prm_vc_bypass_val = value & 0x01ffff7f; break;
\r
838 case 0x1250: s->prm_rstctrl = 0; break; /* TODO: resets */
\r
839 case 0x1254: s->prm_rsttimer = value & 0x1fff; break;
\r
840 case 0x1258: s->prm_rstst &= ~(value & 0x7fb); break;
\r
841 case 0x1260: s->prm_voltctrl = value & 0x1f; break;
\r
842 case 0x1264: s->prm_sram_pcharge = value & 0xff; break;
\r
844 s->prm_clksrc_ctrl = value & (0xd8);
\r
845 omap3_prm_clksrc_ctrl_update(s, s->prm_clksrc_ctrl);
\r
846 /* TODO: update SYSCLKSEL bits */
\r
848 case 0x1280: OMAP_RO_REG(addr); break;
\r
849 case 0x1290: s->prm_voltsetup1 = value; break;
\r
850 case 0x1294: s->prm_voltoffset = value & 0xffff; break;
\r
851 case 0x1298: s->prm_clksetup = value & 0xffff; break;
\r
852 case 0x129c: s->prm_polctrl = value & 0xf; break;
\r
853 case 0x12a0: s->prm_voltsetup2 = value & 0xffff; break;
\r
855 case 0x1358: s->rm_rstst_neon &= ~(value & 0xf); break;
\r
856 case 0x13c8: s->pm_wkdep_neon = value & 0x2; break;
\r
857 case 0x13e0: s->pm_pwstctrl_neon = 0x4 | (value & 3); break;
\r
858 case 0x13e4: OMAP_RO_REG(addr); break;
\r
859 case 0x13e8: s->pm_prepwstst_neon = value & 3; break;
\r
861 case 0x1458: s->rm_rstst_usbhost &= ~(value & 0xf); break;
\r
862 case 0x14a0: s->pm_wken_usbhost = value & 1; break;
\r
863 case 0x14a4: s->pm_mpugrpsel_usbhost = value & 1; break;
\r
864 case 0x14a8: s->pm_iva2grpsel_usbhost = value & 1; break;
\r
865 case 0x14b0: s->pm_wkst_usbhost &= ~(value & 1); break;
\r
866 case 0x14c8: s->pm_wkdep_usbhost = value & 0x17; break;
\r
867 case 0x14e0: s->pm_pwstctrl_usbhost = 0x030104 | (value & 0x13); break;
\r
868 case 0x14e4: OMAP_RO_REG(addr); break;
\r
869 case 0x14e8: s->pm_prepwstst_usbhost = value & 3; break;
\r
871 OMAP_BAD_REGV(addr, value);
\r
876 static CPUReadMemoryFunc *omap3_prm_readfn[] = {
\r
877 omap_badwidth_read32,
\r
878 omap_badwidth_read32,
\r
882 static CPUWriteMemoryFunc *omap3_prm_writefn[] = {
\r
883 omap_badwidth_write32,
\r
884 omap_badwidth_write32,
\r
888 struct omap3_prm_s *omap3_prm_init(struct omap_target_agent_s *ta,
\r
889 qemu_irq mpu_int, qemu_irq dsp_int,
\r
891 struct omap_mpu_state_s *mpu)
\r
894 struct omap3_prm_s *s = (struct omap3_prm_s *) qemu_mallocz(sizeof(*s));
\r
896 s->irq[0] = mpu_int;
\r
897 s->irq[1] = dsp_int;
\r
898 s->irq[2] = iva_int;
\r
900 omap3_prm_reset(s);
\r
902 iomemtype = l4_register_io_memory(0, omap3_prm_readfn,
\r
903 omap3_prm_writefn, s);
\r
904 omap_l4_attach(ta, 0, iomemtype);
\r
905 omap_l4_attach(ta, 1, iomemtype);
\r
914 struct omap_mpu_state_s *mpu;
\r
916 /*IVA2_CM Register */
\r
917 uint32_t cm_fclken_iva2; /*0x4800 4000 */
\r
918 uint32_t cm_clken_pll_iva2; /*0x4800 4004 */
\r
919 uint32_t cm_idlest_iva2; /*0x4800 4020 */
\r
920 uint32_t cm_idlest_pll_iva2; /*0x4800 4024 */
\r
921 uint32_t cm_autoidle_pll_iva2; /*0x4800 4034 */
\r
922 uint32_t cm_clksel1_pll_iva2; /*0x4800 4040 */
\r
923 uint32_t cm_clksel2_pll_iva2; /*0x4800 4044 */
\r
924 uint32_t cm_clkstctrl_iva2; /*0x4800 4048 */
\r
925 uint32_t cm_clkstst_iva2; /*0x4800 404c */
\r
927 /*OCP_System_Reg_CM */
\r
928 uint32_t cm_revision; /*0x4800 4800 */
\r
929 uint32_t cm_sysconfig; /*0x4800 4810 */
\r
931 /*MPU_CM Register */
\r
932 uint32_t cm_clken_pll_mpu; /*0x4800 4904 */
\r
933 uint32_t cm_idlest_mpu; /*0x4800 4920 */
\r
934 uint32_t cm_idlest_pll_mpu; /*0x4800 4924 */
\r
935 uint32_t cm_autoidle_pll_mpu; /*0x4800 4934 */
\r
936 uint32_t cm_clksel1_pll_mpu; /*0x4800 4940 */
\r
937 uint32_t cm_clksel2_pll_mpu; /*0x4800 4944 */
\r
938 uint32_t cm_clkstctrl_mpu; /*0x4800 4948 */
\r
939 uint32_t cm_clkstst_mpu; /*0x4800 494c */
\r
941 /*CORE_CM Register */
\r
942 uint32_t cm_fclken1_core; /*0x4800 4a00 */
\r
943 uint32_t cm_fclken3_core; /*0x4800 4a08 */
\r
944 uint32_t cm_iclken1_core; /*0x4800 4a10 */
\r
945 uint32_t cm_iclken2_core; /*0x4800 4a14 */
\r
946 uint32_t cm_iclken3_core; /*0x4800 4a18 */
\r
947 uint32_t cm_idlest1_core; /*0x4800 4a20 */
\r
948 uint32_t cm_idlest2_core; /*0x4800 4a24 */
\r
949 uint32_t cm_idlest3_core; /*0x4800 4a28 */
\r
950 uint32_t cm_autoidle1_core; /*0x4800 4a30 */
\r
951 uint32_t cm_autoidle2_core; /*0x4800 4a34 */
\r
952 uint32_t cm_autoidle3_core; /*0x4800 4a38 */
\r
953 uint32_t cm_clksel_core; /*0x4800 4a40 */
\r
954 uint32_t cm_clkstctrl_core; /*0x4800 4a48 */
\r
955 uint32_t cm_clkstst_core; /*0x4800 4a4c */
\r
957 /*SGX_CM Register */
\r
958 uint32_t cm_fclken_sgx; /*0x4800 4b00 */
\r
959 uint32_t cm_iclken_sgx; /*0x4800 4b10 */
\r
960 uint32_t cm_idlest_sgx; /*0x4800 4b20 */
\r
961 uint32_t cm_clksel_sgx; /*0x4800 4b40 */
\r
962 uint32_t cm_sleepdep_sgx; /*0x4800 4b44 */
\r
963 uint32_t cm_clkstctrl_sgx; /*0x4800 4b48 */
\r
964 uint32_t cm_clkstst_sgx; /*0x4800 4b4c */
\r
966 /*WKUP_CM Register */
\r
967 uint32_t cm_fclken_wkup; /*0x4800 4c00 */
\r
968 uint32_t cm_iclken_wkup; /*0x4800 4c10 */
\r
969 uint32_t cm_idlest_wkup; /*0x4800 4c20 */
\r
970 uint32_t cm_autoidle_wkup; /*0x4800 4c30 */
\r
971 uint32_t cm_clksel_wkup; /*0x4800 4c40 */
\r
972 uint32_t cm_c48; /*0x4800 4c48 */
\r
974 /*Clock_Control_Reg_CM Register */
\r
975 uint32_t cm_clken_pll; /*0x4800 4d00 */
\r
976 uint32_t cm_clken2_pll; /*0x4800 4d04 */
\r
977 uint32_t cm_idlest_ckgen; /*0x4800 4d20 */
\r
978 uint32_t cm_idlest2_ckgen; /*0x4800 4d24 */
\r
979 uint32_t cm_autoidle_pll; /*0x4800 4d30 */
\r
980 uint32_t cm_autoidle2_pll; /*0x4800 4d34 */
\r
981 uint32_t cm_clksel1_pll; /*0x4800 4d40 */
\r
982 uint32_t cm_clksel2_pll; /*0x4800 4d44 */
\r
983 uint32_t cm_clksel3_pll; /*0x4800 4d48 */
\r
984 uint32_t cm_clksel4_pll; /*0x4800 4d4c */
\r
985 uint32_t cm_clksel5_pll; /*0x4800 4d50 */
\r
986 uint32_t cm_clkout_ctrl; /*0x4800 4d70 */
\r
988 /*DSS_CM Register */
\r
989 uint32_t cm_fclken_dss; /*0x4800 4e00 */
\r
990 uint32_t cm_iclken_dss; /*0x4800 4e10 */
\r
991 uint32_t cm_idlest_dss; /*0x4800 4e20 */
\r
992 uint32_t cm_autoidle_dss; /*0x4800 4e30 */
\r
993 uint32_t cm_clksel_dss; /*0x4800 4e40 */
\r
994 uint32_t cm_sleepdep_dss; /*0x4800 4e44 */
\r
995 uint32_t cm_clkstctrl_dss; /*0x4800 4e48 */
\r
996 uint32_t cm_clkstst_dss; /*0x4800 4e4c */
\r
999 /*CAM_CM Register */
\r
1000 uint32_t cm_fclken_cam; /*0x4800 4f00 */
\r
1001 uint32_t cm_iclken_cam; /*0x4800 4f10 */
\r
1002 uint32_t cm_idlest_cam; /*0x4800 4f20 */
\r
1003 uint32_t cm_autoidle_cam; /*0x4800 4f30 */
\r
1004 uint32_t cm_clksel_cam; /*0x4800 4f40 */
\r
1005 uint32_t cm_sleepdep_cam; /*0x4800 4f44 */
\r
1006 uint32_t cm_clkstctrl_cam; /*0x4800 4f48 */
\r
1007 uint32_t cm_clkstst_cam; /*0x4800 4f4c */
\r
1009 /*PER_CM Register */
\r
1010 uint32_t cm_fclken_per; /*0x4800 5000 */
\r
1011 uint32_t cm_iclken_per; /*0x4800 5010 */
\r
1012 uint32_t cm_idlest_per; /*0x4800 5020 */
\r
1013 uint32_t cm_autoidle_per; /*0x4800 5030 */
\r
1014 uint32_t cm_clksel_per; /*0x4800 5040 */
\r
1015 uint32_t cm_sleepdep_per; /*0x4800 5044 */
\r
1016 uint32_t cm_clkstctrl_per; /*0x4800 5048 */
\r
1017 uint32_t cm_clkstst_per; /*0x4800 504c */
\r
1019 /*EMU_CM Register */
\r
1020 uint32_t cm_clksel1_emu; /*0x4800 5140 */
\r
1021 uint32_t cm_clkstctrl_emu; /*0x4800 5148 */
\r
1022 uint32_t cm_clkstst_emu; /*0x4800 514c */
\r
1023 uint32_t cm_clksel2_emu; /*0x4800 5150 */
\r
1024 uint32_t cm_clksel3_emu; /*0x4800 5154 */
\r
1026 /*Global_Reg_CM Register */
\r
1027 uint32_t cm_polctrl; /*0x4800 529c */
\r
1029 /*NEON_CM Register */
\r
1030 uint32_t cm_idlest_neon; /*0x4800 5320 */
\r
1031 uint32_t cm_clkstctrl_neon; /*0x4800 5348 */
\r
1033 /*USBHOST_CM Register */
\r
1034 uint32_t cm_fclken_usbhost; /*0x4800 5400 */
\r
1035 uint32_t cm_iclken_usbhost; /*0x4800 5410 */
\r
1036 uint32_t cm_idlest_usbhost; /*0x4800 5420 */
\r
1037 uint32_t cm_autoidle_usbhost; /*0x4800 5430 */
\r
1038 uint32_t cm_sleepdep_usbhost; /*0x4800 5444 */
\r
1039 uint32_t cm_clkstctrl_usbhost; /*0x4800 5448 */
\r
1040 uint32_t cm_clkstst_usbhost; /*0x4800 544c */
\r
1045 static inline void omap3_cm_fclken_wkup_update(struct omap3_cm_s *s,
\r
1050 omap_clk_onoff(omap_findclk(s->mpu,"omap3_wkup_32k_fclk"), 1);
\r
1052 omap_clk_onoff(omap_findclk(s->mpu,"omap3_wkup_32k_fclk"), 0);
\r
1055 omap_clk_onoff(omap_findclk(s->mpu,"omap3_gp1_fclk"), 1);
\r
1057 omap_clk_onoff(omap_findclk(s->mpu,"omap3_gp1_fclk"), 0);
\r
1060 static inline void omap3_cm_iclken_wkup_update(struct omap3_cm_s *s,
\r
1065 omap_clk_onoff(omap_findclk(s->mpu,"omap3_wkup_l4_iclk"), 1);
\r
1067 omap_clk_onoff(omap_findclk(s->mpu,"omap3_wkup_l4_iclk"), 0);
\r
1071 static inline void omap3_cm_clksel_wkup_update(struct omap3_cm_s *s,
\r
1074 omap_clk gp1_fclk = omap_findclk(s->mpu, "omap3_gp1_fclk");
\r
1077 omap_clk_reparent(gp1_fclk, omap_findclk(s->mpu, "omap3_sys_clk"));
\r
1079 omap_clk_reparent(gp1_fclk, omap_findclk(s->mpu, "omap3_32k_fclk"));
\r
1080 /*Tell GPTIMER to generate new clk rate */
\r
1081 omap_gp_timer_change_clk(s->mpu->gptimer[0]);
\r
1083 TRACE("omap3_gp1_fclk %lld",
\r
1084 omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp1_fclk")));
\r
1086 /*TODO:CM_USIM_CLK CLKSEL_RM */
\r
1089 static inline void omap3_cm_mpu_update(struct omap3_cm_s *s)
\r
1091 uint32_t m, n, divide, m2, cm_clken_pll_mpu;
\r
1092 uint32_t bypass = 1;
\r
1094 cm_clken_pll_mpu = s->cm_clken_pll_mpu;
\r
1095 omap_clk mpu_clk = omap_findclk(s->mpu, "omap3_mpu_clk");
\r
1097 if ((cm_clken_pll_mpu & 0x7) == 0x5)
\r
1101 else if ((cm_clken_pll_mpu & 0x7) == 0x7)
\r
1103 m = (s->cm_clksel1_pll_mpu & 0x7ff00) >> 8;
\r
1104 if ((m == 0) || (m == 1))
\r
1112 divide = (s->cm_clksel1_pll_mpu & 0x380000) >> 19;
\r
1113 //OMAP3_DEBUG(("divide %d\n",divide));
\r
1114 omap_clk_reparent(mpu_clk, omap_findclk(s->mpu, "omap3_core_clk"));
\r
1115 omap_clk_setrate(mpu_clk, divide, 1);
\r
1120 n = (s->cm_clksel1_pll_mpu & 0x7F);
\r
1121 m2 = (s->cm_clksel2_pll_mpu & 0x1F);
\r
1122 //OMAP3_DEBUG(("M %d N %d M2 %d \n",m,n,m2 ));
\r
1123 omap_clk_reparent(mpu_clk, omap_findclk(s->mpu, "omap3_sys_clk"));
\r
1124 omap_clk_setrate(mpu_clk, (n + 1) * m2, m);
\r
1125 //OMAP3_DEBUG(("mpu %d \n",omap_clk_getrate(mpu_clk)));
\r
1130 static inline void omap3_cm_iva2_update(struct omap3_cm_s *s)
\r
1132 uint32_t m, n, divide, m2, cm_clken_pll_iva2;
\r
1133 uint32_t bypass = 1;
\r
1135 cm_clken_pll_iva2 = s->cm_clken_pll_iva2;
\r
1136 omap_clk iva2_clk = omap_findclk(s->mpu, "omap3_iva2_clk");
\r
1138 if (((cm_clken_pll_iva2 & 0x7) == 0x5)
\r
1139 || ((cm_clken_pll_iva2 & 0x7) == 0x1))
\r
1143 else if ((cm_clken_pll_iva2 & 0x7) == 0x7)
\r
1145 m = (s->cm_clksel1_pll_iva2 & 0x7ff00) >> 8;
\r
1146 if ((m == 0) || (m == 1))
\r
1154 divide = (s->cm_clksel1_pll_iva2 & 0x380000) >> 19;
\r
1155 //OMAP3_DEBUG(("divide %d\n",divide));
\r
1156 omap_clk_reparent(iva2_clk, omap_findclk(s->mpu, "omap3_core_clk"));
\r
1157 omap_clk_setrate(iva2_clk, divide, 1);
\r
1162 n = (s->cm_clksel1_pll_iva2 & 0x7F);
\r
1163 m2 = (s->cm_clksel2_pll_iva2 & 0x1F);
\r
1164 //OMAP3_DEBUG(("M %d N %d M2 %d \n",m,n,m2 ));
\r
1165 omap_clk_reparent(iva2_clk, omap_findclk(s->mpu, "omap3_sys_clk"));
\r
1166 omap_clk_setrate(iva2_clk, (n + 1) * m2, m);
\r
1167 //OMAP3_DEBUG(("iva2_clk %d \n",omap_clk_getrate(iva2_clk)));
\r
1173 static inline void omap3_cm_dpll3_update(struct omap3_cm_s *s)
\r
1175 uint32_t m, n, m2, m3, cm_clken_pll;
\r
1176 uint32_t bypass = 1;
\r
1178 cm_clken_pll = s->cm_clken_pll;
\r
1180 /*dpll3 bypass mode. parent clock is always omap3_sys_clk */
\r
1181 if (((cm_clken_pll & 0x7) == 0x5) || ((cm_clken_pll & 0x7) == 0x6))
\r
1185 else if ((cm_clken_pll & 0x7) == 0x7)
\r
1187 m = (s->cm_clksel1_pll & 0x7ff0000) >> 16;
\r
1188 if ((m == 0) || (m == 1))
\r
1195 omap_clk_setrate(omap_findclk(s->mpu, "omap3_core_clk"), 1, 1);
\r
1196 omap_clk_setrate(omap_findclk(s->mpu, "omap3_core2_clk"), 1, 1);
\r
1197 omap_clk_setrate(omap_findclk(s->mpu, "omap3_emu_core_alwon_clk"), 1,
\r
1202 n = (s->cm_clksel1_pll & 0x3f00) >> 8;
\r
1203 m2 = (s->cm_clksel1_pll & 0xf8000000) >> 27;
\r
1204 m3 = (s->cm_clksel1_emu & 0x1f0000) >> 16;
\r
1206 if (s->cm_clksel2_emu&0x80000)
\r
1208 /*override control of DPLL3*/
\r
1209 m = (s->cm_clksel2_emu&0x7ff)>>8;
\r
1210 n = s->cm_clksel2_emu&0x7f;
\r
1211 TRACE("DPLL3 override, m 0x%x n 0x%x",m,n);
\r
1214 //OMAP3_DEBUG(("dpll3 cm_clksel1_pll %x m %d n %d m2 %d m3 %d\n",s->cm_clksel1_pll,m,n,m2,m3 ));
\r
1215 omap_clk_setrate(omap_findclk(s->mpu, "omap3_core_clk"), (n + 1) * m2,
\r
1217 omap_clk_setrate(omap_findclk(s->mpu, "omap3_core2_clk"), (n + 1) * m2,
\r
1219 omap_clk_setrate(omap_findclk(s->mpu, "omap3_emu_core_alwon_clk"),
\r
1220 (n + 1) * m3, m * 2);
\r
1221 TRACE("coreclk %lld",
\r
1222 omap_clk_getrate(omap_findclk(s->mpu, "omap3_core_clk")));
\r
1229 static inline void omap3_cm_dpll4_update(struct omap3_cm_s *s)
\r
1231 uint32_t m, n, m2, m3, m4, m5, m6, cm_clken_pll;
\r
1232 cm_clken_pll = s->cm_clken_pll;
\r
1233 uint32_t bypass = 1;
\r
1235 /*dpll3 bypass mode. parent clock is always omap3_sys_clk */
\r
1237 if ((cm_clken_pll & 0x70000) == 0x10000)
\r
1241 else if ((cm_clken_pll & 0x70000) == 0x70000)
\r
1243 m = (s->cm_clksel2_pll & 0x7ff00) >> 8;
\r
1244 if ((m == 0) || (m == 1))
\r
1251 omap_clk_setrate(omap_findclk(s->mpu, "omap3_96m_fclk"), 1, 1);
\r
1252 omap_clk_setrate(omap_findclk(s->mpu, "omap3_54m_fclk"), 1, 1);
\r
1253 omap_clk_setrate(omap_findclk(s->mpu, "omap3_dss1_alwon_fclk"), 1, 1);
\r
1254 omap_clk_setrate(omap_findclk(s->mpu, "omap3_cam_mclk"), 1, 1);
\r
1255 omap_clk_setrate(omap_findclk(s->mpu, "omap3_per_alwon_clk"), 1, 1);
\r
1259 n = (s->cm_clksel2_pll & 0x7f);
\r
1260 m2 = s->cm_clksel3_pll & 0x1f;
\r
1261 m3 = (s->cm_clksel_dss & 0x1f00) >> 8;
\r
1262 m4 = s->cm_clksel_dss & 0x1f;
\r
1263 m5 = s->cm_clksel_cam & 0x1f;
\r
1264 m6 = (s->cm_clksel1_emu & 0x1f000000) >> 24;
\r
1266 if (s->cm_clksel3_emu&0x80000)
\r
1268 /*override control of DPLL4*/
\r
1269 m = (s->cm_clksel3_emu&0x7ff)>>8;
\r
1270 n = s->cm_clksel3_emu&0x7f;
\r
1271 TRACE("DPLL4 override, m 0x%x n 0x%x",m,n);
\r
1275 //OMAP3_DEBUG(("dpll4 m %d n %d m2 %d m3 %d m4 %d m5 %d m6 %d \n",m,n,m2,m3,m4,m5,m6 ));
\r
1276 omap_clk_setrate(omap_findclk(s->mpu, "omap3_96m_fclk"), (n + 1) * m2,
\r
1278 omap_clk_setrate(omap_findclk(s->mpu, "omap3_54m_fclk"), (n + 1) * m3,
\r
1280 omap_clk_setrate(omap_findclk(s->mpu, "omap3_dss1_alwon_fclk"),
\r
1281 (n + 1) * m4, m * 2);
\r
1282 omap_clk_setrate(omap_findclk(s->mpu, "omap3_cam_mclk"), (n + 1) * m5,
\r
1284 omap_clk_setrate(omap_findclk(s->mpu, "omap3_per_alwon_clk"),
\r
1285 (n + 1) * m6, m * 2);
\r
1287 TRACE("omap3_96m_fclk %lld",
\r
1288 omap_clk_getrate(omap_findclk(s->mpu, "omap3_96m_fclk")));
\r
1289 TRACE("omap3_54m_fclk %lld",
\r
1290 omap_clk_getrate(omap_findclk(s->mpu, "omap3_54m_fclk")));
\r
1291 TRACE("omap3_dss1_alwon_fclk %lld",
\r
1292 omap_clk_getrate(omap_findclk(s->mpu, "omap3_dss1_alwon_fclk")));
\r
1293 TRACE("omap3_cam_mclk %lld",
\r
1294 omap_clk_getrate(omap_findclk(s->mpu, "omap3_cam_mclk")));
\r
1295 TRACE("omap3_per_alwon_clk %lld",
\r
1296 omap_clk_getrate(omap_findclk(s->mpu, "omap3_per_alwon_clk")));
\r
1297 TRACE("omap3_48m_fclk %lld",
\r
1298 omap_clk_getrate(omap_findclk(s->mpu, "omap3_48m_fclk")));
\r
1299 TRACE("omap3_12m_fclk %lld",
\r
1300 omap_clk_getrate(omap_findclk(s->mpu, "omap3_12m_fclk")));
\r
1304 static inline void omap3_cm_dpll5_update(struct omap3_cm_s *s)
\r
1306 uint32_t m, n, m2, cm_idlest2_ckgen;
\r
1307 uint32_t bypass = 1;
\r
1309 cm_idlest2_ckgen = s->cm_idlest2_ckgen;;
\r
1311 /*dpll5 bypass mode */
\r
1312 if ((cm_idlest2_ckgen & 0x1) == 0x0)
\r
1319 omap_clk_setrate(omap_findclk(s->mpu, "omap3_120m_fclk"), 1, 1);
\r
1323 m = (s->cm_clksel4_pll & 0x7ff00)>>8;
\r
1324 n = s->cm_clksel4_pll & 0x3f00;
\r
1325 m2 = s->cm_clksel5_pll & 0x1f;
\r
1327 TRACE("dpll5 m %d n %d m2 %d",m,n,m2);
\r
1328 omap_clk_setrate(omap_findclk(s->mpu, "omap3_120m_fclk"), (n + 1) * m2,
\r
1330 TRACE("omap3_120m_fclk %lld",
\r
1331 omap_clk_getrate(omap_findclk(s->mpu, "omap3_120m_fclk")));
\r
1336 static inline void omap3_cm_48m_update(struct omap3_cm_s *s)
\r
1338 if (s->cm_clksel1_pll & 0x8)
\r
1340 /*parent is sysaltclk */
\r
1341 omap_clk_reparent(omap_findclk(s->mpu, "omap3_48m_fclk"),
\r
1342 omap_findclk(s->mpu, "omap3_sys_altclk"));
\r
1343 omap_clk_reparent(omap_findclk(s->mpu, "omap3_12m_fclk"),
\r
1344 omap_findclk(s->mpu, "omap3_sys_altclk"));
\r
1345 /*TODO:need to set rate ? */
\r
1350 omap_clk_reparent(omap_findclk(s->mpu, "omap3_12m_fclk"),
\r
1351 omap_findclk(s->mpu, "omap3_96m_fclk"));
\r
1352 omap_clk_reparent(omap_findclk(s->mpu, "omap3_48m_fclk"),
\r
1353 omap_findclk(s->mpu, "omap3_96m_fclk"));
\r
1354 omap_clk_setrate(omap_findclk(s->mpu, "omap3_48m_fclk"), 2, 1);
\r
1355 omap_clk_setrate(omap_findclk(s->mpu, "omap3_12m_fclk"), 8, 1);
\r
1361 static inline void omap3_cm_gp10_update(struct omap3_cm_s *s)
\r
1363 omap_clk gp10_fclk = omap_findclk(s->mpu, "omap3_gp10_fclk");
\r
1365 if (s->cm_clksel_core & 0x40)
\r
1366 omap_clk_reparent(gp10_fclk, omap_findclk(s->mpu, "omap3_sys_clk"));
\r
1368 omap_clk_reparent(gp10_fclk, omap_findclk(s->mpu, "omap3_32k_fclk"));
\r
1370 /*Tell GPTIMER10 to generate new clk rate */
\r
1371 omap_gp_timer_change_clk(s->mpu->gptimer[9]);
\r
1372 TRACE("omap3_gp10_fclk %lld",
\r
1373 omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp10_fclk")));
\r
1376 static inline void omap3_cm_gp11_update(struct omap3_cm_s *s)
\r
1378 omap_clk gp11_fclk = omap_findclk(s->mpu, "omap3_gp11_fclk");
\r
1380 if (s->cm_clksel_core & 0x80)
\r
1381 omap_clk_reparent(gp11_fclk, omap_findclk(s->mpu, "omap3_sys_clk"));
\r
1383 omap_clk_reparent(gp11_fclk, omap_findclk(s->mpu, "omap3_32k_fclk"));
\r
1384 /*Tell GPTIMER11 to generate new clk rate */
\r
1385 omap_gp_timer_change_clk(s->mpu->gptimer[10]);
\r
1386 TRACE("omap3_gp11_fclk %lld",
\r
1387 omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp11_fclk")));
\r
1390 static inline void omap3_cm_l3clk_update(struct omap3_cm_s *s)
\r
1392 omap_clk l3_iclk = omap_findclk(s->mpu, "omap3_l3_iclk");
\r
1393 if ((s->cm_clksel_core & 0x3) == 0x1)
\r
1394 omap_clk_setrate(l3_iclk, 1, 1);
\r
1395 else if ((s->cm_clksel_core & 0x3) == 0x2)
\r
1396 omap_clk_setrate(l3_iclk, 2, 1);
\r
1399 static inline void omap3_cm_l4clk_update(struct omap3_cm_s *s)
\r
1401 omap_clk l4_iclk = omap_findclk(s->mpu, "omap3_l4_iclk");
\r
1402 if ((s->cm_clksel_core & 0xc) == 0x4)
\r
1403 omap_clk_setrate(l4_iclk, 1, 1);
\r
1404 else if ((s->cm_clksel_core & 0xc) == 0x8)
\r
1405 omap_clk_setrate(l4_iclk, 2, 1);
\r
1408 static inline void omap3_cm_per_gptimer_update(struct omap3_cm_s *s)
\r
1410 uint32_t cm_clksel_per = s->cm_clksel_per;
\r
1412 if (cm_clksel_per & 0x1)
\r
1413 omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp2_fclk"),
\r
1414 omap_findclk(s->mpu, "omap3_sys_clk"));
\r
1416 omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp2_fclk"),
\r
1417 omap_findclk(s->mpu, "omap3_32k_fclk"));
\r
1418 omap_gp_timer_change_clk(s->mpu->gptimer[1]);
\r
1420 if (cm_clksel_per & 0x2)
\r
1421 omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp3_fclk"),
\r
1422 omap_findclk(s->mpu, "omap3_sys_clk"));
\r
1424 omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp3_fclk"),
\r
1425 omap_findclk(s->mpu, "omap3_32k_fclk"));
\r
1426 omap_gp_timer_change_clk(s->mpu->gptimer[2]);
\r
1428 if (cm_clksel_per & 0x4)
\r
1429 omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp4_fclk"),
\r
1430 omap_findclk(s->mpu, "omap3_sys_clk"));
\r
1432 omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp4_fclk"),
\r
1433 omap_findclk(s->mpu, "omap3_32k_fclk"));
\r
1434 omap_gp_timer_change_clk(s->mpu->gptimer[3]);
\r
1436 if (cm_clksel_per & 0x8)
\r
1437 omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp5_fclk"),
\r
1438 omap_findclk(s->mpu, "omap3_sys_clk"));
\r
1440 omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp5_fclk"),
\r
1441 omap_findclk(s->mpu, "omap3_32k_fclk"));
\r
1442 omap_gp_timer_change_clk(s->mpu->gptimer[4]);
\r
1444 if (cm_clksel_per & 0x10)
\r
1445 omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp6_fclk"),
\r
1446 omap_findclk(s->mpu, "omap3_sys_clk"));
\r
1448 omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp6_fclk"),
\r
1449 omap_findclk(s->mpu, "omap3_32k_fclk"));
\r
1450 omap_gp_timer_change_clk(s->mpu->gptimer[5]);
\r
1452 if (cm_clksel_per & 0x20)
\r
1453 omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp7_fclk"),
\r
1454 omap_findclk(s->mpu, "omap3_sys_clk"));
\r
1456 omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp7_fclk"),
\r
1457 omap_findclk(s->mpu, "omap3_32k_fclk"));
\r
1458 omap_gp_timer_change_clk(s->mpu->gptimer[6]);
\r
1461 if (cm_clksel_per & 0x40)
\r
1462 omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp8_fclk"),
\r
1463 omap_findclk(s->mpu, "omap3_sys_clk"));
\r
1465 omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp8_fclk"),
\r
1466 omap_findclk(s->mpu, "omap3_32k_fclk"));
\r
1467 omap_gp_timer_change_clk(s->mpu->gptimer[7]);
\r
1469 if (cm_clksel_per & 0x80)
\r
1470 omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp9_fclk"),
\r
1471 omap_findclk(s->mpu, "omap3_sys_clk"));
\r
1473 omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp9_fclk"),
\r
1474 omap_findclk(s->mpu, "omap3_32k_fclk"));
\r
1475 omap_gp_timer_change_clk(s->mpu->gptimer[8]);
\r
1477 /*TODO:Tell GPTIMER to generate new clk rate */
\r
1478 TRACE("omap3_gp2_fclk %lld",
\r
1479 omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp2_fclk")));
\r
1480 TRACE("omap3_gp3_fclk %lld",
\r
1481 omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp3_fclk")));
\r
1482 TRACE("omap3_gp4_fclk %lld",
\r
1483 omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp4_fclk")));
\r
1484 TRACE("omap3_gp5_fclk %lld",
\r
1485 omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp5_fclk")));
\r
1486 TRACE("omap3_gp6_fclk %lld",
\r
1487 omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp6_fclk")));
\r
1488 TRACE("omap3_gp7_fclk %lld",
\r
1489 omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp7_fclk")));
\r
1490 TRACE("omap3_gp8_fclk %lld",
\r
1491 omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp8_fclk")));
\r
1492 TRACE("omap3_gp9_fclk %lld",
\r
1493 omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp9_fclk")));
\r
1496 static inline void omap3_cm_clkout2_update(struct omap3_cm_s *s)
\r
1500 if (!s->cm_clkout_ctrl&0x80)
\r
1503 switch (s->cm_clkout_ctrl&0x3)
\r
1506 omap_clk_reparent(omap_findclk(s->mpu, "omap3_sys_clkout2"),
\r
1507 omap_findclk(s->mpu, "omap3_core_clk"));
\r
1510 omap_clk_reparent(omap_findclk(s->mpu, "omap3_sys_clkout2"),
\r
1511 omap_findclk(s->mpu, "omap3_sys_clk"));
\r
1514 omap_clk_reparent(omap_findclk(s->mpu, "omap3_sys_clkout2"),
\r
1515 omap_findclk(s->mpu, "omap3_96m_fclk"));
\r
1518 omap_clk_reparent(omap_findclk(s->mpu, "omap3_sys_clkout2"),
\r
1519 omap_findclk(s->mpu, "omap3_54m_fclk"));
\r
1523 divor = (s->cm_clkout_ctrl&0x31)>>3;
\r
1525 omap_clk_setrate(omap_findclk(s->mpu, "omap3_sys_clkout2"), divor, 1);
\r
1529 static void omap3_cm_reset(struct omap3_cm_s *s)
\r
1531 s->cm_fclken_iva2 = 0x0;
\r
1532 s->cm_clken_pll_iva2 = 0x11;
\r
1533 s->cm_idlest_iva2 = 0x1;
\r
1534 s->cm_idlest_pll_iva2 = 0x0;
\r
1535 s->cm_autoidle_pll_iva2 = 0x0;
\r
1536 s->cm_clksel1_pll_iva2 = 0x80000;
\r
1537 s->cm_clksel2_pll_iva2 = 0x1;
\r
1538 s->cm_clkstctrl_iva2 = 0x0;
\r
1539 s->cm_clkstst_iva2 = 0x0;
\r
1541 s->cm_revision = 0x10;
\r
1542 s->cm_sysconfig = 0x1;
\r
1544 s->cm_clken_pll_mpu = 0x15;
\r
1545 s->cm_idlest_mpu = 0x1;
\r
1546 s->cm_idlest_pll_mpu = 0x0;
\r
1547 s->cm_autoidle_pll_mpu = 0x0;
\r
1548 s->cm_clksel1_pll_mpu = 0x80000;
\r
1549 s->cm_clksel2_pll_mpu = 0x1;
\r
1550 s->cm_clkstctrl_mpu = 0x0;
\r
1551 s->cm_clkstst_mpu = 0x0;
\r
1553 s->cm_fclken1_core = 0x0;
\r
1554 s->cm_fclken3_core = 0x0;
\r
1555 s->cm_iclken1_core = 0x42;
\r
1556 s->cm_iclken2_core = 0x0;
\r
1557 s->cm_iclken3_core = 0x0;
\r
1558 /*allow access to devices*/
\r
1559 s->cm_idlest1_core = 0x0;
\r
1560 s->cm_idlest2_core = 0x0;
\r
1561 /*ide status =0 */
\r
1562 s->cm_idlest3_core = 0xa;
\r
1563 s->cm_autoidle1_core = 0x0;
\r
1564 s->cm_autoidle2_core = 0x0;
\r
1565 s->cm_autoidle3_core = 0x0;
\r
1566 s->cm_clksel_core = 0x105;
\r
1567 s->cm_clkstctrl_core = 0x0;
\r
1568 s->cm_clkstst_core = 0x0;
\r
1570 s->cm_fclken_sgx = 0x0;
\r
1571 s->cm_iclken_sgx = 0x0;
\r
1572 s->cm_idlest_sgx = 0x1;
\r
1573 s->cm_clksel_sgx = 0x0;
\r
1574 s->cm_sleepdep_sgx = 0x0;
\r
1575 s->cm_clkstctrl_sgx = 0x0;
\r
1576 s->cm_clkstst_sgx = 0x0;
\r
1578 s->cm_fclken_wkup = 0x0;
\r
1579 s->cm_iclken_wkup = 0x0;
\r
1580 /*assume all clock can be accessed*/
\r
1581 s->cm_idlest_wkup = 0x0;
\r
1582 s->cm_autoidle_wkup = 0x0;
\r
1583 s->cm_clksel_wkup = 0x12;
\r
1585 s->cm_clken_pll = 0x110015;
\r
1586 s->cm_clken2_pll = 0x11;
\r
1587 s->cm_idlest_ckgen = 0x0;
\r
1588 s->cm_idlest2_ckgen = 0x0;
\r
1589 s->cm_autoidle_pll = 0x0;
\r
1590 s->cm_autoidle2_pll = 0x0;
\r
1591 s->cm_clksel1_pll = 0x8000040;
\r
1592 s->cm_clksel2_pll = 0x0;
\r
1593 s->cm_clksel3_pll = 0x1;
\r
1594 s->cm_clksel4_pll = 0x0;
\r
1595 s->cm_clksel5_pll = 0x1;
\r
1596 s->cm_clkout_ctrl = 0x3;
\r
1599 s->cm_fclken_dss = 0x0;
\r
1600 s->cm_iclken_dss = 0x0;
\r
1601 /*dss can be accessed*/
\r
1602 s->cm_idlest_dss = 0x0;
\r
1603 s->cm_autoidle_dss = 0x0;
\r
1604 s->cm_clksel_dss = 0x1010;
\r
1605 s->cm_sleepdep_dss = 0x0;
\r
1606 s->cm_clkstctrl_dss = 0x0;
\r
1607 s->cm_clkstst_dss = 0x0;
\r
1609 s->cm_fclken_cam = 0x0;
\r
1610 s->cm_iclken_cam = 0x0;
\r
1611 s->cm_idlest_cam = 0x1;
\r
1612 s->cm_autoidle_cam = 0x0;
\r
1613 s->cm_clksel_cam = 0x10;
\r
1614 s->cm_sleepdep_cam = 0x0;
\r
1615 s->cm_clkstctrl_cam = 0x0;
\r
1616 s->cm_clkstst_cam = 0x0;
\r
1618 s->cm_fclken_per = 0x0;
\r
1619 s->cm_iclken_per = 0x0;
\r
1620 //s->cm_idlest_per = 0x3ffff;
\r
1621 s->cm_idlest_per = 0x0; //enable GPIO access
\r
1622 s->cm_autoidle_per = 0x0;
\r
1623 s->cm_clksel_per = 0x0;
\r
1624 s->cm_sleepdep_per = 0x0;
\r
1625 s->cm_clkstctrl_per = 0x0;
\r
1626 s->cm_clkstst_per = 0x0;
\r
1628 s->cm_clksel1_emu = 0x10100a50;
\r
1629 s->cm_clkstctrl_emu = 0x2;
\r
1630 s->cm_clkstst_emu = 0x0;
\r
1631 s->cm_clksel2_emu = 0x0;
\r
1632 s->cm_clksel3_emu = 0x0;
\r
1634 s->cm_polctrl = 0x0;
\r
1636 s->cm_idlest_neon = 0x1;
\r
1637 s->cm_clkstctrl_neon = 0x0;
\r
1639 s->cm_fclken_usbhost = 0x0;
\r
1640 s->cm_iclken_usbhost = 0x0;
\r
1641 s->cm_idlest_usbhost = 0x3;
\r
1642 s->cm_autoidle_usbhost = 0x0;
\r
1643 s->cm_sleepdep_usbhost = 0x0;
\r
1644 s->cm_clkstctrl_usbhost = 0x0;
\r
1645 s->cm_clkstst_usbhost = 0x0;
\r
1648 static uint32_t omap3_cm_read(void *opaque, target_phys_addr_t addr)
\r
1650 struct omap3_cm_s *s = (struct omap3_cm_s *) opaque;
\r
1652 uint32_t bypass = 0, m;
\r
1654 TRACE("%04x", addr);
\r
1658 return s->cm_fclken_iva2;
\r
1660 return s->cm_clken_pll_iva2;
\r
1662 return s->cm_idlest_iva2;
\r
1664 if (((s->cm_clken_pll_iva2 & 0x7) == 0x5)
\r
1665 || ((s->cm_clken_pll_iva2 & 0x7) == 0x1))
\r
1669 else if ((s->cm_clken_pll_iva2 & 0x7) == 0x7)
\r
1671 m = (s->cm_clksel1_pll_iva2 & 0x7ff00) >> 8;
\r
1672 if ((m == 0) || (m == 1))
\r
1682 return s->cm_autoidle_pll_iva2;
\r
1684 return s->cm_clksel1_pll_iva2;
\r
1686 return s->cm_clksel2_pll_iva2;
\r
1688 return s->cm_clkstctrl_iva2;
\r
1690 return s->cm_clkstst_iva2;
\r
1693 return s->cm_revision;
\r
1695 return s->cm_sysconfig;
\r
1698 case 0x904: /*CM_CLKEN_PLL_MPU */
\r
1699 return s->cm_clken_pll_mpu;
\r
1701 return s->cm_idlest_mpu & 0x0; /*MPU is active*/
\r
1703 if ((s->cm_clken_pll_mpu & 0x7) == 0x5)
\r
1707 else if ((s->cm_clken_pll_mpu & 0x7) == 0x7)
\r
1709 m = (s->cm_clksel1_pll_mpu & 0x7ff00) >> 8;
\r
1710 if ((m == 0) || (m == 1))
\r
1720 return s->cm_autoidle_pll_mpu;
\r
1722 return s->cm_clksel1_pll_mpu;
\r
1724 return s->cm_clksel2_pll_mpu;
\r
1726 return s->cm_clkstctrl_mpu;
\r
1728 return s->cm_clkstst_mpu;
\r
1733 return s->cm_fclken1_core;
\r
1735 return s->cm_fclken3_core;
\r
1737 return s->cm_iclken1_core;
\r
1739 return s->cm_iclken2_core;
\r
1741 return s->cm_idlest1_core;
\r
1743 return s->cm_idlest2_core;
\r
1745 return s->cm_idlest3_core;
\r
1747 return s->cm_autoidle1_core;
\r
1749 return s->cm_autoidle2_core;
\r
1751 return s->cm_autoidle3_core;
\r
1752 case 0xa40: /*CM_CLKSEL_CORE */
\r
1753 return s->cm_clksel_core;
\r
1755 return s->cm_clkstctrl_core;
\r
1757 return s->cm_clkstst_core;
\r
1760 return s->cm_fclken_sgx;
\r
1762 return s->cm_iclken_sgx;
\r
1764 return s->cm_idlest_sgx&0x0;
\r
1765 case 0xb40: /*CM_CLKSEL_SGX */
\r
1766 return s->cm_clksel_sgx;
\r
1768 return s->cm_clkstctrl_sgx;
\r
1770 return s->cm_clkstst_sgx;
\r
1773 case 0xc00: /*CM_FCLKEN_WKUP */
\r
1774 return s->cm_fclken_wkup;
\r
1775 case 0xc10: /*CM_ICLKEN_WKUP */
\r
1776 return s->cm_iclken_wkup;
\r
1777 case 0xc20: /*CM_IDLEST_WKUP */
\r
1778 /*TODO: Check whether the timer can be accessed. */
\r
1781 return s->cm_idlest_wkup;
\r
1783 return s->cm_clksel_wkup;
\r
1788 case 0xd00: /*CM_CLKEN_PLL */
\r
1789 return s->cm_clken_pll;
\r
1791 return s->cm_clken2_pll;
\r
1793 /*FIXME: all clock is active. we do not care it. */
\r
1798 if (((s->cm_clken_pll & 0x7) == 0x5) || ((s->cm_clken_pll & 0x7) == 0x6))
\r
1800 else if ((s->cm_clken_pll & 0x7) == 0x7) {
\r
1801 m = (s->cm_clksel1_pll & 0x7ff0000) >> 16;
\r
1802 if ((m == 0) || (m == 1))
\r
1812 if ((s->cm_clken_pll & 0x70000) == 0x10000)
\r
1814 else if ((s->cm_clken_pll & 0x70000) == 0x70000) {
\r
1815 m = (s->cm_clksel2_pll & 0x7ff00) >> 8;
\r
1816 if ((m == 0) || (m == 1))
\r
1826 return s->cm_idlest2_ckgen;
\r
1828 return s->cm_autoidle_pll;
\r
1830 return s->cm_autoidle2_pll;
\r
1831 case 0xd40: /*CM_CLKSEL1_PLL */
\r
1832 return s->cm_clksel1_pll;
\r
1834 return s->cm_clksel2_pll;
\r
1835 case 0xd48: /*CM_CLKSEL3_PLL */
\r
1836 return s->cm_clksel3_pll;
\r
1838 return s->cm_clksel4_pll;
\r
1839 case 0xd50: /*CM_CLKSEL5_PLL */
\r
1840 return s->cm_clksel5_pll;
\r
1842 return s->cm_clkout_ctrl;
\r
1846 return s->cm_fclken_dss;
\r
1848 return s->cm_iclken_dss;
\r
1850 return s->cm_idlest_dss;
\r
1852 return s->cm_autoidle_dss;
\r
1854 return s->cm_clksel_dss;
\r
1856 return s->cm_sleepdep_dss;
\r
1858 return s->cm_clkstctrl_dss;
\r
1860 return s->cm_clkstst_dss;
\r
1864 return s->cm_fclken_cam;
\r
1866 return s->cm_iclken_cam;
\r
1868 return s->cm_idlest_cam&0x0;
\r
1870 return s->cm_autoidle_cam;
\r
1872 return s->cm_clksel_cam;
\r
1874 return s->cm_sleepdep_cam;
\r
1876 return s->cm_clkstctrl_cam;
\r
1878 return s->cm_clkstst_cam;
\r
1882 return s->cm_fclken_per;
\r
1884 return s->cm_iclken_per;
\r
1886 return s->cm_idlest_per ;
\r
1888 return s->cm_autoidle_per;
\r
1890 return s->cm_clksel_per;
\r
1892 return s->cm_sleepdep_per;
\r
1894 return s->cm_clkstctrl_per;
\r
1896 return s->cm_clkstst_per;
\r
1899 case 0x1140: /*CM_CLKSEL1_EMU */
\r
1900 return s->cm_clksel1_emu;
\r
1902 return s->cm_clkstctrl_emu;
\r
1904 return s->cm_clkstst_emu&0x0;
\r
1906 return s->cm_clksel2_emu;
\r
1908 return s->cm_clksel3_emu;
\r
1911 return s->cm_polctrl;
\r
1914 return s->cm_idlest_neon&0x0;
\r
1916 return s->cm_clkstctrl_neon;
\r
1919 return s->cm_fclken_usbhost;
\r
1921 return s->cm_iclken_usbhost;
\r
1923 return s->cm_idlest_usbhost&0x0;
\r
1925 return s->cm_autoidle_usbhost;
\r
1927 return s->cm_sleepdep_usbhost;
\r
1929 return s->cm_clkstctrl_usbhost;
\r
1931 return s->cm_clkstst_usbhost;
\r
1934 printf("omap3_cm_read addr %x pc %x \n", addr, cpu_single_env->regs[15] );
\r
1940 static void omap3_cm_write(void *opaque, target_phys_addr_t addr,
\r
1943 struct omap3_cm_s *s = (struct omap3_cm_s *) opaque;
\r
1945 TRACE("%04x = %08x", addr, value);
\r
1961 case 0xc20: /*CM_IDLEST_WKUP */
\r
1974 OMAP_RO_REG(addr);
\r
1979 s->cm_fclken_iva2 = value & 0x1;
\r
1981 case 0x4: /*CM_CLKEN_PLL_IVA2 */
\r
1982 s->cm_clken_pll_iva2 = value & 0x7ff;
\r
1983 omap3_cm_iva2_update(s);
\r
1986 s->cm_autoidle_pll_iva2 = value & 0x7;
\r
1989 s->cm_clksel1_pll_iva2 = value & 0x3fff7f;
\r
1990 //printf("value %x s->cm_clksel1_pll_iva2 %x \n",value,s->cm_clksel1_pll_iva2);
\r
1991 omap3_cm_iva2_update(s);
\r
1994 s->cm_clksel2_pll_iva2 = value & 0x1f;
\r
1995 omap3_cm_iva2_update(s);
\r
1998 s->cm_clkstctrl_iva2 = value& 0x3;
\r
2002 s->cm_sysconfig = value & 0x1;
\r
2006 case 0x904: /*CM_CLKEN_PLL_MPU */
\r
2007 s->cm_clken_pll_mpu = value & 0x7ff;
\r
2008 omap3_cm_mpu_update(s);
\r
2011 s->cm_autoidle_pll_mpu = value & 0x7;
\r
2014 //printf("s->cm_clksel1_pll_mpu %x\n",s->cm_clksel1_pll_mpu );
\r
2015 s->cm_clksel1_pll_mpu = value & 0x3fff7f;
\r
2016 omap3_cm_mpu_update(s);
\r
2019 s->cm_clksel2_pll_mpu = value & 0x1f;
\r
2020 omap3_cm_mpu_update(s);
\r
2023 s->cm_clkstctrl_mpu = value & 0x3;
\r
2028 s->cm_fclken1_core = value & 0x43fffe00;
\r
2031 s->cm_fclken3_core = value & 0x7;
\r
2034 s->cm_iclken1_core = value & 0x7ffffed2;
\r
2037 s->cm_iclken2_core = value & 0x1f;
\r
2040 s->cm_iclken3_core = value & 0x2;
\r
2043 s->cm_autoidle1_core = value & 0x7ffffed0;
\r
2046 s->cm_autoidle2_core = value & 0x1f;
\r
2049 s->cm_autoidle3_core = value & 0x2;
\r
2051 case 0xa40: /*CM_CLKSEL_CORE */
\r
2052 s->cm_clksel_core = (value & 0xff);
\r
2053 s->cm_clksel_core |= 0x100;
\r
2054 omap3_cm_gp10_update(s);
\r
2055 omap3_cm_gp11_update(s);
\r
2056 omap3_cm_l3clk_update(s);
\r
2057 omap3_cm_l4clk_update(s);
\r
2060 s->cm_clkstctrl_core = value & 0xf;
\r
2064 s->cm_fclken_sgx = value &0x2;
\r
2067 s->cm_iclken_sgx = value & 0x1;
\r
2069 case 0xb40: /*CM_CLKSEL_SGX */
\r
2070 /*TODO: SGX Clock!! */
\r
2071 s->cm_clksel_sgx = value;
\r
2074 s->cm_sleepdep_sgx = value &0x2;
\r
2077 s->cm_clkstctrl_sgx = value & 0x3;
\r
2081 case 0xc00: /*CM_FCLKEN_WKUP */
\r
2082 s->cm_fclken_wkup = value & 0x2e9;
\r
2084 case 0xc10: /*CM_ICLKEN_WKUP */
\r
2085 s->cm_iclken_wkup = value & 0x2ff;
\r
2088 s->cm_autoidle_wkup = value & 0x23f;
\r
2090 case 0xc40: /*CM_CLKSEL_WKUP */
\r
2091 s->cm_clksel_wkup = value & 0x7f;
\r
2092 omap3_cm_clksel_wkup_update(s, s->cm_clksel_wkup);
\r
2096 case 0xd00: /*CM_CLKEN_PLL */
\r
2097 s->cm_clken_pll = value & 0xffff17ff;
\r
2098 omap3_cm_dpll3_update(s);
\r
2099 omap3_cm_dpll4_update(s);
\r
2102 s->cm_clken2_pll = value & 0x7ff;
\r
2105 s->cm_autoidle_pll = value & 0x3f;
\r
2108 s->cm_autoidle2_pll = value & 0x7;
\r
2110 case 0xd40: /*CM_CLKSEL1_PLL */
\r
2111 //OMAP3_DEBUG(("WD40 value %x \n",value));
\r
2112 s->cm_clksel1_pll = value & 0xffffbffc;
\r
2113 //OMAP3_DEBUG(("WD40 value %x \n",value));
\r
2114 omap3_cm_dpll3_update(s);
\r
2115 omap3_cm_48m_update(s);
\r
2118 s->cm_clksel2_pll = value & 0x7ff7f;
\r
2119 omap3_cm_dpll4_update(s);
\r
2121 case 0xd48: /*CM_CLKSEL3_PLL */
\r
2122 s->cm_clksel3_pll = value & 0x1f;
\r
2123 omap3_cm_dpll4_update(s);
\r
2125 case 0xd4c: /*CM_CLKSEL4_PLL */
\r
2126 s->cm_clksel4_pll = value & 0x7ff7f;
\r
2127 omap3_cm_dpll5_update(s);
\r
2129 case 0xd50: /*CM_CLKSEL5_PLL */
\r
2130 s->cm_clksel5_pll = value & 0x1f;
\r
2131 omap3_cm_dpll5_update(s);
\r
2134 s->cm_clkout_ctrl = value & 0xbb;
\r
2135 omap3_cm_clkout2_update(s);
\r
2139 s->cm_fclken_dss = value & 0x7;
\r
2142 s->cm_iclken_dss = value & 0x1;
\r
2145 s->cm_autoidle_dss = value & 0x1;
\r
2148 s->cm_clksel_dss = value & 0x1f1f;
\r
2149 omap3_cm_dpll4_update(s);
\r
2152 s->cm_sleepdep_dss = value & 0x7;
\r
2155 s->cm_clkstctrl_dss = value & 0x3;
\r
2159 s->cm_fclken_cam = value & 0x3;
\r
2162 s->cm_iclken_cam = value & 0x1;
\r
2165 s->cm_autoidle_cam = value & 0x1;
\r
2168 s->cm_clksel_cam = value & 0x1f;
\r
2169 omap3_cm_dpll4_update(s);
\r
2172 s->cm_sleepdep_cam = value & 0x2;
\r
2175 s->cm_clkstctrl_cam = value & 0x3;
\r
2179 s->cm_fclken_per = value & 0x3ffff;
\r
2182 s->cm_iclken_per = value & 0x3ffff;
\r
2186 s->cm_autoidle_per = value &0x3ffff;
\r
2189 s->cm_clksel_per = value & 0xff;
\r
2190 omap3_cm_per_gptimer_update(s);
\r
2193 s->cm_sleepdep_per = value & 0x6;
\r
2196 s->cm_clkstctrl_per = value &0x7;
\r
2199 case 0x1140: /*CM_CLKSEL1_EMU */
\r
2200 s->cm_clksel1_emu = value & 0x1f1f3fff;
\r
2201 //printf("cm_clksel1_emu %x\n",s->cm_clksel1_emu);
\r
2202 omap3_cm_dpll3_update(s);
\r
2203 omap3_cm_dpll4_update(s);
\r
2206 s->cm_clkstctrl_emu = value & 0x3;
\r
2209 s->cm_clksel2_emu = value & 0xfff7f;
\r
2210 omap3_cm_dpll3_update(s);
\r
2213 s->cm_clksel3_emu = value & 0xfff7f;
\r
2214 omap3_cm_dpll4_update(s);
\r
2218 s->cm_polctrl = value & 0x1;
\r
2222 s->cm_clkstctrl_neon = value & 0x3;
\r
2226 s->cm_fclken_usbhost = value & 0x3;
\r
2229 s->cm_iclken_usbhost = value & 0x1;
\r
2232 s->cm_autoidle_usbhost = value & 0x1;
\r
2235 s->cm_sleepdep_usbhost = value & 0x6;
\r
2238 s->cm_clkstctrl_usbhost = value & 0x3;
\r
2242 printf("omap3_cm_write addr %x value %x pc %x\n", addr, value,cpu_single_env->regs[15] );
\r
2249 static CPUReadMemoryFunc *omap3_cm_readfn[] = {
\r
2250 omap_badwidth_read32,
\r
2251 omap_badwidth_read32,
\r
2255 static CPUWriteMemoryFunc *omap3_cm_writefn[] = {
\r
2256 omap_badwidth_write32,
\r
2257 omap_badwidth_write32,
\r
2261 struct omap3_cm_s *omap3_cm_init(struct omap_target_agent_s *ta,
\r
2262 qemu_irq mpu_int, qemu_irq dsp_int,
\r
2263 qemu_irq iva_int, struct omap_mpu_state_s *mpu)
\r
2266 struct omap3_cm_s *s = (struct omap3_cm_s *) qemu_mallocz(sizeof(*s));
\r
2268 s->irq[0] = mpu_int;
\r
2269 s->irq[1] = dsp_int;
\r
2270 s->irq[2] = iva_int;
\r
2272 omap3_cm_reset(s);
\r
2274 iomemtype = l4_register_io_memory(0, omap3_cm_readfn, omap3_cm_writefn, s);
\r
2275 omap_l4_attach(ta, 0, iomemtype);
\r
2276 omap_l4_attach(ta, 1, iomemtype);
\r
2281 #define OMAP3_SEC_WDT 1
\r
2282 #define OMAP3_MPU_WDT 2
\r
2283 #define OMAP3_IVA2_WDT 3
\r
2284 /*omap3 watchdog timer*/
\r
2285 struct omap3_wdt_s
\r
2287 qemu_irq irq; /*IVA2 IRQ */
\r
2288 struct omap_mpu_state_s *mpu;
\r
2295 //int64_t ticks_per_sec;
\r
2297 uint32_t wd_sysconfig;
\r
2298 uint32_t wd_sysstatus;
\r
2308 /*pre and ptv in wclr */
\r
2313 uint16_t writeh; /* LSB */
\r
2314 uint16_t readh; /* MSB */
\r
2322 static inline void omap3_wdt_timer_update(struct omap3_wdt_s *wdt_timer)
\r
2325 if (wdt_timer->active)
\r
2327 expires = muldiv64(0xffffffffll - wdt_timer->wcrr,
\r
2328 ticks_per_sec, wdt_timer->rate);
\r
2329 qemu_mod_timer(wdt_timer->timer, wdt_timer->time + expires);
\r
2332 qemu_del_timer(wdt_timer->timer);
\r
2334 static void omap3_wdt_clk_setup(struct omap3_wdt_s *timer)
\r
2336 /*TODO: Add irq as user to clk */
\r
2339 static inline uint32_t omap3_wdt_timer_read(struct omap3_wdt_s *timer)
\r
2341 uint64_t distance;
\r
2343 if (timer->active)
\r
2345 distance = qemu_get_clock(vm_clock) - timer->time;
\r
2346 distance = muldiv64(distance, timer->rate, ticks_per_sec);
\r
2348 if (distance >= 0xffffffff - timer->wcrr)
\r
2349 return 0xffffffff;
\r
2351 return timer->wcrr + distance;
\r
2354 return timer->wcrr;
\r
2358 static inline void omap3_wdt_timer_sync(struct omap3_wdt_s *timer)
\r
2360 if (timer->active) {
\r
2361 timer->val = omap3_wdt_timer_read(timer);
\r
2362 timer->time = qemu_get_clock(vm_clock);
\r
2366 static void omap3_wdt_reset(struct omap3_wdt_s *s, int wdt_index)
\r
2368 s->wd_sysconfig = 0x0;
\r
2369 s->wd_sysstatus = 0x0;
\r
2374 switch (wdt_index)
\r
2376 case OMAP3_MPU_WDT:
\r
2377 case OMAP3_IVA2_WDT:
\r
2378 s->wldr = 0xfffb0000;
\r
2380 case OMAP3_SEC_WDT:
\r
2381 s->wldr = 0xffa60000;
\r
2388 switch (wdt_index)
\r
2390 case OMAP3_SEC_WDT:
\r
2391 case OMAP3_MPU_WDT:
\r
2394 case OMAP3_IVA2_WDT:
\r
2398 s->pre = s->wclr & (1 << 5);
\r
2399 s->ptv = (s->wclr & 0x1c) >> 2;
\r
2400 s->rate = omap_clk_getrate(s->clk) >> (s->pre ? s->ptv : 0);
\r
2403 s->time = qemu_get_clock(vm_clock);
\r
2404 omap3_wdt_timer_update(s);
\r
2407 static uint32_t omap3_wdt_read32(void *opaque, target_phys_addr_t addr,
\r
2410 struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
\r
2413 //printf("omap3_wdt_read32 addr %x \n",addr);
\r
2416 case 0x10: /*WD_SYSCONFIG */
\r
2417 return s->wd_sysconfig;
\r
2418 case 0x14: /*WD_SYSSTATUS */
\r
2419 return s->wd_sysstatus;
\r
2421 /*WISR*/ return s->wisr & 0x1;
\r
2423 /*WIER*/ return s->wier & 0x1;
\r
2425 /*WCLR*/ return s->wclr & 0x3c;
\r
2427 /*WCRR*/ s->wcrr = omap3_wdt_timer_read(s);
\r
2428 s->time = qemu_get_clock(vm_clock);
\r
2431 /*WLDR*/ return s->wldr;
\r
2433 /*WTGR*/ return s->wtgr;
\r
2435 /*WWPS*/ return s->wwps;
\r
2437 /*WSPR*/ return s->wspr;
\r
2439 printf("omap3_wdt_read32 addr %x \n", addr);
\r
2443 static uint32_t omap3_mpu_wdt_read16(void *opaque, target_phys_addr_t addr)
\r
2445 struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
\r
2452 ret = omap3_wdt_read32(opaque, addr, OMAP3_MPU_WDT);
\r
2453 s->readh = ret >> 16;
\r
2454 return ret & 0xffff;
\r
2457 static uint32_t omap3_mpu_wdt_read32(void *opaque, target_phys_addr_t addr)
\r
2459 return omap3_wdt_read32(opaque, addr, OMAP3_MPU_WDT);
\r
2462 static void omap3_wdt_write32(void *opaque, target_phys_addr_t addr,
\r
2463 uint32_t value, int wdt_index)
\r
2465 struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
\r
2467 //printf("omap3_wdt_write32 addr %x value %x \n",addr,value);
\r
2470 case 0x14: /*WD_SYSSTATUS */
\r
2472 /*WWPS*/ OMAP_RO_REG(addr);
\r
2475 case 0x10: /*WD_SYSCONFIG */
\r
2476 s->wd_sysconfig = value & 0x33f;
\r
2479 /*WISR*/ s->wisr = value & 0x1;
\r
2482 /*WIER*/ s->wier = value & 0x1;
\r
2485 /*WCLR*/ s->wclr = value & 0x3c;
\r
2488 /*WCRR*/ s->wcrr = value;
\r
2489 s->time = qemu_get_clock(vm_clock);
\r
2490 omap3_wdt_timer_update(s);
\r
2493 /*WLDR*/ s->wldr = value; /*It will take effect after next overflow */
\r
2496 /*WTGR*/ if (value != s->wtgr)
\r
2498 s->wcrr = s->wldr;
\r
2499 s->pre = s->wclr & (1 << 5);
\r
2500 s->ptv = (s->wclr & 0x1c) >> 2;
\r
2501 s->rate = omap_clk_getrate(s->clk) >> (s->pre ? s->ptv : 0);
\r
2502 s->time = qemu_get_clock(vm_clock);
\r
2503 omap3_wdt_timer_update(s);
\r
2509 if (((value & 0xffff) == 0x5555) && ((s->wspr & 0xffff) == 0xaaaa))
\r
2512 s->wcrr = omap3_wdt_timer_read(s);
\r
2513 omap3_wdt_timer_update(s);
\r
2515 if (((value & 0xffff) == 0x4444) && ((s->wspr & 0xffff) == 0xbbbb))
\r
2518 s->time = qemu_get_clock(vm_clock);
\r
2519 omap3_wdt_timer_update(s);
\r
2524 printf("omap3_wdt_write32 addr %x \n", addr);
\r
2529 static void omap3_mpu_wdt_write16(void *opaque, target_phys_addr_t addr,
\r
2532 struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
\r
2535 return omap3_wdt_write32(opaque, addr, (value << 16) | s->writeh,
\r
2538 s->writeh = (uint16_t) value;
\r
2540 static void omap3_mpu_wdt_write32(void *opaque, target_phys_addr_t addr,
\r
2543 omap3_wdt_write32(opaque, addr, value, OMAP3_MPU_WDT);
\r
2547 static CPUReadMemoryFunc *omap3_mpu_wdt_readfn[] = {
\r
2548 omap_badwidth_read32,
\r
2549 omap3_mpu_wdt_read16,
\r
2550 omap3_mpu_wdt_read32,
\r
2553 static CPUWriteMemoryFunc *omap3_mpu_wdt_writefn[] = {
\r
2554 omap_badwidth_write32,
\r
2555 omap3_mpu_wdt_write16,
\r
2556 omap3_mpu_wdt_write32,
\r
2561 static void omap3_mpu_wdt_timer_tick(void *opaque)
\r
2563 struct omap3_wdt_s *wdt_timer = (struct omap3_wdt_s *) opaque;
\r
2565 /*TODO:Sent reset pulse to PRCM */
\r
2566 wdt_timer->wcrr = wdt_timer->wldr;
\r
2568 /*after overflow, generate the new wdt_timer->rate */
\r
2569 wdt_timer->pre = wdt_timer->wclr & (1 << 5);
\r
2570 wdt_timer->ptv = (wdt_timer->wclr & 0x1c) >> 2;
\r
2572 omap_clk_getrate(wdt_timer->clk) >> (wdt_timer->pre ? wdt_timer->
\r
2575 wdt_timer->time = qemu_get_clock(vm_clock);
\r
2576 omap3_wdt_timer_update(wdt_timer);
\r
2579 static struct omap3_wdt_s *omap3_mpu_wdt_init(struct omap_target_agent_s *ta,
\r
2580 qemu_irq irq, omap_clk fclk,
\r
2582 struct omap_mpu_state_s *mpu)
\r
2585 struct omap3_wdt_s *s = (struct omap3_wdt_s *) qemu_mallocz(sizeof(*s));
\r
2589 s->timer = qemu_new_timer(vm_clock, omap3_mpu_wdt_timer_tick, s);
\r
2591 omap3_wdt_reset(s, OMAP3_MPU_WDT);
\r
2593 omap3_wdt_clk_setup(s);
\r
2595 iomemtype = l4_register_io_memory(0, omap3_mpu_wdt_readfn,
\r
2596 omap3_mpu_wdt_writefn, s);
\r
2597 omap_l4_attach(ta, 0, iomemtype);
\r
2604 /*dummy system control module*/
\r
2605 struct omap3_scm_s
\r
2607 struct omap_mpu_state_s *mpu;
\r
2609 uint8 interface[48]; /*0x4800 2000*/
\r
2610 uint8 padconfs[576]; /*0x4800 2030*/
\r
2611 uint32 general[228]; /*0x4800 2270*/
\r
2612 uint8 mem_wkup[1024]; /*0x4800 2600*/
\r
2613 uint8 padconfs_wkup[84]; /*0x4800 2a00*/
\r
2614 uint32 general_wkup[8]; /*0x4800 2a60*/
\r
2617 #define PADCONFS_VALUE(wakeup0,wakeup1,offmode0,offmode1, \
\r
2618 inputenable0,inputenable1,pupd0,pupd1,muxmode0,muxmode1,offset) \
\r
2620 *(padconfs+offset/4) = (wakeup0 <<14)|(offmode0<<9)|(inputenable0<<8)|(pupd0<<3)|(muxmode0); \
\r
2621 *(padconfs+offset/4) |= (wakeup1 <<30)|(offmode1<<25)|(inputenable1<<24)|(pupd1<<19)|(muxmode1<<16); \
\r
2625 static void omap3_scm_reset(struct omap3_scm_s *s)
\r
2627 uint32 * padconfs;
\r
2628 padconfs = (uint32 *)(s->padconfs);
\r
2629 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x0);
\r
2630 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x4);
\r
2631 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x8);
\r
2632 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0xc);
\r
2633 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x10);
\r
2634 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x14);
\r
2635 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x18);
\r
2636 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x1c);
\r
2637 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x20);
\r
2638 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x24);
\r
2639 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x28);
\r
2640 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x2c);
\r
2641 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x30);
\r
2642 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x34);
\r
2643 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x38);
\r
2644 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x3c);
\r
2645 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x40);
\r
2646 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x44);
\r
2647 PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,7,0x48);
\r
2648 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x4c);
\r
2649 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x50);
\r
2650 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x54);
\r
2651 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x58);
\r
2652 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,0,0x5c);
\r
2653 PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x60);
\r
2654 PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x64);
\r
2655 PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x68);
\r
2656 PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x6c);
\r
2657 PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x70);
\r
2658 PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x74);
\r
2659 PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x78);
\r
2660 PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x7c);
\r
2661 PADCONFS_VALUE(0,0,0,0,1,1,0,3,0,7,0x80);
\r
2662 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x84);
\r
2663 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x88);
\r
2664 PADCONFS_VALUE(0,0,0,0,1,1,3,0,7,0,0x8c);
\r
2665 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x90);
\r
2666 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x94);
\r
2667 PADCONFS_VALUE(0,0,0,0,1,1,1,0,7,0,0x98);
\r
2668 PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,7,0x9c);
\r
2669 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0xa0);
\r
2670 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0xa4);
\r
2671 PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0xa8);
\r
2672 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xac);
\r
2673 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb0);
\r
2674 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb4);
\r
2675 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb8);
\r
2676 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xbc);
\r
2677 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc0);
\r
2678 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc4);
\r
2679 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc8);
\r
2680 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xcc);
\r
2681 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd0);
\r
2682 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd4);
\r
2683 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd8);
\r
2684 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xdc);
\r
2685 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe0);
\r
2686 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe4);
\r
2687 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe8);
\r
2688 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xec);
\r
2689 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf0);
\r
2690 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf4);
\r
2691 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf8);
\r
2692 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xfc);
\r
2693 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x100);
\r
2694 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x104);
\r
2695 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x108);
\r
2696 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x10c);
\r
2697 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x110);
\r
2698 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x114);
\r
2699 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x118);
\r
2700 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x11c);
\r
2701 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x120);
\r
2702 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x124);
\r
2703 PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x128);
\r
2704 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x12c);
\r
2705 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x130);
\r
2706 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x134);
\r
2707 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x138);
\r
2708 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x13c);
\r
2709 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x140);
\r
2710 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x144);
\r
2711 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x148);
\r
2712 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x14c);
\r
2713 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x150);
\r
2714 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x154);
\r
2715 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x158);
\r
2716 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x15c);
\r
2717 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x160);
\r
2718 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x164);
\r
2719 PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x168);
\r
2720 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x16c);
\r
2721 PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x170);
\r
2722 PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x174);
\r
2723 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x178);
\r
2724 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x17c);
\r
2725 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x180);
\r
2726 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x184);
\r
2727 PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x188);
\r
2728 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x18c);
\r
2729 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x190);
\r
2730 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x194);
\r
2731 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x198);
\r
2732 PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x19c);
\r
2733 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x1a0);
\r
2734 PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1a4);
\r
2735 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x1a8);
\r
2736 PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1ac);
\r
2737 PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1b0);
\r
2738 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1b4);
\r
2739 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1b8);
\r
2740 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1bc);
\r
2741 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c0);
\r
2742 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c4);
\r
2743 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c8);
\r
2744 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1cc);
\r
2745 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d0);
\r
2746 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d4);
\r
2747 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d8);
\r
2748 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1dc);
\r
2749 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e0);
\r
2750 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e4);
\r
2751 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e8);
\r
2752 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1ec);
\r
2753 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f0);
\r
2754 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f4);
\r
2755 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f8);
\r
2756 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1fc);
\r
2757 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x200);
\r
2758 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x204);
\r
2759 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x208);
\r
2760 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x20c);
\r
2761 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x210);
\r
2762 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x214);
\r
2763 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x218);
\r
2764 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x21c);
\r
2765 PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x220);
\r
2766 PADCONFS_VALUE(0,0,0,0,1,1,3,1,0,0,0x224);
\r
2767 PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,0,0x228);
\r
2768 PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,0,0x22c);
\r
2769 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x230);
\r
2770 PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x234);
\r
2773 padconfs = (uint32 *)(s->general);
\r
2774 s->general[1] = 0x4000000; /*0x4800 2274*/
\r
2775 s->general[0x1c] = 0x1; /*0x4800 22e0*/
\r
2776 s->general[0x75] = 0x7fc0; /*0x4800 2444*/
\r
2777 s->general[0x76] = 0xaa; /*0x4800 2448*/
\r
2778 s->general[0x7c] = 0x2700; /*0x4800 2460*/
\r
2779 s->general[0x7d] = 0x300000; /*0x4800 2464*/
\r
2780 s->general[0x7e] = 0x300000; /*0x4800 2468*/
\r
2781 s->general[0x81] = 0xffff; /*0x4800 2474*/
\r
2782 s->general[0x82] = 0xffff; /*0x4800 2478*/
\r
2783 s->general[0x83] = 0xffff; /*0x4800 247c*/
\r
2784 s->general[0x84] = 0x6; /*0x4800 2480*/
\r
2785 s->general[0x85] = 0xffffffff; /*0x4800 2484*/
\r
2786 s->general[0x86] = 0xffff; /*0x4800 2488*/
\r
2787 s->general[0x87] = 0xffff; /*0x4800 248c*/
\r
2788 s->general[0x88] = 0x1; /*0x4800 2490*/
\r
2789 s->general[0x8b] = 0xffffffff; /*0x4800 249c*/
\r
2790 s->general[0x8c] = 0xffff; /*0x4800 24a0*/
\r
2791 s->general[0x8e] = 0xffff; /*0x4800 24a8*/
\r
2792 s->general[0x8f] = 0xffff; /*0x4800 24ac*/
\r
2793 s->general[0x91] = 0xffff; /*0x4800 24b4*/
\r
2794 s->general[0x92] = 0xffff; /*0x4800 24b8*/
\r
2795 s->general[0xac] = 0x109; /*0x4800 2520*/
\r
2796 s->general[0xb2] = 0xffff; /*0x4800 2538*/
\r
2797 s->general[0xb3] = 0xffff; /*0x4800 253c*/
\r
2798 s->general[0xb4] = 0xffff; /*0x4800 2540*/
\r
2799 PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x368);
\r
2800 PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x36c);
\r
2801 PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x370);
\r
2802 PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x374);
\r
2803 PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x378);
\r
2804 PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x37c);
\r
2805 PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x380);
\r
2806 PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x384);
\r
2807 PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x388);
\r
2811 padconfs = (uint32 *)(s->padconfs_wkup);
\r
2812 PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x0);
\r
2813 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x4);
\r
2814 PADCONFS_VALUE(0,0,0,0,1,1,3,0,0,0,0x8);
\r
2815 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0xc);
\r
2816 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x10);
\r
2817 PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x14);
\r
2818 PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x18);
\r
2819 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c);
\r
2820 PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x20);
\r
2821 PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x24);
\r
2822 PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x2c);
\r
2825 s->general_wkup[0] = 0x66ff; /*0x4800 2A60*/
\r
2829 static uint32_t omap3_scm_read8(void *opaque, target_phys_addr_t addr)
\r
2831 struct omap3_scm_s *s = (struct omap3_scm_s *) opaque;
\r
2835 case 0x00 ... 0x2f:
\r
2836 return s->interface[addr];
\r
2837 case 0x30 ... 0x26f:
\r
2838 return s->padconfs[addr-0x30];
\r
2839 case 0x270 ... 0x5ff:
\r
2840 temp = (uint8_t *)s->general;
\r
2841 return temp[addr-0x270];
\r
2842 case 0x600 ... 0x9ff:
\r
2843 return s->mem_wkup[addr-0x600];
\r
2844 case 0xa00 ... 0xa5f:
\r
2845 return s->padconfs_wkup[addr-0xa00];
\r
2846 case 0xa60 ... 0xa7f:
\r
2847 temp = (uint8_t *)s->general_wkup;
\r
2848 return temp[addr-0xa60];
\r
2850 return s->control_status & 0xff;
\r
2852 return (s->control_status & 0xff00) >> 8;
\r
2854 return (s->control_status & 0xff0000) >> 16;
\r
2856 return (s->control_status & 0xff000000) >> 24; */
\r
2861 printf("omap3_scm_read8 addr %x pc %x \n", addr,cpu_single_env->regs[15] );
\r
2865 static uint32_t omap3_scm_read16(void *opaque, target_phys_addr_t addr)
\r
2868 v = omap3_scm_read8(opaque, addr);
\r
2869 v |= omap3_scm_read8(opaque, addr + 1) << 8;
\r
2873 static uint32_t omap3_scm_read32(void *opaque, target_phys_addr_t addr)
\r
2876 v = omap3_scm_read8(opaque, addr);
\r
2877 v |= omap3_scm_read8(opaque, addr + 1) << 8;
\r
2878 v |= omap3_scm_read8(opaque, addr + 2) << 16;
\r
2879 v |= omap3_scm_read8(opaque, addr + 3) << 24;
\r
2883 static void omap3_scm_write8(void *opaque, target_phys_addr_t addr,
\r
2886 struct omap3_scm_s *s = (struct omap3_scm_s *) opaque;
\r
2891 case 0x00 ... 0x2f:
\r
2892 s->interface[addr] = value;
\r
2894 case 0x30 ... 0x26f:
\r
2895 s->padconfs[addr-0x30] = value;
\r
2897 case 0x270 ... 0x5ff:
\r
2898 temp = (uint8_t *)s->general;
\r
2899 temp[addr-0x270] = value;
\r
2901 case 0x600 ... 0x9ff:
\r
2902 s->mem_wkup[addr-0x600] = value;
\r
2904 case 0xa00 ... 0xa5f:
\r
2905 s->padconfs_wkup[addr-0xa00] = value;
\r
2907 case 0xa60 ... 0xa7f:
\r
2908 temp = (uint8_t *)s->general_wkup;
\r
2909 temp[addr-0xa60] = value;
\r
2912 /*we do not care scm write*/
\r
2913 printf("omap3_scm_write8 addr %x pc %x \n \n", addr,
\r
2914 cpu_single_env->regs[15] - 0x80008000 + 0x80e80000);
\r
2920 static void omap3_scm_write16(void *opaque, target_phys_addr_t addr,
\r
2923 omap3_scm_write8(opaque, addr + 0, (value) & 0xff);
\r
2924 omap3_scm_write8(opaque, addr + 1, (value >> 8) & 0xff);
\r
2927 static void omap3_scm_write32(void *opaque, target_phys_addr_t addr,
\r
2930 omap3_scm_write8(opaque, addr + 0, (value) & 0xff);
\r
2931 omap3_scm_write8(opaque, addr + 1, (value >> 8) & 0xff);
\r
2932 omap3_scm_write8(opaque, addr + 2, (value >> 16) & 0xff);
\r
2933 omap3_scm_write8(opaque, addr + 3, (value >> 24) & 0xff);
\r
2936 static CPUReadMemoryFunc *omap3_scm_readfn[] = {
\r
2942 static CPUWriteMemoryFunc *omap3_scm_writefn[] = {
\r
2944 omap3_scm_write16,
\r
2945 omap3_scm_write32,
\r
2948 static struct omap3_scm_s *omap3_scm_init(struct omap_target_agent_s *ta,
\r
2949 struct omap_mpu_state_s *mpu)
\r
2952 struct omap3_scm_s *s = (struct omap3_scm_s *) qemu_mallocz(sizeof(*s));
\r
2956 omap3_scm_reset(s);
\r
2958 iomemtype = l4_register_io_memory(0, omap3_scm_readfn,
\r
2959 omap3_scm_writefn, s);
\r
2960 omap_l4_attach(ta, 0, iomemtype);
\r
2966 /*dummy port protection*/
\r
2969 struct omap_mpu_state_s *mpu;
\r
2971 uint32_t l3_pm_rt_error_log; /*0x6801 0020 */
\r
2972 uint32_t l3_pm_rt_control; /*0x6801 0028 */
\r
2973 uint32_t l3_pm_rt_error_clear_single; /*0x6801 0030 */
\r
2974 uint32_t l3_pm_rt_error_clear_multi; /*0x6801 0038 */
\r
2975 uint32_t l3_pm_rt_req_info_permission[2]; /*0x6801 0048 + (0x20*i) */
\r
2976 uint32_t l3_pm_rt_read_permission[2]; /*0x6801 0050 + (0x20*i) */
\r
2977 uint32_t l3_pm_rt_write_permission[2]; /*0x6801 0058 + (0x20*i) */
\r
2978 uint32_t l3_pm_rt_addr_match[1]; /*0x6801 0060 + (0x20*k) */
\r
2980 uint32_t l3_pm_gpmc_error_log; /*0x6801 2420 */
\r
2981 uint32_t l3_pm_gpmc_control; /*0x6801 2428 */
\r
2982 uint32_t l3_pm_gpmc_error_clear_single; /*0x6801 2430 */
\r
2983 uint32_t l3_pm_gpmc_error_clear_multi; /*0x6801 2438 */
\r
2984 uint32_t l3_pm_gpmc_req_info_permission[8]; /*0x6801 2448 + (0x20*i) */
\r
2985 uint32_t l3_pm_gpmc_read_permission[8]; /*0x6801 2450 + (0x20*i) */
\r
2986 uint32_t l3_pm_gpmc_write_permission[8]; /*0x6801 2458 + (0x20*i) */
\r
2987 uint32_t l3_pm_gpmc_addr_match[7]; /*0x6801 2460 + (0x20*k) */
\r
2989 uint32_t l3_pm_ocmram_error_log; /*0x6801 2820 */
\r
2990 uint32_t l3_pm_ocmram_control; /*0x6801 2828 */
\r
2991 uint32_t l3_pm_ocmram_error_clear_single; /*0x6801 2830 */
\r
2992 uint32_t l3_pm_ocmram_error_clear_multi; /*0x6801 2838 */
\r
2993 uint32_t l3_pm_ocmram_req_info_permission[8]; /*0x6801 2848 + (0x20*i) */
\r
2994 uint32_t l3_pm_ocmram_read_permission[8]; /*0x6801 2850 + (0x20*i) */
\r
2995 uint32_t l3_pm_ocmram_write_permission[8]; /*0x6801 2858 + (0x20*i) */
\r
2996 uint32_t l3_pm_ocmram_addr_match[7]; /*0x6801 2860 + (0x20*k) */
\r
2998 uint32_t l3_pm_ocmrom_error_log; /*0x6801 2c20 */
\r
2999 uint32_t l3_pm_ocmrom_control; /*0x6801 2c28 */
\r
3000 uint32_t l3_pm_ocmrom_error_clear_single; /*0x6801 2c30 */
\r
3001 uint32_t l3_pm_ocmrom_error_clear_multi; /*0x6801 2c38 */
\r
3002 uint32_t l3_pm_ocmrom_req_info_permission[2]; /*0x6801 2c48 + (0x20*i) */
\r
3003 uint32_t l3_pm_ocmrom_read_permission[2]; /*0x6801 2c50 + (0x20*i) */
\r
3004 uint32_t l3_pm_ocmrom_write_permission[2]; /*0x6801 2c58 + (0x20*i) */
\r
3005 uint32_t l3_pm_ocmrom_addr_match[1]; /*0x6801 2c60 + (0x20*k) */
\r
3007 uint32_t l3_pm_mad2d_error_log; /*0x6801 3020 */
\r
3008 uint32_t l3_pm_mad2d_control; /*0x6801 3028 */
\r
3009 uint32_t l3_pm_mad2d_error_clear_single; /*0x6801 3030 */
\r
3010 uint32_t l3_pm_mad2d_error_clear_multi; /*0x6801 3038 */
\r
3011 uint32_t l3_pm_mad2d_req_info_permission[8]; /*0x6801 3048 + (0x20*i) */
\r
3012 uint32_t l3_pm_mad2d_read_permission[8]; /*0x6801 3050 + (0x20*i) */
\r
3013 uint32_t l3_pm_mad2d_write_permission[8]; /*0x6801 3058 + (0x20*i) */
\r
3014 uint32_t l3_pm_mad2d_addr_match[7]; /*0x6801 3060 + (0x20*k) */
\r
3016 uint32_t l3_pm_iva_error_log; /*0x6801 4020 */
\r
3017 uint32_t l3_pm_iva_control; /*0x6801 4028 */
\r
3018 uint32_t l3_pm_iva_error_clear_single; /*0x6801 4030 */
\r
3019 uint32_t l3_pm_iva_error_clear_multi; /*0x6801 4038 */
\r
3020 uint32_t l3_pm_iva_req_info_permission[4]; /*0x6801 4048 + (0x20*i) */
\r
3021 uint32_t l3_pm_iva_read_permission[4]; /*0x6801 4050 + (0x20*i) */
\r
3022 uint32_t l3_pm_iva_write_permission[4]; /*0x6801 4058 + (0x20*i) */
\r
3023 uint32_t l3_pm_iva_addr_match[3]; /*0x6801 4060 + (0x20*k) */
\r
3026 static void omap3_pm_reset(struct omap3_pm_s *s)
\r
3030 s->l3_pm_rt_control = 0x3000000;
\r
3031 s->l3_pm_gpmc_control = 0x3000000;
\r
3032 s->l3_pm_ocmram_control = 0x3000000;
\r
3033 s->l3_pm_ocmrom_control = 0x3000000;
\r
3034 s->l3_pm_mad2d_control = 0x3000000;
\r
3035 s->l3_pm_iva_control = 0x3000000;
\r
3037 s->l3_pm_rt_req_info_permission[0] = 0xffff;
\r
3038 s->l3_pm_rt_req_info_permission[1] = 0x0;
\r
3039 for (i = 3; i < 8; i++)
\r
3040 s->l3_pm_gpmc_req_info_permission[i] = 0xffff;
\r
3041 for (i = 1; i < 8; i++)
\r
3042 s->l3_pm_ocmram_req_info_permission[i] = 0xffff;
\r
3043 s->l3_pm_ocmrom_req_info_permission[1] = 0xffff;
\r
3044 for (i = 1; i < 8; i++)
\r
3045 s->l3_pm_mad2d_req_info_permission[i] = 0xffff;
\r
3046 for (i = 1; i < 4; i++)
\r
3047 s->l3_pm_iva_req_info_permission[i] = 0xffff;
\r
3049 s->l3_pm_rt_read_permission[0] = 0x1406;
\r
3050 s->l3_pm_rt_read_permission[1] = 0x1406;
\r
3051 s->l3_pm_rt_write_permission[0] = 0x1406;
\r
3052 s->l3_pm_rt_write_permission[1] = 0x1406;
\r
3053 for (i = 0; i < 8; i++)
\r
3055 s->l3_pm_gpmc_read_permission[i] = 0x563e;
\r
3056 s->l3_pm_gpmc_write_permission[i] = 0x563e;
\r
3058 for (i = 0; i < 8; i++)
\r
3060 s->l3_pm_ocmram_read_permission[i] = 0x5f3e;
\r
3061 s->l3_pm_ocmram_write_permission[i] = 0x5f3e;
\r
3063 for (i = 0; i < 2; i++)
\r
3065 s->l3_pm_ocmrom_read_permission[i] = 0x1002;
\r
3066 s->l3_pm_ocmrom_write_permission[i] = 0x1002;
\r
3069 for (i = 0; i < 8; i++)
\r
3071 s->l3_pm_mad2d_read_permission[i] = 0x5f1e;
\r
3072 s->l3_pm_mad2d_write_permission[i] = 0x5f1e;
\r
3075 for (i = 0; i < 4; i++)
\r
3077 s->l3_pm_iva_read_permission[i] = 0x140e;
\r
3078 s->l3_pm_iva_write_permission[i] = 0x140e;
\r
3082 s->l3_pm_rt_addr_match[0] = 0x10230;
\r
3084 s->l3_pm_gpmc_addr_match[0] = 0x10230;
\r
3087 static uint32_t omap3_pm_read8(void *opaque, target_phys_addr_t addr)
\r
3089 //struct omap3_pm_s *s = (struct omap3_pm_s *) opaque;
\r
3094 printf("omap3_pm_read8 addr %x \n", addr);
\r
3099 static uint32_t omap3_pm_read16(void *opaque, target_phys_addr_t addr)
\r
3102 v = omap3_pm_read8(opaque, addr);
\r
3103 v |= omap3_pm_read8(opaque, addr + 1) << 8;
\r
3107 static uint32_t omap3_pm_read32(void *opaque, target_phys_addr_t addr)
\r
3110 v = omap3_pm_read8(opaque, addr);
\r
3111 v |= omap3_pm_read8(opaque, addr + 1) << 8;
\r
3112 v |= omap3_pm_read8(opaque, addr + 2) << 16;
\r
3113 v |= omap3_pm_read8(opaque, addr + 3) << 24;
\r
3117 static void omap3_pm_write8(void *opaque, target_phys_addr_t addr,
\r
3120 struct omap3_pm_s *s = (struct omap3_pm_s *) opaque;
\r
3125 case 0x48 ... 0x4b:
\r
3126 case 0x68 ... 0x6b:
\r
3127 i = (addr - 0x48) / 0x20;
\r
3128 s->l3_pm_rt_req_info_permission[i] &=
\r
3129 (~(0xff << ((addr - 0x48 - i * 0x20) * 8)));
\r
3130 s->l3_pm_rt_req_info_permission[i] |=
\r
3131 (value << (addr - 0x48 - i * 0x20) * 8);
\r
3133 case 0x50 ... 0x53:
\r
3134 case 0x70 ... 0x73:
\r
3135 i = (addr - 0x50) / 0x20;
\r
3136 s->l3_pm_rt_read_permission[i] &=
\r
3137 (~(0xff << ((addr - 0x50 - i * 0x20) * 8)));
\r
3138 s->l3_pm_rt_read_permission[i] |=
\r
3139 (value << (addr - 0x50 - i * 0x20) * 8);
\r
3141 case 0x58 ... 0x5b:
\r
3142 case 0x78 ... 0x7b:
\r
3143 i = (addr - 0x58) / 0x20;
\r
3144 s->l3_pm_rt_write_permission[i] &=
\r
3145 (~(0xff << ((addr - 0x58 - i * 0x20) * 8)));
\r
3146 s->l3_pm_rt_write_permission[i] |=
\r
3147 (value << (addr - 0x58 - i * 0x20) * 8);
\r
3149 case 0x60 ... 0x63:
\r
3150 s->l3_pm_rt_addr_match[0] &= (~(0xff << ((addr - 0x60) * 8)));
\r
3151 s->l3_pm_rt_addr_match[0] |= (value << (addr - 0x60) * 8);
\r
3153 case 0x2448 ... 0x244b:
\r
3154 case 0x2468 ... 0x246b:
\r
3155 case 0x2488 ... 0x248b:
\r
3156 case 0x24a8 ... 0x24ab:
\r
3157 case 0x24c8 ... 0x24cb:
\r
3158 case 0x24e8 ... 0x24eb:
\r
3159 case 0x2508 ... 0x250b:
\r
3160 case 0x2528 ... 0x252b:
\r
3161 i = (addr - 0x2448) / 0x20;
\r
3162 s->l3_pm_gpmc_req_info_permission[i] &=
\r
3163 (~(0xff << ((addr - 0x2448 - i * 0x20) * 8)));
\r
3164 s->l3_pm_gpmc_req_info_permission[i] |=
\r
3165 (value << (addr - 0x2448 - i * 0x20) * 8);
\r
3167 case 0x2450 ... 0x2453:
\r
3168 case 0x2470 ... 0x2473:
\r
3169 case 0x2490 ... 0x2493:
\r
3170 case 0x24b0 ... 0x24b3:
\r
3171 case 0x24d0 ... 0x24d3:
\r
3172 case 0x24f0 ... 0x24f3:
\r
3173 case 0x2510 ... 0x2513:
\r
3174 case 0x2530 ... 0x2533:
\r
3175 i = (addr - 0x2450) / 0x20;
\r
3176 s->l3_pm_gpmc_read_permission[i] &=
\r
3177 (~(0xff << ((addr - 0x2450 - i * 0x20) * 8)));
\r
3178 s->l3_pm_gpmc_read_permission[i] |=
\r
3179 (value << (addr - 0x2450 - i * 0x20) * 8);
\r
3181 case 0x2458 ... 0x245b:
\r
3182 case 0x2478 ... 0x247b:
\r
3183 case 0x2498 ... 0x249b:
\r
3184 case 0x24b8 ... 0x24bb:
\r
3185 case 0x24d8 ... 0x24db:
\r
3186 case 0x24f8 ... 0x24fb:
\r
3187 case 0x2518 ... 0x251b:
\r
3188 case 0x2538 ... 0x253b:
\r
3189 i = (addr - 0x2458) / 0x20;
\r
3190 s->l3_pm_gpmc_write_permission[i] &=
\r
3191 (~(0xff << ((addr - 0x2458 - i * 0x20) * 8)));
\r
3192 s->l3_pm_gpmc_write_permission[i] |=
\r
3193 (value << (addr - 0x2458 - i * 0x20) * 8);
\r
3195 case 0x2848 ... 0x284b:
\r
3196 case 0x2868 ... 0x286b:
\r
3197 case 0x2888 ... 0x288b:
\r
3198 case 0x28a8 ... 0x28ab:
\r
3199 case 0x28c8 ... 0x28cb:
\r
3200 case 0x28e8 ... 0x28eb:
\r
3201 case 0x2908 ... 0x290b:
\r
3202 case 0x2928 ... 0x292b:
\r
3203 i = (addr - 0x2848) / 0x20;
\r
3204 s->l3_pm_ocmram_req_info_permission[i] &=
\r
3205 (~(0xff << ((addr - 0x2848 - i * 0x20) * 8)));
\r
3206 s->l3_pm_ocmram_req_info_permission[i] |=
\r
3207 (value << (addr - 0x2848 - i * 0x20) * 8);
\r
3209 case 0x2850 ... 0x2853:
\r
3210 case 0x2870 ... 0x2873:
\r
3211 case 0x2890 ... 0x2893:
\r
3212 case 0x28b0 ... 0x28b3:
\r
3213 case 0x28d0 ... 0x28d3:
\r
3214 case 0x28f0 ... 0x28f3:
\r
3215 case 0x2910 ... 0x2913:
\r
3216 case 0x2930 ... 0x2933:
\r
3217 i = (addr - 0x2850) / 0x20;
\r
3218 s->l3_pm_ocmram_read_permission[i] &=
\r
3219 (~(0xff << ((addr - 0x2850 - i * 0x20) * 8)));
\r
3220 s->l3_pm_ocmram_read_permission[i] |=
\r
3221 (value << (addr - 0x2850 - i * 0x20) * 8);
\r
3223 case 0x2858 ... 0x285b:
\r
3224 case 0x2878 ... 0x287b:
\r
3225 case 0x2898 ... 0x289b:
\r
3226 case 0x28b8 ... 0x28bb:
\r
3227 case 0x28d8 ... 0x28db:
\r
3228 case 0x28f8 ... 0x28fb:
\r
3229 case 0x2918 ... 0x291b:
\r
3230 case 0x2938 ... 0x293b:
\r
3231 i = (addr - 0x2858) / 0x20;
\r
3232 s->l3_pm_ocmram_write_permission[i] &=
\r
3233 (~(0xff << ((addr - 0x2858 - i * 0x20) * 8)));
\r
3234 s->l3_pm_ocmram_write_permission[i] |=
\r
3235 (value << (addr - 0x2858 - i * 0x20) * 8);
\r
3238 case 0x2860 ... 0x2863:
\r
3239 case 0x2880 ... 0x2883:
\r
3240 case 0x28a0 ... 0x28a3:
\r
3241 case 0x28c0 ... 0x28c3:
\r
3242 case 0x28e0 ... 0x28e3:
\r
3243 case 0x2900 ... 0x2903:
\r
3244 case 0x2920 ... 0x2923:
\r
3245 i = (addr - 0x2860) / 0x20;
\r
3246 s->l3_pm_ocmram_addr_match[i] &=
\r
3247 (~(0xff << ((addr - 0x2860 - i * 0x20) * 8)));
\r
3248 s->l3_pm_ocmram_addr_match[i] |=
\r
3249 (value << (addr - 0x2860 - i * 0x20) * 8);
\r
3252 case 0x4048 ... 0x404b:
\r
3253 case 0x4068 ... 0x406b:
\r
3254 case 0x4088 ... 0x408b:
\r
3255 case 0x40a8 ... 0x40ab:
\r
3256 i = (addr - 0x4048) / 0x20;
\r
3257 s->l3_pm_iva_req_info_permission[i] &=
\r
3258 (~(0xff << ((addr - 0x4048 - i * 0x20) * 8)));
\r
3259 s->l3_pm_iva_req_info_permission[i] |=
\r
3260 (value << (addr - 0x4048 - i * 0x20) * 8);
\r
3262 case 0x4050 ... 0x4053:
\r
3263 case 0x4070 ... 0x4073:
\r
3264 case 0x4090 ... 0x4093:
\r
3265 case 0x40b0 ... 0x40b3:
\r
3266 i = (addr - 0x4050) / 0x20;
\r
3267 s->l3_pm_iva_read_permission[i] &=
\r
3268 (~(0xff << ((addr - 0x4050 - i * 0x20) * 8)));
\r
3269 s->l3_pm_iva_read_permission[i] |=
\r
3270 (value << (addr - 0x4050 - i * 0x20) * 8);
\r
3272 case 0x4058 ... 0x405b:
\r
3273 case 0x4078 ... 0x407b:
\r
3274 case 0x4098 ... 0x409b:
\r
3275 case 0x40b8 ... 0x40bb:
\r
3276 i = (addr - 0x4058) / 0x20;
\r
3277 s->l3_pm_iva_write_permission[i] &=
\r
3278 (~(0xff << ((addr - 0x4058 - i * 0x20) * 8)));
\r
3279 s->l3_pm_iva_write_permission[i] |=
\r
3280 (value << (addr - 0x4058 - i * 0x20) * 8);
\r
3283 printf("omap3_pm_write8 addr %x \n", addr);
\r
3288 static void omap3_pm_write16(void *opaque, target_phys_addr_t addr,
\r
3291 omap3_pm_write8(opaque, addr + 0, (value) & 0xff);
\r
3292 omap3_pm_write8(opaque, addr + 1, (value >> 8) & 0xff);
\r
3295 static void omap3_pm_write32(void *opaque, target_phys_addr_t addr,
\r
3298 omap3_pm_write8(opaque, addr + 0, (value) & 0xff);
\r
3299 omap3_pm_write8(opaque, addr + 1, (value >> 8) & 0xff);
\r
3300 omap3_pm_write8(opaque, addr + 2, (value >> 16) & 0xff);
\r
3301 omap3_pm_write8(opaque, addr + 3, (value >> 24) & 0xff);
\r
3304 static CPUReadMemoryFunc *omap3_pm_readfn[] = {
\r
3310 static CPUWriteMemoryFunc *omap3_pm_writefn[] = {
\r
3316 static struct omap3_pm_s *omap3_pm_init(struct omap_mpu_state_s *mpu)
\r
3319 struct omap3_pm_s *s = (struct omap3_pm_s *) qemu_mallocz(sizeof(*s));
\r
3322 //s->base = 0x68010000;
\r
3323 //s->size = 0x4400;
\r
3325 omap3_pm_reset(s);
\r
3327 iomemtype = cpu_register_io_memory(0, omap3_pm_readfn, omap3_pm_writefn, s);
\r
3328 cpu_register_physical_memory(0x68010000, 0x4400, iomemtype);
\r
3333 /*dummy SDRAM Memory Scheduler emulation*/
\r
3334 struct omap3_sms_s
\r
3336 struct omap_mpu_state_s *mpu;
\r
3338 uint32 sms_sysconfig;
\r
3339 uint32 sms_sysstatus;
\r
3340 uint32 sms_rg_att[8];
\r
3341 uint32 sms_rg_rdperm[8];
\r
3342 uint32 sms_rg_wrperm[8];
\r
3343 uint32 sms_rg_start[7];
\r
3344 uint32 sms_rg_end[7];
\r
3345 uint32 sms_security_control;
\r
3346 uint32 sms_class_arbiter0;
\r
3347 uint32 sms_class_arbiter1;
\r
3348 uint32 sms_class_arbiter2;
\r
3349 uint32 sms_interclass_arbiter;
\r
3350 uint32 sms_class_rotation[3];
\r
3351 uint32 sms_err_addr;
\r
3352 uint32 sms_err_type;
\r
3353 uint32 sms_pow_ctrl;
\r
3354 uint32 sms_rot_control[12];
\r
3355 uint32 sms_rot_size[12];
\r
3356 uint32 sms_rot_physical_ba[12];
\r
3361 static uint32_t omap3_sms_read32(void *opaque, target_phys_addr_t addr)
\r
3363 struct omap3_sms_s *s = (struct omap3_sms_s *) opaque;
\r
3368 return s->sms_sysconfig;
\r
3370 return s->sms_sysstatus;
\r
3379 return s->sms_rg_att[(addr-0x48)/0x20];
\r
3388 return s->sms_rg_rdperm[(addr-0x50)/0x20];
\r
3396 return s->sms_rg_wrperm[(addr-0x58)/0x20];
\r
3404 return s->sms_rg_start[(addr-0x60)/0x20];
\r
3413 return s->sms_rg_end[(addr-0x64)/0x20];
\r
3415 return s->sms_security_control;
\r
3417 return s->sms_class_arbiter0;
\r
3419 return s->sms_class_arbiter1;
\r
3421 return s->sms_class_arbiter2;
\r
3423 return s->sms_interclass_arbiter;
\r
3427 return s->sms_class_rotation[(addr-0x164)/4];
\r
3429 return s->sms_err_addr;
\r
3431 return s->sms_err_type;
\r
3433 return s->sms_pow_ctrl;
\r
3446 return s->sms_rot_control[(addr-0x180)/0x10];
\r
3459 return s->sms_rot_size[(addr-0x184)/0x10];
\r
3473 return s->sms_rot_size[(addr-0x188)/0x10];
\r
3476 printf("omap3_sms_read32 addr %x \n", addr);
\r
3481 static void omap3_sms_write32(void *opaque, target_phys_addr_t addr,
\r
3484 struct omap3_sms_s *s = (struct omap3_sms_s *) opaque;
\r
3490 OMAP_RO_REG(addr);
\r
3493 s->sms_sysconfig = value & 0x1f;
\r
3504 s->sms_rg_att[(addr-0x48)/0x20] = value;
\r
3514 s->sms_rg_rdperm[(addr-0x50)/0x20] = value&0xffff;
\r
3523 s->sms_rg_wrperm[(addr-0x58)/0x20] = value&0xffff;
\r
3532 s->sms_rg_start[(addr-0x60)/0x20] = value;
\r
3541 s->sms_rg_end[(addr-0x64)/0x20] = value;
\r
3544 s->sms_security_control = value &0xfffffff;
\r
3547 s->sms_class_arbiter0 = value;
\r
3550 s->sms_class_arbiter1 = value;
\r
3553 s->sms_class_arbiter2 = value;
\r
3556 s->sms_interclass_arbiter = value;
\r
3561 s->sms_class_rotation[(addr-0x164)/4] = value;
\r
3564 s->sms_err_addr = value;
\r
3567 s->sms_err_type = value;
\r
3570 s->sms_pow_ctrl = value;
\r
3584 s->sms_rot_control[(addr-0x180)/0x10] = value;
\r
3598 s->sms_rot_size[(addr-0x184)/0x10] = value;
\r
3613 s->sms_rot_size[(addr-0x188)/0x10] = value;
\r
3616 printf("omap3_sms_write32 addr %x\n", addr);
\r
3621 static CPUReadMemoryFunc *omap3_sms_readfn[] = {
\r
3622 omap_badwidth_read32,
\r
3623 omap_badwidth_read32,
\r
3627 static CPUWriteMemoryFunc *omap3_sms_writefn[] = {
\r
3628 omap_badwidth_write32,
\r
3629 omap_badwidth_write32,
\r
3630 omap3_sms_write32,
\r
3633 static void omap3_sms_reset(struct omap3_sms_s *s)
\r
3635 s->sms_sysconfig = 0x1;
\r
3636 s->sms_class_arbiter0 = 0x500000;
\r
3637 s->sms_class_arbiter1 = 0x500;
\r
3638 s->sms_class_arbiter2 = 0x55000;
\r
3639 s->sms_interclass_arbiter = 0x400040;
\r
3640 s->sms_class_rotation[0] = 0x1;
\r
3641 s->sms_class_rotation[1] = 0x1;
\r
3642 s->sms_class_rotation[2] = 0x1;
\r
3643 s->sms_pow_ctrl = 0x80;
\r
3646 static struct omap3_sms_s *omap3_sms_init(struct omap_mpu_state_s *mpu)
\r
3649 struct omap3_sms_s *s = (struct omap3_sms_s *) qemu_mallocz(sizeof(*s));
\r
3653 omap3_sms_reset(s);
\r
3655 iomemtype = cpu_register_io_memory(0, omap3_sms_readfn,
\r
3656 omap3_sms_writefn, s);
\r
3657 cpu_register_physical_memory(0x6c000000, 0x10000, iomemtype);
\r
3662 static const struct dma_irq_map omap3_dma_irq_map[] = {
\r
3663 {0, OMAP_INT_35XX_SDMA_IRQ0},
\r
3664 {0, OMAP_INT_35XX_SDMA_IRQ1},
\r
3665 {0, OMAP_INT_35XX_SDMA_IRQ2},
\r
3666 {0, OMAP_INT_35XX_SDMA_IRQ3},
\r
3669 static int omap3_validate_addr(struct omap_mpu_state_s *s,
\r
3670 target_phys_addr_t addr)
\r
3676 set the kind of memory connected to GPMC that we are trying to boot form.
\r
3677 Uses SYS BOOT settings.
\r
3679 void omap3_set_mem_type(struct omap_mpu_state_s *s,int bootfrom)
\r
3683 case 0x0: /*GPMC_NOR*/
\r
3684 s->omap3_scm->general[32] |= 7;
\r
3686 case 0x1: /*GPMC_NAND*/
\r
3687 s->omap3_scm->general[32] |= 1;
\r
3690 s->omap3_scm->general[32] |= 8;
\r
3693 s->omap3_scm->general[32] |= 0;
\r
3696 s->omap3_scm->general[32] |= 17;
\r
3699 s->omap3_scm->general[32] |= 3;
\r
3704 void omap3_set_device_type(struct omap_mpu_state_s *s,int device_type)
\r
3706 s->omap3_scm->general[32] |= (device_type & 0x7) << 8;
\r
3709 struct omap_mpu_state_s *omap3530_mpu_init(unsigned long sdram_size,
\r
3710 DisplayState * ds, const char *core)
\r
3712 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
\r
3713 qemu_mallocz(sizeof(struct omap_mpu_state_s));
\r
3714 ram_addr_t sram_base, q2_base;
\r
3715 qemu_irq *cpu_irq;
\r
3716 qemu_irq dma_irqs[4];
\r
3719 //omap_clk gpio_clks[4];
\r
3722 s->mpu_model = omap3530;
\r
3723 s->env = cpu_init("cortex-a8-r2");
\r
3726 fprintf(stderr, "Unable to find CPU definition\n");
\r
3729 s->sdram_size = sdram_size;
\r
3730 s->sram_size = OMAP3530_SRAM_SIZE;
\r
3732 sdindex = drive_get_index(IF_SD, 0, 0);
\r
3733 if (sdindex == -1) {
\r
3734 fprintf(stderr, "qemu: missing SecureDigital device\n");
\r
3741 /* Memory-mapped stuff */
\r
3743 q2_base = qemu_ram_alloc(s->sdram_size);
\r
3744 cpu_register_physical_memory(OMAP3_Q2_BASE, s->sdram_size,
\r
3745 (q2_base | IO_MEM_RAM));
\r
3746 sram_base = qemu_ram_alloc(s->sram_size);
\r
3747 cpu_register_physical_memory(OMAP3_SRAM_BASE, s->sram_size,
\r
3748 (sram_base | IO_MEM_RAM));
\r
3753 s->l4 = omap_l4_init(OMAP3_L4_BASE, sizeof(omap3_l4_agent_info) / sizeof(struct omap_l4_agent_info_s));
\r
3755 cpu_irq = arm_pic_init_cpu(s->env);
\r
3756 s->ih[0] = omap2_inth_init(s, 0x48200000, 0x1000, 3, &s->irq[0],
\r
3757 cpu_irq[ARM_PIC_CPU_IRQ],
\r
3758 cpu_irq[ARM_PIC_CPU_FIQ],
\r
3759 omap_findclk(s, "omap3_mpu_intc_fclk"),
\r
3760 omap_findclk(s, "omap3_mpu_intc_iclk"));
\r
3762 for (i = 0; i < 4; i++)
\r
3764 s->irq[omap3_dma_irq_map[i].ih][omap3_dma_irq_map[i].intr];
\r
3765 s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
\r
3766 omap_findclk(s, "omap3_sdma_fclk"),
\r
3767 omap_findclk(s, "omap3_sdma_iclk"));
\r
3768 s->port->addr_valid = omap3_validate_addr;
\r
3771 /* Register SDRAM and SRAM ports for fast DMA transfers. */
\r
3772 soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
\r
3773 soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
\r
3776 s->omap3_cm = omap3_cm_init(omap3_l4ta_get(s->l4, 1), NULL, NULL, NULL, s);
\r
3778 s->omap3_prm = omap3_prm_init(omap3_l4ta_get(s->l4, 2),
\r
3779 NULL, NULL, NULL, s);
\r
3781 s->omap3_mpu_wdt = omap3_mpu_wdt_init(omap3_l4ta_get(s->l4, 3),
\r
3784 "omap3_wkup_32k_fclk"),
\r
3785 omap_findclk(s, "omap3_wkup_l4_iclk"),
\r
3788 s->omap3_scm = omap3_scm_init(omap3_l4ta_get(s->l4, 0), s);
\r
3790 s->omap3_pm = omap3_pm_init(s);
\r
3791 s->omap3_sms = omap3_sms_init(s);
\r
3793 s->gptimer[0] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 4),
\r
3794 s->irq[0][OMAP_INT_35XX_GPTIMER1],
\r
3795 omap_findclk(s, "omap3_gp1_fclk"),
\r
3796 omap_findclk(s, "omap3_wkup_l4_iclk"));
\r
3797 s->gptimer[1] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 5),
\r
3798 s->irq[0][OMAP_INT_35XX_GPTIMER2],
\r
3799 omap_findclk(s, "omap3_gp2_fclk"),
\r
3800 omap_findclk(s, "omap3_per_l4_iclk"));
\r
3801 s->gptimer[2] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 6),
\r
3802 s->irq[0][OMAP_INT_35XX_GPTIMER3],
\r
3803 omap_findclk(s, "omap3_gp3_fclk"),
\r
3804 omap_findclk(s, "omap3_per_l4_iclk"));
\r
3805 s->gptimer[3] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 7),
\r
3806 s->irq[0][OMAP_INT_35XX_GPTIMER4],
\r
3807 omap_findclk(s, "omap3_gp4_fclk"),
\r
3808 omap_findclk(s, "omap3_per_l4_iclk"));
\r
3809 s->gptimer[4] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 8),
\r
3810 s->irq[0][OMAP_INT_35XX_GPTIMER5],
\r
3811 omap_findclk(s, "omap3_gp5_fclk"),
\r
3812 omap_findclk(s, "omap3_per_l4_iclk"));
\r
3813 s->gptimer[5] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 9),
\r
3814 s->irq[0][OMAP_INT_35XX_GPTIMER6],
\r
3815 omap_findclk(s, "omap3_gp6_fclk"),
\r
3816 omap_findclk(s, "omap3_per_l4_iclk"));
\r
3817 s->gptimer[6] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 10),
\r
3818 s->irq[0][OMAP_INT_35XX_GPTIMER7],
\r
3819 omap_findclk(s, "omap3_gp7_fclk"),
\r
3820 omap_findclk(s, "omap3_per_l4_iclk"));
\r
3821 s->gptimer[7] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 11),
\r
3822 s->irq[0][OMAP_INT_35XX_GPTIMER8],
\r
3823 omap_findclk(s, "omap3_gp8_fclk"),
\r
3824 omap_findclk(s, "omap3_per_l4_iclk"));
\r
3825 s->gptimer[8] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 12),
\r
3826 s->irq[0][OMAP_INT_35XX_GPTIMER9],
\r
3827 omap_findclk(s, "omap3_gp9_fclk"),
\r
3828 omap_findclk(s, "omap3_per_l4_iclk"));
\r
3829 s->gptimer[9] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 13),
\r
3830 s->irq[0][OMAP_INT_35XX_GPTIMER10],
\r
3831 omap_findclk(s, "omap3_gp10_fclk"),
\r
3832 omap_findclk(s, "omap3_core_l4_iclk"));
\r
3833 s->gptimer[10] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 14),
\r
3834 s->irq[0][OMAP_INT_35XX_GPTIMER11],
\r
3835 omap_findclk(s, "omap3_gp12_fclk"),
\r
3836 omap_findclk(s, "omap3_core_l4_iclk"));
\r
3837 s->gptimer[11] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 15),
\r
3838 s->irq[0][OMAP_INT_35XX_GPTIMER12],
\r
3839 omap_findclk(s, "omap3_gp12_fclk"),
\r
3840 omap_findclk(s, "omap3_wkup_l4_iclk"));
\r
3843 omap_synctimer_init(omap3_l4ta_get(s->l4, 16), s,
\r
3844 omap_findclk(s, "omap3_sys_32k"), NULL);
\r
3846 s->sdrc = omap_sdrc_init(0x6d000000);
\r
3848 s->gpmc = omap_gpmc_init(s, 0x6e000000, s->irq[0][OMAP_INT_35XX_GPMC_IRQ]);
\r
3851 s->uart[0] = omap2_uart_init(omap3_l4ta_get(s->l4, 17),
\r
3852 s->irq[0][OMAP_INT_35XX_UART1_IRQ],
\r
3853 omap_findclk(s, "omap3_uart1_fclk"),
\r
3854 omap_findclk(s, "omap3_uart1_iclk"),
\r
3855 s->drq[OMAP35XX_DMA_UART1_TX],
\r
3856 s->drq[OMAP35XX_DMA_UART1_RX], serial_hds[0]);
\r
3857 s->uart[1] = omap2_uart_init(omap3_l4ta_get(s->l4, 18),
\r
3858 s->irq[0][OMAP_INT_35XX_UART2_IRQ],
\r
3859 omap_findclk(s, "omap3_uart2_fclk"),
\r
3860 omap_findclk(s, "omap3_uart2_iclk"),
\r
3861 s->drq[OMAP35XX_DMA_UART2_TX],
\r
3862 s->drq[OMAP35XX_DMA_UART2_RX],
\r
3863 serial_hds[0] ? serial_hds[1] : 0);
\r
3864 s->uart[2] = omap2_uart_init(omap3_l4ta_get(s->l4, 19),
\r
3865 s->irq[0][OMAP_INT_35XX_UART3_IRQ],
\r
3866 omap_findclk(s, "omap3_uart2_fclk"),
\r
3867 omap_findclk(s, "omap3_uart3_iclk"),
\r
3868 s->drq[OMAP35XX_DMA_UART3_TX],
\r
3869 s->drq[OMAP35XX_DMA_UART3_RX],
\r
3871 && serial_hds[1] ? serial_hds[2] : 0);
\r
3873 /*attach serial[0] to uart 2 for beagle board */
\r
3874 omap_uart_attach(s->uart[2], serial_hds[0]);
\r
3876 s->dss = omap_dss_init(omap3_l4ta_get(s->l4, 20), 0x68005400, ds,
\r
3877 s->irq[0][OMAP_INT_35XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
\r
3878 NULL,NULL,NULL,NULL,NULL);
\r
3880 //gpio_clks[0] = NULL;
\r
3881 //gpio_clks[1] = NULL;
\r
3882 //gpio_clks[2] = NULL;
\r
3883 //gpio_clks[3] = NULL;
\r
3885 s->gpif = omap3_gpif_init();
\r
3887 omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 21),
\r
3888 &s->irq[0][OMAP_INT_35XX_GPIO_BANK1],
\r
3891 omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 22),
\r
3892 &s->irq[0][OMAP_INT_35XX_GPIO_BANK2],
\r
3895 omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 23),
\r
3896 &s->irq[0][OMAP_INT_35XX_GPIO_BANK3],
\r
3899 omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 24),
\r
3900 &s->irq[0][OMAP_INT_35XX_GPIO_BANK4],
\r
3904 omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 25),
\r
3905 &s->irq[0][OMAP_INT_35XX_GPIO_BANK5],
\r
3908 omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 26),
\r
3909 &s->irq[0][OMAP_INT_35XX_GPIO_BANK6],
\r
3912 omap_tap_init(omap3_l4ta_get(s->l4, 27), s);
\r
3914 s->omap3_mmc = omap3_mmc_init(omap3_l4ta_get(s->l4, 28), drives_table[sdindex].bdrv,
\r
3915 s->irq[0][OMAP_INT_35XX_MMC1_IRQ],
\r
3916 &s->drq[OMAP35XX_DMA_MMC1_TX],
\r
3917 omap_findclk(s, "omap3_mmc1_fclk"), omap_findclk(s, "omap3_mmc1_iclk"));
\r
3919 s->i2c[0] = omap3_i2c_init(omap3_l4ta_get(s->l4, 31),
\r
3920 s->irq[0][OMAP_INT_35XX_I2C1_IRQ],
\r
3921 &s->drq[OMAP35XX_DMA_I2C1_TX],
\r
3922 omap_findclk(s, "omap3_i2c1_fclk"),
\r
3923 omap_findclk(s, "omap3_i2c1_iclk"),
\r
3925 s->i2c[1] = omap3_i2c_init(omap3_l4ta_get(s->l4, 32),
\r
3926 s->irq[0][OMAP_INT_35XX_I2C2_IRQ],
\r
3927 &s->drq[OMAP35XX_DMA_I2C2_TX],
\r
3928 omap_findclk(s, "omap3_i2c2_fclk"),
\r
3929 omap_findclk(s, "omap3_i2c2_iclk"),
\r
3931 s->i2c[2] = omap3_i2c_init(omap3_l4ta_get(s->l4, 33),
\r
3932 s->irq[0][OMAP_INT_35XX_I2C3_IRQ],
\r
3933 &s->drq[OMAP35XX_DMA_I2C3_TX],
\r
3934 omap_findclk(s, "omap3_i2c3_fclk"),
\r
3935 omap_findclk(s, "omap3_i2c3_iclk"),
\r
projects / qemu / blob