git.maemo.org Git - qemu/blob - hw/omap3.c

   1 /*
   2  * TI OMAP3 processors emulation.
   3  *
   4  * Copyright (C) 2008 yajin <yajin@vm-kernel.org>
   5  * Copyright (C) 2009 Nokia Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 or
  10  * (at your option) version 3 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include "hw.h"
  24 #include "arm-misc.h"
  25 #include "omap.h"
  26 #include "sysemu.h"
  27 #include "qemu-timer.h"
  28 #include "qemu-char.h"
  29 #include "flash.h"
  30 #include "soc_dma.h"
  31 #include "audio/audio.h"
  32 #include "block.h"
  33
  34 //#define OMAP3_DEBUG_
  35
  36 #ifdef OMAP3_DEBUG_
  37 #define TRACE(fmt, ...) fprintf(stderr, "%s " fmt "\n", __FUNCTION__, ##__VA_ARGS__)
  38 #else
  39 #define TRACE(...)
  40 #endif
  41
  42 typedef enum {
  43     /* 68000000-680003FF */ L3ID_L3RT = 0,
  44     /* 68000400-680007FF */ L3ID_L3SI,
  45     /* 68000800-680013FF */
  46     /* 68001400-680017FF */ L3ID_MPUSS_IA,
  47     /* 68001800-68001BFF */ L3ID_IVASS_IA,
  48     /* 68001C00-68001FFF */ L3ID_SGXSS_IA,
  49     /* 68002000-680023FF */ L3ID_SMS_TA,
  50     /* 68002400-680027FF */ L3ID_GPMC_TA,
  51     /* 68002800-68002BFF */ L3ID_OCM_RAM_TA,
  52     /* 68002C00-68002FFF */ L3ID_OCM_ROM_TA,
  53     /* 68003000-680033FF */ L3ID_D2D_IA,
  54     /* 68003400-680037FF */ L3ID_D2D_TA,
  55     /* 68003800-68003FFF */
  56     /* 68004000-680043FF */ L3ID_HSUSB_HOST_IA,
  57     /* 68004400-680047FF */ L3ID_HSUSB_OTG_IA,
  58     /* 68004800-68004BFF */
  59     /* 68004C00-68004FFF */ L3ID_SDMA_RD_IA,
  60     /* 68005000-680053FF */ L3ID_SDMA_WR_IA,
  61     /* 68005400-680057FF */ L3ID_DSS_IA,
  62     /* 68005800-68005BFF */ L3ID_CAMISP_IA,
  63     /* 68005C00-68005FFF */ L3ID_DAP_IA,
  64     /* 68006000-680063FF */ L3ID_IVASS_TA,
  65     /* 68006400-680067FF */ L3ID_SGXSS_TA,
  66     /* 68006800-68006BFF */ L3ID_L4_CORE_TA,
  67     /* 68006C00-68006FFF */ L3ID_L4_PER_TA,
  68     /* 68007000-680073FF */ L3ID_L4_EMU_TA,
  69     /* 68007400-6800FFFF */
  70     /* 68010000-680103FF */ L3ID_RT_PM,
  71     /* 68010400-680123FF */
  72     /* 68012400-680127FF */ L3ID_GPMC_PM,
  73     /* 68012800-68012BFF */ L3ID_OCM_RAM_PM,
  74     /* 68012C00-68012FFF */ L3ID_OCM_ROM_PM,
  75     /* 68013000-680133FF */ L3ID_D2D_PM,
  76     /* 68013400-68013FFF */
  77     /* 68014000-680143FF */ L3ID_IVA_PM,
  78     /* 68014400-68FFFFFF */
  79 } omap3_l3_region_id_t;
  80
  81 struct omap_l3_region_s {
  82     target_phys_addr_t offset;
  83     size_t size;
  84     enum {
  85         L3TYPE_GENERIC = 0, /* needs to be mapped separately */
  86         L3TYPE_IA,          /* initiator agent */
  87         L3TYPE_TA,          /* target agent */
  88         L3TYPE_PM,          /* protection mechanism */
  89         L3TYPE_UNDEFINED,   /* every access will emit an error message */
  90     } type;
  91 };
  92
  93 struct omap3_l3_initiator_agent_s {
  94     target_phys_addr_t base;
  95
  96     uint32_t component;
  97     uint32_t control;
  98     uint32_t status;
  99 };
 100
 101 struct omap3_l3pm_s {
 102     target_phys_addr_t base;
 103
 104     uint32_t error_log;
 105     uint8_t  control;
 106     uint16_t req_info_permission[8];
 107     uint16_t read_permission[8];
 108     uint16_t write_permission[8];
 109     uint32_t addr_match[7];
 110 };
 111
 112 union omap3_l3_port_s {
 113     struct omap_target_agent_s ta;
 114     struct omap3_l3_initiator_agent_s ia;
 115     struct omap3_l3pm_s pm;
 116 };
 117
 118 struct omap_l3_s {
 119     target_phys_addr_t base;
 120     int region_count;
 121     union omap3_l3_port_s region[0];
 122 };
 123
 124 static struct omap_l3_region_s omap3_l3_region[] = {
 125     [L3ID_L3RT         ] = {0x00000000, 0x0400, L3TYPE_UNDEFINED},
 126     [L3ID_L3SI         ] = {0x00000400, 0x0400, L3TYPE_UNDEFINED},
 127     [L3ID_MPUSS_IA     ] = {0x00001400, 0x0400, L3TYPE_IA},
 128     [L3ID_IVASS_IA     ] = {0x00001800, 0x0400, L3TYPE_IA},
 129     [L3ID_SGXSS_IA     ] = {0x00001c00, 0x0400, L3TYPE_IA},
 130     [L3ID_SMS_TA       ] = {0x00002000, 0x0400, L3TYPE_TA},
 131     [L3ID_GPMC_TA      ] = {0x00002400, 0x0400, L3TYPE_TA},
 132     [L3ID_OCM_RAM_TA   ] = {0x00002800, 0x0400, L3TYPE_TA},
 133     [L3ID_OCM_ROM_TA   ] = {0x00002c00, 0x0400, L3TYPE_TA},
 134     [L3ID_D2D_IA       ] = {0x00003000, 0x0400, L3TYPE_IA},
 135     [L3ID_D2D_TA       ] = {0x00003400, 0x0400, L3TYPE_TA},
 136     [L3ID_HSUSB_HOST_IA] = {0x00004000, 0x0400, L3TYPE_IA},
 137     [L3ID_HSUSB_OTG_IA ] = {0x00004400, 0x0400, L3TYPE_IA},
 138     [L3ID_SDMA_RD_IA   ] = {0x00004c00, 0x0400, L3TYPE_IA},
 139     [L3ID_SDMA_WR_IA   ] = {0x00005000, 0x0400, L3TYPE_IA},
 140     [L3ID_DSS_IA       ] = {0x00005400, 0x0400, L3TYPE_IA},
 141     [L3ID_CAMISP_IA    ] = {0x00005800, 0x0400, L3TYPE_IA},
 142     [L3ID_DAP_IA       ] = {0x00005c00, 0x0400, L3TYPE_IA},
 143     [L3ID_IVASS_TA     ] = {0x00006000, 0x0400, L3TYPE_TA},
 144     [L3ID_SGXSS_TA     ] = {0x00006400, 0x0400, L3TYPE_TA},
 145     [L3ID_L4_CORE_TA   ] = {0x00006800, 0x0400, L3TYPE_TA},
 146     [L3ID_L4_PER_TA    ] = {0x00006c00, 0x0400, L3TYPE_TA},
 147     [L3ID_L4_EMU_TA    ] = {0x00007000, 0x0400, L3TYPE_TA},
 148     [L3ID_RT_PM        ] = {0x00010000, 0x0400, L3TYPE_PM},
 149     [L3ID_GPMC_PM      ] = {0x00012400, 0x0400, L3TYPE_PM},
 150     [L3ID_OCM_RAM_PM   ] = {0x00012800, 0x0400, L3TYPE_PM},
 151     [L3ID_OCM_ROM_PM   ] = {0x00012c00, 0x0400, L3TYPE_PM},
 152     [L3ID_D2D_PM       ] = {0x00013000, 0x0400, L3TYPE_PM},
 153     [L3ID_IVA_PM       ] = {0x00014000, 0x0400, L3TYPE_PM},
 154 };
 155
 156 static uint32_t omap3_l3ia_read(void *opaque, target_phys_addr_t addr)
 157 {
 158     struct omap3_l3_initiator_agent_s *s = (struct omap3_l3_initiator_agent_s *)opaque;
 159
 160     switch (addr) {
 161         case 0x00: /* COMPONENT_L */
 162             return s->component;
 163         case 0x04: /* COMPONENT_H */
 164             return 0;
 165         case 0x18: /* CORE_L */
 166             return s->component;
 167         case 0x1c: /* CORE_H */
 168             return (s->component >> 16);
 169         case 0x20: /* AGENT_CONTROL_L */
 170             return s->control;
 171         case 0x24: /* AGENT_CONTROL_H */
 172             return 0;
 173         case 0x28: /* AGENT_STATUS_L */
 174             return s->status;
 175         case 0x2c: /* AGENT_STATUS_H */
 176             return 0;
 177         case 0x58: /* ERROR_LOG_L */
 178             return 0;
 179         case 0x5c: /* ERROR_LOG_H */
 180             return 0;
 181         case 0x60: /* ERROR_LOG_ADDR_L */
 182             return 0;
 183         case 0x64: /* ERROR_LOG_ADDR_H */
 184             return 0;
 185         default:
 186             break;
 187     }
 188
 189     OMAP_BAD_REG(s->base + addr);
 190     return 0;
 191 }
 192
 193 static void omap3_l3ia_write(void *opaque, target_phys_addr_t addr,
 194                              uint32_t value)
 195 {
 196     struct omap3_l3_initiator_agent_s *s = (struct omap3_l3_initiator_agent_s *)opaque;
 197
 198     switch (addr) {
 199         case 0x00: /* COMPONENT_L */
 200         case 0x04: /* COMPONENT_H */
 201         case 0x18: /* CORE_L */
 202         case 0x1c: /* CORE_H */
 203         case 0x60: /* ERROR_LOG_ADDR_L */
 204         case 0x64: /* ERROR_LOG_ADDR_H */
 205             OMAP_RO_REG(s->base + addr);
 206             break;
 207         case 0x24: /* AGENT_CONTROL_H */
 208         case 0x2c: /* AGENT_STATUS_H */
 209         case 0x5c: /* ERROR_LOG_H */
 210             /* RW register but all bits are reserved/read-only */
 211             break;
 212         case 0x20: /* AGENT_CONTROL_L */
 213             s->control = value & 0x3e070711;
 214             /* TODO: some bits are reserved for some IA instances */
 215             break;
 216         case 0x28: /* AGENT_STATUS_L */
 217             s->status &= ~(value & 0x30000000);
 218             break;
 219         case 0x58: /* ERROR_LOG_L */
 220             /* error logging is not implemented, so ignore */
 221             break;
 222         default:
 223             OMAP_BAD_REG(s->base + addr);
 224             break;
 225     }
 226 }
 227
 228 static void omap3_l3ia_init(struct omap3_l3_initiator_agent_s *s)
 229 {
 230     s->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
 231     s->control = 0x3e000000;
 232     s->status = 0;
 233 }
 234
 235 static CPUReadMemoryFunc *omap3_l3ia_readfn[] = {
 236     omap_badwidth_read32,
 237     omap_badwidth_read32,
 238     omap3_l3ia_read,
 239 };
 240
 241 static CPUWriteMemoryFunc *omap3_l3ia_writefn[] = {
 242     omap_badwidth_write32,
 243     omap_badwidth_write32,
 244     omap3_l3ia_write,
 245 };
 246
 247 static uint32_t omap3_l3ta_read(void *opaque, target_phys_addr_t addr)
 248 {
 249     struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
 250
 251     switch (addr) {
 252         case 0x00: /* COMPONENT_L */
 253             return s->component;
 254         case 0x04: /* COMPONENT_H */
 255             return 0;
 256         case 0x18: /* CORE_L */
 257             return s->component;
 258         case 0x1c: /* CORE_H */
 259             return (s->component >> 16);
 260         case 0x20: /* AGENT_CONTROL_L */
 261             return s->control;
 262         case 0x24: /* AGENT_CONTROL_H */
 263             return s->control_h;
 264         case 0x28: /* AGENT_STATUS_L */
 265             return s->status;
 266         case 0x2c: /* AGENT_STATUS_H */
 267             return 0;
 268         case 0x58: /* ERROR_LOG_L */
 269             return 0;
 270         case 0x5c: /* ERROR_LOG_H */
 271             return 0;
 272         case 0x60: /* ERROR_LOG_ADDR_L */
 273             return 0;
 274         case 0x64: /* ERROR_LOG_ADDR_H */
 275             return 0;
 276         default:
 277             break;
 278     }
 279
 280     OMAP_BAD_REG(s->base + addr);
 281     return 0;
 282 }
 283
 284 static void omap3_l3ta_write(void *opaque, target_phys_addr_t addr,
 285                              uint32_t value)
 286 {
 287     struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
 288
 289     switch (addr) {
 290         case 0x00: /* COMPONENT_L */
 291         case 0x04: /* COMPONENT_H */
 292         case 0x18: /* CORE_L */
 293         case 0x1c: /* CORE_H */
 294         case 0x60: /* ERROR_LOG_ADDR_L */
 295         case 0x64: /* ERROR_LOG_ADDR_H */
 296             OMAP_RO_REG(s->base + addr);
 297             break;
 298         case 0x24: /* AGENT_CONTROL_H */
 299         case 0x5c: /* ERROR_LOG_H */
 300             /* RW register but all bits are reserved/read-only */
 301             break;
 302         case 0x20: /* AGENT_CONTROL_L */
 303             s->control = value & 0x03000711;
 304             break;
 305         case 0x28: /* AGENT_STATUS_L */
 306             if (s->base == OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_CORE_TA].offset
 307                 || s->base == OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_PER_TA].offset
 308                 || s->base == OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_EMU_TA].offset) {
 309                 s->status &= ~(value & (1 << 24));
 310             } else
 311                 OMAP_RO_REG(s->base + addr);
 312             break;
 313         case 0x2c: /* AGENT_STATUS_H */
 314             if (s->base != OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_CORE_TA].offset
 315                 && s->base != OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_PER_TA].offset
 316                 && s->base != OMAP3_L3_BASE + omap3_l3_region[L3ID_L4_EMU_TA].offset)
 317                 OMAP_RO_REG(s->base + addr);
 318             /* for L4 core, per, emu TAs this is RW reg */
 319             break;
 320         case 0x58: /* ERROR_LOG_L */
 321             /* error logging is not implemented, so ignore */
 322             break;
 323         default:
 324             OMAP_BAD_REG(s->base + addr);
 325             break;
 326     }
 327 }
 328
 329 static void omap3_l3ta_init(struct omap_target_agent_s *s)
 330 {
 331     s->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
 332     s->control = 0x03000000;
 333     s->status = 0;
 334 }
 335
 336 static CPUReadMemoryFunc *omap3_l3ta_readfn[] = {
 337     omap_badwidth_read32,
 338     omap_badwidth_read32,
 339     omap3_l3ta_read,
 340 };
 341
 342 static CPUWriteMemoryFunc *omap3_l3ta_writefn[] = {
 343     omap_badwidth_write32,
 344     omap_badwidth_write32,
 345     omap3_l3ta_write,
 346 };
 347
 348 static uint32_t omap3_l3pm_read8(void *opaque, target_phys_addr_t addr)
 349 {
 350     struct omap3_l3pm_s *s = (struct omap3_l3pm_s *)opaque;
 351     int i;
 352
 353     switch (addr) {
 354         case 0x00 ... 0x1f:
 355         case 0x40 ... 0x47:
 356             OMAP_BAD_REG(s->base + addr);
 357             return 0;
 358         /* ERROR_LOG */
 359         case 0x20: return s->error_log & 0xff;
 360         case 0x21: return (s->error_log >> 8) & 0xff;
 361         case 0x22: return (s->error_log >> 16) & 0xff;
 362         case 0x23: return (s->error_log >> 24) & 0xff;
 363         case 0x24 ... 0x27: return 0;
 364         /* CONTROL */
 365         case 0x28 ... 0x2a: return 0;
 366         case 0x2b: return s->control;
 367         case 0x2c ... 0x2f: return 0;
 368         /* ERROR_CLEAR_SINGLE */
 369         case 0x30: return 0; /* TODO: clear single error from log */
 370         case 0x31 ... 0x37: return 0;
 371         /* ERROR_CLEAR_MULTI */
 372         case 0x38: return 0; /* TODO: clear multiple errors from log */
 373         case 0x39 ... 0x3f: return 0;
 374         default:
 375             break;
 376     }
 377
 378     i = (addr - 0x48) / 0x20;
 379     addr -= i * 0x20;
 380     if (i < 7 || (i < 8 && addr < 0x60))
 381         switch (addr) {
 382             /* REQ_INFO_PERMISSION_i */
 383             case 0x48: return s->req_info_permission[i] & 0xff;
 384             case 0x49: return (s->req_info_permission[i] >> 8) & 0xff;
 385             case 0x4a ... 0x4f: return 0;
 386             /* READ_PERMISSION_i */
 387             case 0x50: return s->read_permission[i] & 0xff;
 388             case 0x51: return (s->read_permission[i] >> 8) & 0xff;
 389             case 0x52 ... 0x57: return 0;
 390             /* WRITE_PERMISSION_i */
 391             case 0x58: return s->write_permission[i] & 0xff;
 392             case 0x59: return (s->write_permission[i] >> 8) & 0xff;
 393             case 0x5a ... 0x5f: return 0;
 394             /* ADDR_MATCH_i */
 395             case 0x60: return s->addr_match[i] & 0xff;
 396             case 0x61: return (s->addr_match[i] >> 8) & 0xff;
 397             case 0x62: return (s->addr_match[i] >> 16) & 0xff;
 398             case 0x63 ... 0x67: return 0;
 399             default:
 400                 break;
 401         }
 402
 403     OMAP_BAD_REG(s->base + addr);
 404     return 0;
 405 }
 406
 407 static uint32_t omap3_l3pm_read16(void *opaque, target_phys_addr_t addr)
 408 {
 409     return omap3_l3pm_read8(opaque, addr)
 410         | (omap3_l3pm_read8(opaque, addr + 1) << 8);
 411 }
 412
 413 static uint32_t omap3_l3pm_read32(void *opaque, target_phys_addr_t addr)
 414 {
 415     return omap3_l3pm_read16(opaque, addr)
 416         | (omap3_l3pm_read16(opaque, addr + 2) << 16);
 417 }
 418
 419 static void omap3_l3pm_write8(void *opaque, target_phys_addr_t addr,
 420                               uint32_t value)
 421 {
 422     struct omap3_l3pm_s *s = (struct omap3_l3pm_s *)opaque;
 423     int i;
 424
 425     switch (addr) {
 426         case 0x00 ... 0x1f:
 427         case 0x40 ... 0x47:
 428             OMAP_BAD_REGV(s->base + addr, value);
 429             return;
 430         /* ERROR_LOG */
 431         case 0x23:
 432             s->error_log &= ~((value & 0xcf) << 24);
 433         case 0x20 ... 0x22:
 434         case 0x24 ... 0x27:
 435             return;
 436         /* CONTROL */
 437         case 0x2b:
 438             s->control = value & 3;
 439         case 0x28 ... 0x2a:
 440         case 0x2c ... 0x2f:
 441             return;
 442         /* ERROR_CLEAR_SINGLE / ERROR_CLEAR_MULTI */
 443         case 0x30 ... 0x3f:
 444             OMAP_RO_REGV(s->base + addr, value);
 445             return;
 446         default:
 447             break;
 448     }
 449
 450     i = (addr - 0x48) / 0x20;
 451     addr -= i * 0x20;
 452     if (i < 7 || (i < 8 && addr < 0x60))
 453         switch (addr) {
 454             /* REQ_INFO_PERMISSION_i */
 455             case 0x48:
 456                 s->req_info_permission[i] =
 457                     (s->req_info_permission[i] & ~0xff) | (value & 0xff);
 458                 return;
 459             case 0x49:
 460                 s->req_info_permission[i] =
 461                     (s->req_info_permission[i] & ~0xff00) | ((value & 0xff) << 8);
 462                 return;
 463             case 0x4a ... 0x4f:
 464                 return;
 465             /* READ_PERMISSION_i */
 466             case 0x50:
 467                 s->read_permission[i] =
 468                     (s->read_permission[i] & ~0xff) | (value & 0x3e);
 469                 return;
 470             case 0x51:
 471                 s->read_permission[i] =
 472                     (s->read_permission[i] & ~0xff00) | ((value & 0x5f) << 8);
 473                 return;
 474             case 0x52 ... 0x57:
 475                 return;
 476             /* WRITE_PERMISSION_i */
 477             case 0x58:
 478                 s->write_permission[i] =
 479                     (s->write_permission[i] & ~0xff) | (value & 0x3e);
 480                 return;
 481             case 0x59:
 482                 s->write_permission[i] =
 483                     (s->write_permission[i] & ~0xff00) | ((value & 0x5f) << 8);
 484                 return;
 485             case 0x5a ... 0x5f:
 486                 return;
 487             /* ADDR_MATCH_i */
 488             case 0x60:
 489                 s->addr_match[i] = (s->addr_match[i] & ~0xff) | (value & 0xff);
 490                 return;
 491             case 0x61:
 492                 s->addr_match[i] =
 493                     (s->addr_match[i] & ~0xfe00) | ((value & 0xfe) << 8);
 494                 return;
 495             case 0x62:
 496                 s->addr_match[i] =
 497                     (s->addr_match[i] & ~0x0f0000) | ((value & 0x0f) << 16);
 498                 return;
 499             case 0x63 ... 0x67:
 500                 return;
 501             default:
 502                 break;
 503         }
 504
 505     OMAP_BAD_REGV(s->base + addr, value);
 506 }
 507
 508 static void omap3_l3pm_write16(void *opaque, target_phys_addr_t addr,
 509                                uint32_t value)
 510 {
 511     omap3_l3pm_write8(opaque, addr + 0, value & 0xff);
 512     omap3_l3pm_write8(opaque, addr + 1, (value >> 8) & 0xff);
 513 }
 514
 515 static void omap3_l3pm_write32(void *opaque, target_phys_addr_t addr,
 516                                uint32_t value)
 517 {
 518     omap3_l3pm_write16(opaque, addr + 0, value & 0xffff);
 519     omap3_l3pm_write16(opaque, addr + 2, (value >> 16) & 0xffff);
 520 }
 521
 522 static void omap3_l3pm_init(struct omap3_l3pm_s *s)
 523 {
 524     int i;
 525
 526     s->error_log = 0;
 527     s->control = 0x03;
 528     switch (s->base) {
 529         case 0x68010000: /* PM_RT */
 530             s->req_info_permission[0] = 0xffff;
 531             s->req_info_permission[1] = 0;
 532             for (i = 0; i < 2; i++)
 533                 s->read_permission[i] = s->write_permission[i] = 0x1406;
 534             s->addr_match[0] = 0x10230;
 535             break;
 536         case 0x68012400: /* PM_GPMC */
 537             s->req_info_permission[0] = 0;
 538             for (i = 3; i < 8; i++)
 539                 s->req_info_permission[i] = 0xffff;
 540             for (i = 0; i < 8; i++)
 541                 s->read_permission[i] = s->write_permission[i] = 0x563e;
 542             s->addr_match[0] = 0x00098;
 543             break;
 544         case 0x68012800: /* PM_OCM_RAM */
 545             s->req_info_permission[0] = 0;
 546             for (i = 1; i < 8; i++)
 547                 s->req_info_permission[i] = 0xffff;
 548             for (i = 0; i < 8; i++)
 549                 s->read_permission[i] = s->write_permission[i] = 0x5f3e;
 550             s->addr_match[1] = 0x0f810;
 551             break;
 552         case 0x68012C00: /* PM_OCM_ROM */
 553             s->req_info_permission[1] = 0xffff;
 554             for (i = 0; i < 2; i++) {
 555                 s->read_permission[i] = 0x1002;
 556                 s->write_permission[i] = 0;
 557             }
 558             s->addr_match[0] = 0x14028;
 559             break;
 560         case 0x68013000: /* PM_MAD2D */
 561             s->req_info_permission[0] = 0;
 562             for (i = 1; i < 8; i++)
 563                 s->req_info_permission[i] = 0xffff;
 564             for (i = 0; i < 8; i++)
 565                 s->read_permission[i] = s->write_permission[i] = 0x5f1e;
 566             break;
 567         case 0x68014000: /* PM_IVA2.2 */
 568             s->req_info_permission[0] = 0;
 569             for (i = 1; i < 4; i++)
 570                 s->req_info_permission[i] = 0xffff;
 571             for (i = 0; i < 4; i++)
 572                 s->read_permission[i] = s->write_permission[i] = 0x140e;
 573             break;
 574         default:
 575             fprintf(stderr, "%s: unknown PM region (0x%08llx)\n",
 576                     __FUNCTION__, s->base);
 577             exit(-1);
 578             break;
 579     }
 580 }
 581
 582 static CPUReadMemoryFunc *omap3_l3pm_readfn[] = {
 583     omap3_l3pm_read8,
 584     omap3_l3pm_read16,
 585     omap3_l3pm_read32,
 586 };
 587
 588 static CPUWriteMemoryFunc *omap3_l3pm_writefn[] = {
 589     omap3_l3pm_write8,
 590     omap3_l3pm_write16,
 591     omap3_l3pm_write32,
 592 };
 593
 594 static uint32_t omap3_l3undef_read8(void *opaque, target_phys_addr_t addr)
 595 {
 596     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx "\n",
 597             __FUNCTION__, addr);
 598     return 0;
 599 }
 600
 601 static uint32_t omap3_l3undef_read16(void *opaque, target_phys_addr_t addr)
 602 {
 603     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx "\n",
 604             __FUNCTION__, addr);
 605     return 0;
 606 }
 607
 608 static uint32_t omap3_l3undef_read32(void *opaque, target_phys_addr_t addr)
 609 {
 610     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx "\n",
 611             __FUNCTION__, addr);
 612     return 0;
 613 }
 614
 615 static void omap3_l3undef_write8(void *opaque, target_phys_addr_t addr,
 616                                uint32_t value)
 617 {
 618     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx ", value %02x\n",
 619             __FUNCTION__, addr, value);
 620 }
 621
 622 static void omap3_l3undef_write16(void *opaque, target_phys_addr_t addr,
 623                                 uint32_t value)
 624 {
 625     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx ", value %04x\n",
 626             __FUNCTION__, addr, value);
 627 }
 628
 629 static void omap3_l3undef_write32(void *opaque, target_phys_addr_t addr,
 630                                 uint32_t value)
 631 {
 632     fprintf(stderr, "%s: unsupported register at " OMAP_FMT_plx ", value %08x\n",
 633             __FUNCTION__, addr, value);
 634 }
 635
 636 static CPUReadMemoryFunc *omap3_l3undef_readfn[] = {
 637     omap3_l3undef_read8,
 638     omap3_l3undef_read16,
 639     omap3_l3undef_read32,
 640 };
 641
 642 static CPUWriteMemoryFunc *omap3_l3undef_writefn[] = {
 643     omap3_l3undef_write8,
 644     omap3_l3undef_write16,
 645     omap3_l3undef_write32,
 646 };
 647
 648 static struct omap_l3_s *omap3_l3_init(target_phys_addr_t base,
 649                                        struct omap_l3_region_s *regions,
 650                                        int n)
 651 {
 652     int i, iomemtype = 0;
 653
 654     struct omap_l3_s *bus = qemu_mallocz(sizeof(*bus) + n * sizeof(*bus->region));
 655     bus->region_count = n;
 656     bus->base = base;
 657
 658     for (i = 0; i < n; i++) {
 659         switch (regions[i].type) {
 660             case L3TYPE_GENERIC:
 661                 /* not mapped for now, mapping will be done later by
 662                    specialized code */
 663                 break;
 664             case L3TYPE_IA:
 665                 iomemtype = cpu_register_io_memory(0, omap3_l3ia_readfn,
 666                                                    omap3_l3ia_writefn,
 667                                                    &bus->region[i].ia);
 668                 bus->region[i].ia.base = base + regions[i].offset;
 669                 omap3_l3ia_init(&bus->region[i].ia);
 670                 break;
 671             case L3TYPE_TA:
 672                 iomemtype = cpu_register_io_memory(0, omap3_l3ta_readfn,
 673                                                    omap3_l3ta_writefn,
 674                                                    &bus->region[i].ta);
 675                 bus->region[i].ta.base = base + regions[i].offset;
 676                 omap3_l3ta_init(&bus->region[i].ta);
 677                 break;
 678             case L3TYPE_PM:
 679                 iomemtype = cpu_register_io_memory(0, omap3_l3pm_readfn,
 680                                                    omap3_l3pm_writefn,
 681                                                    &bus->region[i].pm);
 682                 bus->region[i].pm.base = base + regions[i].offset;
 683                 omap3_l3pm_init(&bus->region[i].pm);
 684                 break;
 685             case L3TYPE_UNDEFINED:
 686                 iomemtype = cpu_register_io_memory(0, omap3_l3undef_readfn,
 687                                                    omap3_l3undef_writefn,
 688                                                    &bus->region[i]);
 689                 break;
 690             default:
 691                 fprintf(stderr, "%s: unknown L3 region type: %d\n",
 692                         __FUNCTION__, regions[i].type);
 693                 exit(-1);
 694                 break;
 695         }
 696         cpu_register_physical_memory(base + regions[i].offset,
 697                                      regions[i].size,
 698                                      iomemtype);
 699     }
 700
 701     return bus;
 702 }
 703
 704 typedef enum {
 705     /* 48000000-48001FFF */
 706     /* 48002000-48002FFF */ L4ID_SCM = 0,
 707     /* 48003000-48003FFF */ L4ID_SCM_TA,
 708     /* 48004000-48005FFF */ L4ID_CM_A,
 709     /* 48006000-480067FF */ L4ID_CM_B,
 710     /* 48006800-48006FFF */
 711     /* 48007000-48007FFF */ L4ID_CM_TA,
 712     /* 48008000-48023FFF */
 713     /* 48024000-48024FFF */
 714     /* 48025000-48025FFF */
 715     /* 48026000-4803FFFF */
 716     /* 48040000-480407FF */ L4ID_CORE_AP,
 717     /* 48040800-48040FFF */ L4ID_CORE_IP,
 718     /* 48041000-48041FFF */ L4ID_CORE_LA,
 719     /* 48042000-4804FBFF */
 720     /* 4804FC00-4804FFFF */ L4ID_DSI,
 721     /* 48050000-480503FF */ L4ID_DSS,
 722     /* 48050400-480507FF */ L4ID_DISPC,
 723     /* 48050800-48050BFF */ L4ID_RFBI,
 724     /* 48050C00-48050FFF */ L4ID_VENC,
 725     /* 48051000-48051FFF */ L4ID_DSS_TA,
 726     /* 48052000-48055FFF */
 727     /* 48056000-48056FFF */ L4ID_SDMA,
 728     /* 48057000-48057FFF */ L4ID_SDMA_TA,
 729     /* 48058000-4805FFFF */
 730     /* 48060000-48060FFF */ L4ID_I2C3,
 731     /* 48061000-48061FFF */ L4ID_I2C3_TA,
 732     /* 48062000-48062FFF */ L4ID_USBTLL,
 733     /* 48063000-48063FFF */ L4ID_USBTLL_TA,
 734     /* 48064000-48064FFF */ L4ID_HSUSBHOST,
 735     /* 48065000-48065FFF */ L4ID_HSUSBHOST_TA,
 736     /* 48066000-48069FFF */
 737     /* 4806A000-4806AFFF */ L4ID_UART1,
 738     /* 4806B000-4806BFFF */ L4ID_UART1_TA,
 739     /* 4806C000-4806CFFF */ L4ID_UART2,
 740     /* 4806D000-4806DFFF */ L4ID_UART2_TA,
 741     /* 4806E000-4806FFFF */
 742     /* 48070000-48070FFF */ L4ID_I2C1,
 743     /* 48071000-48071FFF */ L4ID_I2C1_TA,
 744     /* 48072000-48072FFF */ L4ID_I2C2,
 745     /* 48073000-48073FFF */ L4ID_I2C2_TA,
 746     /* 48074000-48074FFF */ L4ID_MCBSP1,
 747     /* 48075000-48075FFF */ L4ID_MCBSP1_TA,
 748     /* 48076000-48085FFF */
 749     /* 48086000-48086FFF */ L4ID_GPTIMER10,
 750     /* 48087000-48087FFF */ L4ID_GPTIMER10_TA,
 751     /* 48088000-48088FFF */ L4ID_GPTIMER11,
 752     /* 48089000-48089FFF */ L4ID_GPTIMER11_TA,
 753     /* 4808A000-4808AFFF */
 754     /* 4808B000-4808BFFF */
 755     /* 4808C000-48093FFF */
 756     /* 48094000-48094FFF */ L4ID_MAILBOX,
 757     /* 48095000-48095FFF */ L4ID_MAILBOX_TA,
 758     /* 48096000-48096FFF */ L4ID_MCBSP5,
 759     /* 48097000-48097FFF */ L4ID_MCBSP5_TA,
 760     /* 48098000-48098FFF */ L4ID_MCSPI1,
 761     /* 48099000-48099FFF */ L4ID_MCSPI1_TA,
 762     /* 4809A000-4809AFFF */ L4ID_MCSPI2,
 763     /* 4809B000-4809BFFF */ L4ID_MCSPI2_TA,
 764     /* 4809C000-4809CFFF */ L4ID_MMCSDIO1,
 765     /* 4809D000-4809DFFF */ L4ID_MMCSDIO1_TA,
 766     /* 4809E000-4809EFFF */ L4ID_MSPRO,
 767     /* 4809F000-4809FFFF */ L4ID_MSPRO_TA,
 768     /* 480A0000-480AAFFF */
 769     /* 480AB000-480ABFFF */ L4ID_HSUSBOTG,
 770     /* 480AC000-480ACFFF */ L4ID_HSUSBOTG_TA,
 771     /* 480AD000-480ADFFF */ L4ID_MMCSDIO3,
 772     /* 480AE000-480AEFFF */ L4ID_MMCSDIO3_TA,
 773     /* 480AF000-480AFFFF */
 774     /* 480B0000-480B0FFF */
 775     /* 480B1000-480B1FFF */
 776     /* 480B2000-480B2FFF */ L4ID_HDQ1WIRE,
 777     /* 480B3000-480B2FFF */ L4ID_HDQ1WIRE_TA,
 778     /* 480B4000-480B4FFF */ L4ID_MMCSDIO2,
 779     /* 480B5000-480B5FFF */ L4ID_MMCSDIO2_TA,
 780     /* 480B6000-480B6FFF */ L4ID_ICRMPU,
 781     /* 480B7000-480B7FFF */ L4ID_ICRMPU_TA,
 782     /* 480B8000-480B8FFF */ L4ID_MCSPI3,
 783     /* 480B9000-480B9FFF */ L4ID_MCSPI3_TA,
 784     /* 480BA000-480BAFFF */ L4ID_MCSPI4,
 785     /* 480BB000-480BBFFF */ L4ID_MCSPI4_TA,
 786     /* 480BC000-480BFFFF */ L4ID_CAMERAISP,
 787     /* 480C0000-480C0FFF */ L4ID_CAMERAISP_TA,
 788     /* 480C1000-480CCFFF */
 789     /* 480CD000-480CDFFF */ L4ID_ICRMODEM,
 790     /* 480CE000-480CEFFF */ L4ID_ICRMODEM_TA,
 791     /* 480CF000-482FFFFF */
 792     /* 48300000-48303FFF */
 793     /* 48304000-48304FFF */ L4ID_GPTIMER12,
 794     /* 48305000-48305FFF */ L4ID_GPTIMER12_TA,
 795     /* 48306000-48307FFF */ L4ID_PRM_A,
 796     /* 48308000-483087FF */ L4ID_PRM_B,
 797     /* 48308800-48308FFF */
 798     /* 48309000-48309FFF */ L4ID_PRM_TA,
 799     /* 4830A000-4830AFFF */ L4ID_TAP,
 800     /* 4830B000-4830BFFF */ L4ID_TAP_TA,
 801     /* 4830C000-4830FFFF */
 802     /* 48310000-48310FFF */ L4ID_GPIO1,
 803     /* 48311000-48311FFF */ L4ID_GPIO1_TA,
 804     /* 48312000-48313FFF */
 805     /* 48314000-48314FFF */ L4ID_WDTIMER2,
 806     /* 48315000-48315FFF */ L4ID_WDTIMER2_TA,
 807     /* 48316000-48317FFF */
 808     /* 48318000-48318FFF */ L4ID_GPTIMER1,
 809     /* 48319000-48319FFF */ L4ID_GPTIMER1_TA,
 810     /* 4831A000-4831FFFF */
 811     /* 48320000-48320FFF */ L4ID_32KTIMER,
 812     /* 48321000-48321FFF */ L4ID_32KTIMER_TA,
 813     /* 48322000-48327FFF */
 814     /* 48328000-483287FF */ L4ID_WAKEUP_AP,
 815     /* 48328800-48328FFF */ L4ID_WAKEUP_C_IP,
 816     /* 48329000-48329FFF */ L4ID_WAKEUP_LA,
 817     /* 4832A000-4832A7FF */ L4ID_WAKEUP_E_IP,
 818     /* 4832A800-4833FFFF */
 819     /* 48340000-48340FFF */
 820     /* 48341000-48FFFFFF */
 821     /* 49000000-490007FF */ L4ID_PER_AP,
 822     /* 49000800-49000FFF */ L4ID_PER_IP,
 823     /* 49001000-49001FFF */ L4ID_PER_LA,
 824     /* 49002000-4901FFFF */
 825     /* 49020000-49020FFF */ L4ID_UART3,
 826     /* 49021000-49021FFF */ L4ID_UART3_TA,
 827     /* 49022000-49022FFF */ L4ID_MCBSP2,
 828     /* 49023000-49023FFF */ L4ID_MCBSP2_TA,
 829     /* 49024000-49024FFF */ L4ID_MCBSP3,
 830     /* 49025000-49025FFF */ L4ID_MCBSP3_TA,
 831     /* 49026000-49026FFF */ L4ID_MCBSP4,
 832     /* 49027000-49027FFF */ L4ID_MCBSP4_TA,
 833     /* 49028000-49028FFF */ L4ID_MCBSP2S,
 834     /* 49029000-49029FFF */ L4ID_MCBSP2S_TA,
 835     /* 4902A000-4902AFFF */ L4ID_MCBSP3S,
 836     /* 4902B000-4902BFFF */ L4ID_MCBSP3S_TA,
 837     /* 4902C000-4902FFFF */
 838     /* 49030000-49030FFF */ L4ID_WDTIMER3,
 839     /* 49031000-49031FFF */ L4ID_WDTIMER3_TA,
 840     /* 49032000-49032FFF */ L4ID_GPTIMER2,
 841     /* 49033000-49033FFF */ L4ID_GPTIMER2_TA,
 842     /* 49034000-49034FFF */ L4ID_GPTIMER3,
 843     /* 49035000-49035FFF */ L4ID_GPTIMER3_TA,
 844     /* 49036000-49036FFF */ L4ID_GPTIMER4,
 845     /* 49037000-49037FFF */ L4ID_GPTIMER4_TA,
 846     /* 49038000-49038FFF */ L4ID_GPTIMER5,
 847     /* 49039000-49039FFF */ L4ID_GPTIMER5_TA,
 848     /* 4903A000-4903AFFF */ L4ID_GPTIMER6,
 849     /* 4903B000-4903BFFF */ L4ID_GPTIMER6_TA,
 850     /* 4903C000-4903CFFF */ L4ID_GPTIMER7,
 851     /* 4903D000-4903DFFF */ L4ID_GPTIMER7_TA,
 852     /* 4903E000-4903EFFF */ L4ID_GPTIMER8,
 853     /* 4903F000-4903FFFF */ L4ID_GPTIMER8_TA,
 854     /* 49040000-49040FFF */ L4ID_GPTIMER9,
 855     /* 49041000-49041FFF */ L4ID_GPTIMER9_TA,
 856     /* 49042000-4904FFFF */
 857     /* 49050000-49050FFF */ L4ID_GPIO2,
 858     /* 49051000-49051FFF */ L4ID_GPIO2_TA,
 859     /* 49052000-49052FFF */ L4ID_GPIO3,
 860     /* 49053000-49053FFF */ L4ID_GPIO3_TA,
 861     /* 49054000-49054FFF */ L4ID_GPIO4,
 862     /* 49055000-49055FFF */ L4ID_GPIO4_TA,
 863     /* 49056000-49056FFF */ L4ID_GPIO5,
 864     /* 49057000-49057FFF */ L4ID_GPIO5_TA,
 865     /* 49058000-49058FFF */ L4ID_GPIO6,
 866     /* 49059000-49059FFF */ L4ID_GPIO6_TA,
 867     /* 4905A000-490FFFFF */
 868     /* 54000000-54003FFF */
 869     /* 54004000-54005FFF */
 870     /* 54006000-540067FF */ L4ID_EMU_AP,
 871     /* 54006800-54006FFF */ L4ID_EMU_IP_C,
 872     /* 54007000-54007FFF */ L4ID_EMU_LA,
 873     /* 54008000-540087FF */ L4ID_EMU_IP_DAP,
 874     /* 54008800-5400FFFF */
 875     /* 54010000-54017FFF */ L4ID_MPUEMU,
 876     /* 54018000-54018FFF */ L4ID_MPUEMU_TA,
 877     /* 54019000-54019FFF */ L4ID_TPIU,
 878     /* 5401A000-5401AFFF */ L4ID_TPIU_TA,
 879     /* 5401B000-5401BFFF */ L4ID_ETB,
 880     /* 5401C000-5401CFFF */ L4ID_ETB_TA,
 881     /* 5401D000-5401DFFF */ L4ID_DAPCTL,
 882     /* 5401E000-5401EFFF */ L4ID_DAPCTL_TA,
 883     /* 5401F000-5401FFFF */ L4ID_SDTI_TA,
 884     /* 54020000-544FFFFF */
 885     /* 54500000-5450FFFF */ L4ID_SDTI_CFG,
 886     /* 54510000-545FFFFF */
 887     /* 54600000-546FFFFF */ L4ID_SDTI,
 888     /* 54700000-54705FFF */
 889     /* 54706000-54707FFF */ L4ID_EMU_PRM_A,
 890     /* 54708000-547087FF */ L4ID_EMU_PRM_B,
 891     /* 54708800-54708FFF */
 892     /* 54709000-54709FFF */ L4ID_EMU_PRM_TA,
 893     /* 5470A000-5470FFFF */
 894     /* 54710000-54710FFF */ L4ID_EMU_GPIO1,
 895     /* 54711000-54711FFF */ L4ID_EMU_GPIO1_TA,
 896     /* 54712000-54713FFF */
 897     /* 54714000-54714FFF */ L4ID_EMU_WDTM2,
 898     /* 54715000-54715FFF */ L4ID_EMU_WDTM2_TA,
 899     /* 54716000-54717FFF */
 900     /* 54718000-54718FFF */ L4ID_EMU_GPTM1,
 901     /* 54719000-54719FFF */ L4ID_EMU_GPTM1_TA,
 902     /* 5471A000-5471FFFF */
 903     /* 54720000-54720FFF */ L4ID_EMU_32KTM,
 904     /* 54721000-54721FFF */ L4ID_EMU_32KTM_TA,
 905     /* 54722000-54727FFF */
 906     /* 54728000-547287FF */ L4ID_EMU_WKUP_AP,
 907     /* 54728800-54728FFF */ L4ID_EMU_WKUP_IPC,
 908     /* 54729000-54729FFF */ L4ID_EMU_WKUP_LA,
 909     /* 5472A000-5472A7FF */ L4ID_EMU_WKUP_IPE,
 910     /* 5472A800-547FFFFF */
 911 } omap3_l4_region_id_t;
 912
 913 typedef enum {
 914     L4TYPE_GENERIC = 0, /* not mapped by default, must be mapped separately */
 915     L4TYPE_IA,          /* initiator agent */
 916     L4TYPE_TA,          /* target agent */
 917     L4TYPE_LA,          /* link register agent */
 918     L4TYPE_AP           /* address protection */
 919 } omap3_l4_region_type_t;
 920
 921 /* we reuse the "access" member for defining region type -- the original
 922    omap_l4_region_s "access" member is not used anywhere else anyway! */
 923 static struct omap_l4_region_s omap3_l4_region[] = {
 924     /* L4-Core */
 925     [L4ID_SCM         ] = {0x00002000, 0x1000, L4TYPE_GENERIC},
 926     [L4ID_SCM_TA      ] = {0x00003000, 0x1000, L4TYPE_TA},
 927     [L4ID_CM_A        ] = {0x00004000, 0x2000, L4TYPE_GENERIC},
 928     [L4ID_CM_B        ] = {0x00006000, 0x0800, L4TYPE_GENERIC},
 929     [L4ID_CM_TA       ] = {0x00007000, 0x1000, L4TYPE_TA},
 930     [L4ID_CORE_AP     ] = {0x00040000, 0x0800, L4TYPE_AP},
 931     [L4ID_CORE_IP     ] = {0x00040800, 0x0800, L4TYPE_IA},
 932     [L4ID_CORE_LA     ] = {0x00041000, 0x1000, L4TYPE_LA},
 933     [L4ID_DSI         ] = {0x0004fc00, 0x0400, L4TYPE_GENERIC},
 934     [L4ID_DSS         ] = {0x00050000, 0x0400, L4TYPE_GENERIC},
 935     [L4ID_DISPC       ] = {0x00050400, 0x0400, L4TYPE_GENERIC},
 936     [L4ID_RFBI        ] = {0x00050800, 0x0400, L4TYPE_GENERIC},
 937     [L4ID_VENC        ] = {0x00050c00, 0x0400, L4TYPE_GENERIC},
 938     [L4ID_DSS_TA      ] = {0x00051000, 0x1000, L4TYPE_TA},
 939     [L4ID_SDMA        ] = {0x00056000, 0x1000, L4TYPE_GENERIC},
 940     [L4ID_SDMA_TA     ] = {0x00057000, 0x1000, L4TYPE_TA},
 941     [L4ID_I2C3        ] = {0x00060000, 0x1000, L4TYPE_GENERIC},
 942     [L4ID_I2C3_TA     ] = {0x00061000, 0x1000, L4TYPE_TA},
 943     [L4ID_USBTLL      ] = {0x00062000, 0x1000, L4TYPE_GENERIC},
 944     [L4ID_USBTLL_TA   ] = {0x00063000, 0x1000, L4TYPE_TA},
 945     [L4ID_HSUSBHOST   ] = {0x00064000, 0x1000, L4TYPE_GENERIC},
 946     [L4ID_HSUSBHOST_TA] = {0x00065000, 0x1000, L4TYPE_TA},
 947     [L4ID_UART1       ] = {0x0006a000, 0x1000, L4TYPE_GENERIC},
 948     [L4ID_UART1_TA    ] = {0x0006b000, 0x1000, L4TYPE_TA},
 949     [L4ID_UART2       ] = {0x0006c000, 0x1000, L4TYPE_GENERIC},
 950     [L4ID_UART2_TA    ] = {0x0006d000, 0x1000, L4TYPE_TA},
 951     [L4ID_I2C1        ] = {0x00070000, 0x1000, L4TYPE_GENERIC},
 952     [L4ID_I2C1_TA     ] = {0x00071000, 0x1000, L4TYPE_TA},
 953     [L4ID_I2C2        ] = {0x00072000, 0x1000, L4TYPE_GENERIC},
 954     [L4ID_I2C2_TA     ] = {0x00073000, 0x1000, L4TYPE_TA},
 955     [L4ID_MCBSP1      ] = {0x00074000, 0x1000, L4TYPE_GENERIC},
 956     [L4ID_MCBSP1_TA   ] = {0x00075000, 0x1000, L4TYPE_TA},
 957     [L4ID_GPTIMER10   ] = {0x00086000, 0x1000, L4TYPE_GENERIC},
 958     [L4ID_GPTIMER10_TA] = {0x00087000, 0x1000, L4TYPE_TA},
 959     [L4ID_GPTIMER11   ] = {0x00088000, 0x1000, L4TYPE_GENERIC},
 960     [L4ID_GPTIMER11_TA] = {0x00089000, 0x1000, L4TYPE_TA},
 961     [L4ID_MAILBOX     ] = {0x00094000, 0x1000, L4TYPE_GENERIC},
 962     [L4ID_MAILBOX_TA  ] = {0x00095000, 0x1000, L4TYPE_TA},
 963     [L4ID_MCBSP5      ] = {0x00096000, 0x1000, L4TYPE_GENERIC},
 964     [L4ID_MCBSP5_TA   ] = {0x00097000, 0x1000, L4TYPE_TA},
 965     [L4ID_MCSPI1      ] = {0x00098000, 0x1000, L4TYPE_GENERIC},
 966     [L4ID_MCSPI1_TA   ] = {0x00099000, 0x1000, L4TYPE_TA},
 967     [L4ID_MCSPI2      ] = {0x0009a000, 0x1000, L4TYPE_GENERIC},
 968     [L4ID_MCSPI2_TA   ] = {0x0009b000, 0x1000, L4TYPE_TA},
 969     [L4ID_MMCSDIO1    ] = {0x0009c000, 0x1000, L4TYPE_GENERIC},
 970     [L4ID_MMCSDIO1_TA ] = {0x0009d000, 0x1000, L4TYPE_TA},
 971     [L4ID_MSPRO       ] = {0x0009e000, 0x1000, L4TYPE_GENERIC},
 972     [L4ID_MSPRO_TA    ] = {0x0009f000, 0x1000, L4TYPE_TA},
 973     [L4ID_HSUSBOTG    ] = {0x000ab000, 0x1000, L4TYPE_GENERIC},
 974     [L4ID_HSUSBOTG_TA ] = {0x000ac000, 0x1000, L4TYPE_TA},
 975     [L4ID_MMCSDIO3    ] = {0x000ad000, 0x1000, L4TYPE_GENERIC},
 976     [L4ID_MMCSDIO3_TA ] = {0x000ae000, 0x1000, L4TYPE_TA},
 977     [L4ID_HDQ1WIRE    ] = {0x000b2000, 0x1000, L4TYPE_GENERIC},
 978     [L4ID_HDQ1WIRE_TA ] = {0x000b3000, 0x1000, L4TYPE_TA},
 979     [L4ID_MMCSDIO2    ] = {0x000b4000, 0x1000, L4TYPE_GENERIC},
 980     [L4ID_MMCSDIO2_TA ] = {0x000b5000, 0x1000, L4TYPE_TA},
 981     [L4ID_ICRMPU      ] = {0x000b6000, 0x1000, L4TYPE_GENERIC},
 982     [L4ID_ICRMPU_TA   ] = {0x000b7000, 0x1000, L4TYPE_TA},
 983     [L4ID_MCSPI3      ] = {0x000b8000, 0x1000, L4TYPE_GENERIC},
 984     [L4ID_MCSPI3_TA   ] = {0x000b9000, 0x1000, L4TYPE_TA},
 985     [L4ID_MCSPI4      ] = {0x000ba000, 0x1000, L4TYPE_GENERIC},
 986     [L4ID_MCSPI4_TA   ] = {0x000bb000, 0x1000, L4TYPE_TA},
 987     [L4ID_CAMERAISP   ] = {0x000bc000, 0x4000, L4TYPE_GENERIC},
 988     [L4ID_CAMERAISP_TA] = {0x000c0000, 0x1000, L4TYPE_TA},
 989     [L4ID_ICRMODEM    ] = {0x000cd000, 0x1000, L4TYPE_GENERIC},
 990     [L4ID_ICRMODEM_TA ] = {0x000ce000, 0x1000, L4TYPE_TA},
 991     /* L4-Wakeup interconnect region A */
 992     [L4ID_GPTIMER12   ] = {0x00304000, 0x1000, L4TYPE_GENERIC},
 993     [L4ID_GPTIMER12_TA] = {0x00305000, 0x1000, L4TYPE_TA},
 994     [L4ID_PRM_A       ] = {0x00306000, 0x2000, L4TYPE_GENERIC},
 995     [L4ID_PRM_B       ] = {0x00308000, 0x0800, L4TYPE_GENERIC},
 996     [L4ID_PRM_TA      ] = {0x00309000, 0x1000, L4TYPE_TA},
 997     /* L4-Core */
 998     [L4ID_TAP         ] = {0x0030a000, 0x1000, L4TYPE_GENERIC},
 999     [L4ID_TAP_TA      ] = {0x0030b000, 0x1000, L4TYPE_TA},
1000     /* L4-Wakeup interconnect region B */
1001     [L4ID_GPIO1       ] = {0x00310000, 0x1000, L4TYPE_GENERIC},
1002     [L4ID_GPIO1_TA    ] = {0x00311000, 0x1000, L4TYPE_TA},
1003     [L4ID_WDTIMER2    ] = {0x00314000, 0x1000, L4TYPE_GENERIC},
1004     [L4ID_WDTIMER2_TA ] = {0x00315000, 0x1000, L4TYPE_TA},
1005     [L4ID_GPTIMER1    ] = {0x00318000, 0x1000, L4TYPE_GENERIC},
1006     [L4ID_GPTIMER1_TA ] = {0x00319000, 0x1000, L4TYPE_TA},
1007     [L4ID_32KTIMER    ] = {0x00320000, 0x1000, L4TYPE_GENERIC},
1008     [L4ID_32KTIMER_TA ] = {0x00321000, 0x1000, L4TYPE_TA},
1009     [L4ID_WAKEUP_AP   ] = {0x00328000, 0x0800, L4TYPE_AP},
1010     [L4ID_WAKEUP_C_IP ] = {0x00328800, 0x0800, L4TYPE_IA},
1011     [L4ID_WAKEUP_LA   ] = {0x00329000, 0x1000, L4TYPE_LA},
1012     [L4ID_WAKEUP_E_IP ] = {0x0032a000, 0x0800, L4TYPE_IA},
1013     /* L4-Per */
1014     [L4ID_PER_AP      ] = {0x01000000, 0x0800, L4TYPE_AP},
1015     [L4ID_PER_IP      ] = {0x01000800, 0x0800, L4TYPE_IA},
1016     [L4ID_PER_LA      ] = {0x01001000, 0x1000, L4TYPE_LA},
1017     [L4ID_UART3       ] = {0x01020000, 0x1000, L4TYPE_GENERIC},
1018     [L4ID_UART3_TA    ] = {0x01021000, 0x1000, L4TYPE_TA},
1019     [L4ID_MCBSP2      ] = {0x01022000, 0x1000, L4TYPE_GENERIC},
1020     [L4ID_MCBSP2_TA   ] = {0x01023000, 0x1000, L4TYPE_TA},
1021     [L4ID_MCBSP3      ] = {0x01024000, 0x1000, L4TYPE_GENERIC},
1022     [L4ID_MCBSP3_TA   ] = {0x01025000, 0x1000, L4TYPE_TA},
1023     [L4ID_MCBSP4      ] = {0x01026000, 0x1000, L4TYPE_GENERIC},
1024     [L4ID_MCBSP4_TA   ] = {0x01027000, 0x1000, L4TYPE_TA},
1025     [L4ID_MCBSP2S     ] = {0x01028000, 0x1000, L4TYPE_GENERIC},
1026     [L4ID_MCBSP2S_TA  ] = {0x01029000, 0x1000, L4TYPE_TA},
1027     [L4ID_MCBSP3S     ] = {0x0102a000, 0x1000, L4TYPE_GENERIC},
1028     [L4ID_MCBSP3S_TA  ] = {0x0102b000, 0x1000, L4TYPE_TA},
1029     [L4ID_WDTIMER3    ] = {0x01030000, 0x1000, L4TYPE_GENERIC},
1030     [L4ID_WDTIMER3_TA ] = {0x01031000, 0x1000, L4TYPE_TA},
1031     [L4ID_GPTIMER2    ] = {0x01032000, 0x1000, L4TYPE_GENERIC},
1032     [L4ID_GPTIMER2_TA ] = {0x01033000, 0x1000, L4TYPE_TA},
1033     [L4ID_GPTIMER3    ] = {0x01034000, 0x1000, L4TYPE_GENERIC},
1034     [L4ID_GPTIMER3_TA ] = {0x01035000, 0x1000, L4TYPE_TA},
1035     [L4ID_GPTIMER4    ] = {0x01036000, 0x1000, L4TYPE_GENERIC},
1036     [L4ID_GPTIMER4_TA ] = {0x01037000, 0x1000, L4TYPE_TA},
1037     [L4ID_GPTIMER5    ] = {0x01038000, 0x1000, L4TYPE_GENERIC},
1038     [L4ID_GPTIMER5_TA ] = {0x01039000, 0x1000, L4TYPE_TA},
1039     [L4ID_GPTIMER6    ] = {0x0103a000, 0x1000, L4TYPE_GENERIC},
1040     [L4ID_GPTIMER6_TA ] = {0x0103b000, 0x1000, L4TYPE_TA},
1041     [L4ID_GPTIMER7    ] = {0x0103c000, 0x1000, L4TYPE_GENERIC},
1042     [L4ID_GPTIMER7_TA ] = {0x0103d000, 0x1000, L4TYPE_TA},
1043     [L4ID_GPTIMER8    ] = {0x0103e000, 0x1000, L4TYPE_GENERIC},
1044     [L4ID_GPTIMER8_TA ] = {0x0103f000, 0x1000, L4TYPE_TA},
1045     [L4ID_GPTIMER9    ] = {0x01040000, 0x1000, L4TYPE_GENERIC},
1046     [L4ID_GPTIMER9_TA ] = {0x01041000, 0x1000, L4TYPE_TA},
1047     [L4ID_GPIO2       ] = {0x01050000, 0x1000, L4TYPE_GENERIC},
1048     [L4ID_GPIO2_TA    ] = {0x01051000, 0x1000, L4TYPE_TA},
1049     [L4ID_GPIO3       ] = {0x01052000, 0x1000, L4TYPE_GENERIC},
1050     [L4ID_GPIO3_TA    ] = {0x01053000, 0x1000, L4TYPE_TA},
1051     [L4ID_GPIO4       ] = {0x01054000, 0x1000, L4TYPE_GENERIC},
1052     [L4ID_GPIO4_TA    ] = {0x01055000, 0x1000, L4TYPE_TA},
1053     [L4ID_GPIO5       ] = {0x01056000, 0x1000, L4TYPE_GENERIC},
1054     [L4ID_GPIO5_TA    ] = {0x01057000, 0x1000, L4TYPE_TA},
1055     [L4ID_GPIO6       ] = {0x01058000, 0x1000, L4TYPE_GENERIC},
1056     [L4ID_GPIO6_TA    ] = {0x01059000, 0x1000, L4TYPE_TA},
1057     /* L4-Emu */
1058     [L4ID_EMU_AP      ] = {0x0c006000, 0x0800, L4TYPE_AP},
1059     [L4ID_EMU_IP_C    ] = {0x0c006800, 0x0800, L4TYPE_IA},
1060     [L4ID_EMU_LA      ] = {0x0c007000, 0x1000, L4TYPE_LA},
1061     [L4ID_EMU_IP_DAP  ] = {0x0c008000, 0x0800, L4TYPE_IA},
1062     [L4ID_MPUEMU      ] = {0x0c010000, 0x8000, L4TYPE_GENERIC},
1063     [L4ID_MPUEMU_TA   ] = {0x0c018000, 0x1000, L4TYPE_TA},
1064     [L4ID_TPIU        ] = {0x0c019000, 0x1000, L4TYPE_GENERIC},
1065     [L4ID_TPIU_TA     ] = {0x0c01a000, 0x1000, L4TYPE_TA},
1066     [L4ID_ETB         ] = {0x0c01b000, 0x1000, L4TYPE_GENERIC},
1067     [L4ID_ETB_TA      ] = {0x0c01c000, 0x1000, L4TYPE_TA},
1068     [L4ID_DAPCTL      ] = {0x0c01d000, 0x1000, L4TYPE_GENERIC},
1069     [L4ID_DAPCTL_TA   ] = {0x0c01e000, 0x1000, L4TYPE_TA},
1070     [L4ID_EMU_PRM_A   ] = {0x0c706000, 0x2000, L4TYPE_GENERIC},
1071     [L4ID_EMU_PRM_B   ] = {0x0c706800, 0x0800, L4TYPE_GENERIC},
1072     [L4ID_EMU_PRM_TA  ] = {0x0c709000, 0x1000, L4TYPE_TA},
1073     [L4ID_EMU_GPIO1   ] = {0x0c710000, 0x1000, L4TYPE_GENERIC},
1074     [L4ID_EMU_GPIO1_TA] = {0x0c711000, 0x1000, L4TYPE_TA},
1075     [L4ID_EMU_WDTM2   ] = {0x0c714000, 0x1000, L4TYPE_GENERIC},
1076     [L4ID_EMU_WDTM2_TA] = {0x0c715000, 0x1000, L4TYPE_TA},
1077     [L4ID_EMU_GPTM1   ] = {0x0c718000, 0x1000, L4TYPE_GENERIC},
1078     [L4ID_EMU_GPTM1_TA] = {0x0c719000, 0x1000, L4TYPE_TA},
1079     [L4ID_EMU_32KTM   ] = {0x0c720000, 0x1000, L4TYPE_GENERIC},
1080     [L4ID_EMU_32KTM_TA] = {0x0c721000, 0x1000, L4TYPE_TA},
1081     [L4ID_EMU_WKUP_AP ] = {0x0c728000, 0x0800, L4TYPE_AP},
1082     [L4ID_EMU_WKUP_IPC] = {0x0c728800, 0x0800, L4TYPE_IA},
1083     [L4ID_EMU_WKUP_LA ] = {0x0c729000, 0x1000, L4TYPE_LA},
1084     [L4ID_EMU_WKUP_IPE] = {0x0c72a000, 0x0800, L4TYPE_IA},
1085 };
1086
1087 typedef enum {
1088     L4A_SCM = 0,
1089     L4A_CM,
1090     L4A_PRM,
1091     L4A_GPTIMER1,
1092     L4A_GPTIMER2,
1093     L4A_GPTIMER3,
1094     L4A_GPTIMER4,
1095     L4A_GPTIMER5,
1096     L4A_GPTIMER6,
1097     L4A_GPTIMER7,
1098     L4A_GPTIMER8,
1099     L4A_GPTIMER9,
1100     L4A_GPTIMER10,
1101     L4A_GPTIMER11,
1102     L4A_GPTIMER12,
1103     L4A_WDTIMER2,
1104     L4A_32KTIMER,
1105     L4A_UART1,
1106     L4A_UART2,
1107     L4A_UART3,
1108     L4A_DSS,
1109     L4A_GPIO1,
1110     L4A_GPIO2,
1111     L4A_GPIO3,
1112     L4A_GPIO4,
1113     L4A_GPIO5,
1114     L4A_GPIO6,
1115     L4A_MMC1,
1116     L4A_MMC2,
1117     L4A_MMC3,
1118     L4A_I2C1,
1119     L4A_I2C2,
1120     L4A_I2C3,
1121     L4A_TAP,
1122     L4A_USBHS_OTG,
1123     L4A_USBHS_HOST,
1124     L4A_USBHS_TLL
1125 } omap3_l4_agent_info_id_t;
1126
1127 struct omap3_l4_agent_info_s {
1128     omap3_l4_agent_info_id_t agent_id;
1129     omap3_l4_region_id_t     first_region_id;
1130     int                      region_count;
1131 };
1132
1133 static const struct omap3_l4_agent_info_s omap3_l4_agent_info[] = {
1134     /* L4-Core Agents */
1135     {L4A_DSS,        L4ID_DSI,       6},
1136     /* TODO: camera */
1137     {L4A_USBHS_OTG,  L4ID_HSUSBOTG,  2},
1138     {L4A_USBHS_HOST, L4ID_HSUSBHOST, 2},
1139     {L4A_USBHS_TLL,  L4ID_USBTLL,    2},
1140     {L4A_UART1,      L4ID_UART1,     2},
1141     {L4A_UART2,      L4ID_UART2,     2},
1142     {L4A_I2C1,       L4ID_I2C1,      2},
1143     {L4A_I2C2,       L4ID_I2C2,      2},
1144     {L4A_I2C3,       L4ID_I2C3,      2},
1145     /* TODO: McBSP1 */
1146     /* TODO: McBSP5 */
1147     {L4A_GPTIMER10,  L4ID_GPTIMER10, 2},
1148     {L4A_GPTIMER11,  L4ID_GPTIMER11, 2},
1149     /* TODO: SPI1 */
1150     /* TODO: SPI2 */
1151     {L4A_MMC1,       L4ID_MMCSDIO1,  2},
1152     {L4A_MMC2,       L4ID_MMCSDIO2,  2},
1153     {L4A_MMC3,       L4ID_MMCSDIO3,  2},
1154     /* TODO: HDQ/1-Wire */
1155     /* TODO: Mailbox */
1156     /* TODO: SPI3 */
1157     /* TODO: SPI4 */
1158     /* TODO: SDMA */
1159     {L4A_CM,         L4ID_CM_A,      3},
1160     {L4A_SCM,        L4ID_SCM,       2},
1161     {L4A_TAP,        L4ID_TAP,       2},
1162     /* L4-Wakeup Agents */
1163     {L4A_GPTIMER12,  L4ID_GPTIMER12, 2},
1164     {L4A_PRM,        L4ID_PRM_A,     3},
1165     {L4A_GPIO1,      L4ID_GPIO1,     2},
1166     {L4A_WDTIMER2,   L4ID_WDTIMER2,  2},
1167     {L4A_GPTIMER1,   L4ID_GPTIMER1,  2},
1168     {L4A_32KTIMER,   L4ID_32KTIMER,  2},
1169     /* L4-Per Agents */
1170     {L4A_UART3,      L4ID_UART3,     2},
1171     /* TODO: McBSP2 */
1172     /* TODO: McBSP3 */
1173     {L4A_GPTIMER2,   L4ID_GPTIMER2,  2},
1174     {L4A_GPTIMER3,   L4ID_GPTIMER3,  2},
1175     {L4A_GPTIMER4,   L4ID_GPTIMER4,  2},
1176     {L4A_GPTIMER5,   L4ID_GPTIMER5,  2},
1177     {L4A_GPTIMER6,   L4ID_GPTIMER6,  2},
1178     {L4A_GPTIMER7,   L4ID_GPTIMER7,  2},
1179     {L4A_GPTIMER8,   L4ID_GPTIMER8,  2},
1180     {L4A_GPTIMER9,   L4ID_GPTIMER9,  2},
1181     {L4A_GPIO2,      L4ID_GPIO2,     2},
1182     {L4A_GPIO3,      L4ID_GPIO3,     2},
1183     {L4A_GPIO4,      L4ID_GPIO4,     2},
1184     {L4A_GPIO5,      L4ID_GPIO5,     2},
1185     {L4A_GPIO6,      L4ID_GPIO6,     2},
1186 };
1187
1188 static uint32_t omap3_l4ta_read(void *opaque, target_phys_addr_t addr)
1189 {
1190     struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
1191
1192     switch (addr) {
1193         case 0x00: /* COMPONENT_L */
1194             return s->component;
1195         case 0x04: /* COMPONENT_H */
1196             return 0;
1197         case 0x18: /* CORE_L */
1198             return s->component;
1199         case 0x1c: /* CORE_H */
1200             return (s->component >> 16);
1201         case 0x20: /* AGENT_CONTROL_L */
1202             return s->control;
1203         case 0x24: /* AGENT_CONTROL_H */
1204             return s->control_h;
1205         case 0x28: /* AGENT_STATUS_L */
1206             return s->status;
1207         case 0x2c: /* AGENT_STATUS_H */
1208             return 0;
1209         default:
1210             break;
1211     }
1212
1213     OMAP_BAD_REG(s->base + addr);
1214     return 0;
1215 }
1216
1217 static void omap3_l4ta_write(void *opaque, target_phys_addr_t addr,
1218                              uint32_t value)
1219 {
1220     struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
1221
1222     switch (addr) {
1223         case 0x00: /* COMPONENT_L */
1224         case 0x04: /* COMPONENT_H */
1225         case 0x18: /* CORE_L */
1226         case 0x1c: /* CORE_H */
1227             OMAP_RO_REG(s->base + addr);
1228             break;
1229         case 0x20: /* AGENT_CONTROL_L */
1230             s->control = value & 0x00000701;
1231             break;
1232         case 0x24: /* AGENT_CONTROL_H */
1233             s->control_h = value & 0x100; /* TODO: shouldn't this be read-only? */
1234             break;
1235         case 0x28: /* AGENT_STATUS_L */
1236             if (value & 0x100)
1237                 s->status &= ~0x100; /* REQ_TIMEOUT */
1238             break;
1239         case 0x2c: /* AGENT_STATUS_H */
1240             /* no writable bits although the register is listed as RW */
1241             break;
1242         default:
1243             OMAP_BAD_REG(s->base + addr);
1244             break;
1245     }
1246 }
1247
1248 static CPUReadMemoryFunc *omap3_l4ta_readfn[] = {
1249     omap_badwidth_read32,
1250     omap_badwidth_read32,
1251     omap3_l4ta_read,
1252 };
1253
1254 static CPUWriteMemoryFunc *omap3_l4ta_writefn[] = {
1255     omap_badwidth_write32,
1256     omap_badwidth_write32,
1257     omap3_l4ta_write,
1258 };
1259
1260 static struct omap_target_agent_s *omap3_l4ta_init(struct omap_l4_s *bus, int cs)
1261 {
1262     int i, iomemtype;
1263     struct omap_target_agent_s *ta = 0;
1264     const struct omap3_l4_agent_info_s *info = 0;
1265
1266     for (i = 0; i < bus->ta_num; i++)
1267         if (omap3_l4_agent_info[i].agent_id == cs) {
1268             ta = &bus->ta[i];
1269             info = &omap3_l4_agent_info[i];
1270             break;
1271         }
1272     if (!ta) {
1273         fprintf(stderr, "%s: invalid agent id (%i)\n", __FUNCTION__, cs);
1274         exit(-1);
1275     }
1276     if (ta->bus) {
1277         fprintf(stderr, "%s: target agent (%d) already initialized\n",
1278                 __FUNCTION__, cs);
1279         exit(-1);
1280     }
1281
1282     ta->bus = bus;
1283     ta->start = &omap3_l4_region[info->first_region_id];
1284     ta->regions = info->region_count;
1285
1286     ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
1287     ta->status = 0x00000000;
1288     ta->control = 0x00000200;
1289
1290     for (i = 0; i < info->region_count; i++)
1291         if (omap3_l4_region[info->first_region_id + i].access == L4TYPE_TA)
1292             break;
1293     if (i >= info->region_count) {
1294         fprintf(stderr, "%s: specified agent (%d) has no TA region\n",
1295                 __FUNCTION__, cs);
1296         exit(-1);
1297     }
1298
1299     iomemtype = l4_register_io_memory(0, omap3_l4ta_readfn,
1300                                       omap3_l4ta_writefn, ta);
1301     ta->base = omap_l4_attach(ta, i, iomemtype);
1302
1303     return ta;
1304 }
1305
1306 /* common PRM domain registers */
1307 struct omap3_prm_domain_s {
1308     uint32_t rm_rstctrl;   /* 50 */
1309     uint32_t rm_rstst;     /* 58 */
1310     uint32_t pm_wken;      /* a0 */
1311     uint32_t pm_mpugrpsel; /* a4 */
1312     uint32_t pm_ivagrpsel; /* a8 */
1313     uint32_t pm_wkst;      /* b0 */
1314     uint32_t pm_wkdep;     /* c8 */
1315     uint32_t pm_pwstctrl;  /* e0 */
1316     uint32_t pm_pwstst;    /* e4 */
1317     uint32_t pm_prepwstst; /* e8 */
1318 };
1319
1320 struct omap3_prm_s {
1321     qemu_irq mpu_irq;
1322     qemu_irq iva_irq;
1323     struct omap_mpu_state_s *omap;
1324
1325     struct omap3_prm_domain_s iva2;
1326     struct omap3_prm_domain_s mpu;
1327     struct omap3_prm_domain_s core;
1328     struct omap3_prm_domain_s sgx;
1329     struct omap3_prm_domain_s wkup;
1330     struct omap3_prm_domain_s dss;
1331     struct omap3_prm_domain_s cam;
1332     struct omap3_prm_domain_s per;
1333     struct omap3_prm_domain_s emu;
1334     struct omap3_prm_domain_s neon;
1335     struct omap3_prm_domain_s usbhost;
1336
1337     uint32_t iva2_prm_irqstatus;
1338     uint32_t iva2_prm_irqenable;
1339
1340     uint32_t mpu_pm_evgenctrl;
1341     uint32_t mpu_pm_evgenontim;
1342     uint32_t mpu_pm_evgenofftim;
1343
1344     uint32_t core_pm_wkst3;
1345     uint32_t core_pm_wken3;
1346     uint32_t core_pm_iva2grpsel3;
1347     uint32_t core_pm_mpugrpsel3;
1348
1349     struct {
1350         uint32_t prm_revision;
1351         uint32_t prm_sysconfig;
1352         uint32_t prm_irqstatus_mpu;
1353         uint32_t prm_irqenable_mpu;
1354     } ocp;
1355
1356     struct {
1357         uint32_t prm_clksel;
1358         uint32_t prm_clkout_ctrl;
1359     } ccr; /* clock_control_reg */
1360
1361     struct {
1362         uint32_t prm_vc_smps_sa;
1363         uint32_t prm_vc_smps_vol_ra;
1364         uint32_t prm_vc_smps_cmd_ra;
1365         uint32_t prm_vc_cmd_val_0;
1366         uint32_t prm_vc_cmd_val_1;
1367         uint32_t prm_vc_hc_conf;
1368         uint32_t prm_vc_i2c_cfg;
1369         uint32_t prm_vc_bypass_val;
1370         uint32_t prm_rstctrl;
1371         uint32_t prm_rsttimer;
1372         uint32_t prm_rstst;
1373         uint32_t prm_voltctrl;
1374         uint32_t prm_sram_pcharge;
1375         uint32_t prm_clksrc_ctrl;
1376         uint32_t prm_obs;
1377         uint32_t prm_voltsetup1;
1378         uint32_t prm_voltoffset;
1379         uint32_t prm_clksetup;
1380         uint32_t prm_polctrl;
1381         uint32_t prm_voltsetup2;
1382     } gr; /* global_reg */
1383 };
1384
1385 static void omap3_prm_int_update(struct omap3_prm_s *s)
1386 {
1387     qemu_set_irq(s->mpu_irq, s->ocp.prm_irqstatus_mpu & s->ocp.prm_irqenable_mpu);
1388     qemu_set_irq(s->iva_irq, s->iva2_prm_irqstatus & s->iva2_prm_irqenable);
1389 }
1390
1391 static void omap3_prm_reset(struct omap3_prm_s *s)
1392 {
1393     s->iva2.rm_rstctrl    = 0x7;
1394     s->iva2.rm_rstst      = 0x1;
1395     s->iva2.pm_wkdep      = 0xb3;
1396     s->iva2.pm_pwstctrl   = 0xff0f07;
1397     s->iva2.pm_pwstst     = 0xff7;
1398     s->iva2.pm_prepwstst  = 0x0;
1399     s->iva2_prm_irqstatus = 0x0;
1400     s->iva2_prm_irqenable = 0x0;
1401
1402     s->ocp.prm_revision      = 0x10;
1403     s->ocp.prm_sysconfig     = 0x1;
1404     s->ocp.prm_irqstatus_mpu = 0x0;
1405     s->ocp.prm_irqenable_mpu = 0x0;
1406
1407     s->mpu.rm_rstst       = 0x1;
1408     s->mpu.pm_wkdep       = 0xa5;
1409     s->mpu.pm_pwstctrl    = 0x30107;
1410     s->mpu.pm_pwstst      = 0xc7;
1411     s->mpu.pm_pwstst      = 0x0;
1412     s->mpu_pm_evgenctrl   = 0x12;
1413     s->mpu_pm_evgenontim  = 0x0;
1414     s->mpu_pm_evgenofftim = 0x0;
1415
1416     s->core.rm_rstst       = 0x1;
1417     s->core.pm_wken        = 0xc33ffe18;
1418     s->core.pm_mpugrpsel   = 0xc33ffe18;
1419     s->core.pm_ivagrpsel   = 0xc33ffe18;
1420     s->core.pm_wkst        = 0x0;
1421     s->core.pm_pwstctrl    = 0xf0307;
1422     s->core.pm_pwstst      = 0xf7;
1423     s->core.pm_prepwstst   = 0x0;
1424     s->core_pm_wkst3       = 0x0;
1425     s->core_pm_wken3       = 0x4;
1426     s->core_pm_iva2grpsel3 = 0x4;
1427     s->core_pm_mpugrpsel3  = 0x4;
1428
1429     s->sgx.rm_rstst     = 0x1;
1430     s->sgx.pm_wkdep     = 0x16;
1431     s->sgx.pm_pwstctrl  = 0x30107;
1432     s->sgx.pm_pwstst    = 0x3;
1433     s->sgx.pm_prepwstst = 0x0;
1434
1435     s->wkup.pm_wken      = 0x3cb;
1436     s->wkup.pm_mpugrpsel = 0x3cb;
1437     s->wkup.pm_ivagrpsel = 0x0;
1438     s->wkup.pm_wkst      = 0x0;
1439     s->wkup.pm_pwstst    = 0x3; /* TODO: check on real hardware */
1440
1441     s->ccr.prm_clksel      = 0x3; /* TRM says 0x4, but on HW this is 0x3 */
1442     s->ccr.prm_clkout_ctrl = 0x80;
1443
1444     s->dss.rm_rstst     = 0x1;
1445     s->dss.pm_wken      = 0x1;
1446     s->dss.pm_wkdep     = 0x16;
1447     s->dss.pm_pwstctrl  = 0x30107;
1448     s->dss.pm_pwstst    = 0x3;
1449     s->dss.pm_prepwstst = 0x0;
1450
1451     s->cam.rm_rstst     = 0x1;
1452     s->cam.pm_wkdep     = 0x16;
1453     s->cam.pm_pwstctrl  = 0x30107;
1454     s->cam.pm_pwstst    = 0x3;
1455     s->cam.pm_prepwstst = 0x0;
1456
1457     s->per.rm_rstst     = 0x1;
1458     s->per.pm_wken      = 0x3efff;
1459     s->per.pm_mpugrpsel = 0x3efff;
1460     s->per.pm_ivagrpsel = 0x3efff;
1461     s->per.pm_wkst      = 0x0;
1462     s->per.pm_wkdep     = 0x17;
1463     s->per.pm_pwstctrl  = 0x30107;
1464     s->per.pm_pwstst    = 0x7;
1465     s->per.pm_prepwstst = 0x0;
1466
1467     s->emu.rm_rstst  = 0x1;
1468     s->emu.pm_pwstst = 0x13;
1469
1470     s->gr.prm_vc_smps_sa     = 0x0;
1471     s->gr.prm_vc_smps_vol_ra = 0x0;
1472     s->gr.prm_vc_smps_cmd_ra = 0x0;
1473     s->gr.prm_vc_cmd_val_0   = 0x0;
1474     s->gr.prm_vc_cmd_val_1   = 0x0;
1475     s->gr.prm_vc_hc_conf     = 0x0;
1476     s->gr.prm_vc_i2c_cfg     = 0x18;
1477     s->gr.prm_vc_bypass_val  = 0x0;
1478     s->gr.prm_rstctrl        = 0x0;
1479     s->gr.prm_rsttimer       = 0x1006;
1480     s->gr.prm_rstst          = 0x1;
1481     s->gr.prm_voltctrl       = 0x0;
1482     s->gr.prm_sram_pcharge   = 0x50;
1483     s->gr.prm_clksrc_ctrl    = 0x43;
1484     s->gr.prm_obs            = 0x0;
1485     s->gr.prm_voltsetup1     = 0x0;
1486     s->gr.prm_voltoffset     = 0x0;
1487     s->gr.prm_clksetup       = 0x0;
1488     s->gr.prm_polctrl        = 0xa;
1489     s->gr.prm_voltsetup2     = 0x0;
1490
1491     s->neon.rm_rstst     = 0x1;
1492     s->neon.pm_wkdep     = 0x2;
1493     s->neon.pm_pwstctrl  = 0x7;
1494     s->neon.pm_pwstst    = 0x3;
1495     s->neon.pm_prepwstst = 0x0;
1496
1497     s->usbhost.rm_rstst     = 0x1;
1498     s->usbhost.pm_wken      = 0x1;
1499     s->usbhost.pm_mpugrpsel = 0x1;
1500     s->usbhost.pm_ivagrpsel = 0x1;
1501     s->usbhost.pm_wkst      = 0x0;
1502     s->usbhost.pm_wkdep     = 0x17;
1503     s->usbhost.pm_pwstctrl  = 0x30107;
1504     s->usbhost.pm_pwstst    = 0x3;
1505     s->usbhost.pm_prepwstst = 0x0;
1506
1507     omap3_prm_int_update(s);
1508 }
1509
1510 static uint32_t omap3_prm_read(void *opaque, target_phys_addr_t addr)
1511 {
1512     struct omap3_prm_s *s = (struct omap3_prm_s *)opaque;
1513     struct omap3_prm_domain_s *d = 0;
1514
1515     TRACE("%04x", addr);
1516
1517     /* handle common domain registers first - all domains may not
1518        have all common registers though but we're returning zeroes there */
1519     switch ((addr >> 8) & 0xff) {
1520         case 0x00: d = &s->iva2; break;
1521         case 0x09: d = &s->mpu; break;
1522         case 0x0a: d = &s->core; break;
1523         case 0x0b: d = &s->sgx; break;
1524         case 0x0c: d = &s->wkup; break;
1525         case 0x0e: d = &s->dss; break;
1526         case 0x0f: d = &s->cam; break;
1527         case 0x10: d = &s->per; break;
1528         case 0x11: d = &s->emu; break;
1529         case 0x13: d = &s->neon; break;
1530         case 0x14: d = &s->usbhost; break;
1531         default: break;
1532     }
1533     if (d)
1534         switch (addr & 0xff) {
1535             case 0x50: return d->rm_rstctrl;
1536             case 0x58: return d->rm_rstst;
1537             case 0xa0: return d->pm_wken;
1538             case 0xa4: return d->pm_mpugrpsel;
1539             case 0xa8: return d->pm_ivagrpsel;
1540             case 0xb0: return d->pm_wkst;
1541             case 0xc8: return d->pm_wkdep;
1542             case 0xe0: return d->pm_pwstctrl;
1543             case 0xe4: return d->pm_pwstst;
1544             case 0xe8: return d->pm_prepwstst;
1545             default: break;
1546         }
1547
1548     /* okay, not a common domain register so let's take a closer look */
1549     switch (addr) {
1550         case 0x00f8: return s->iva2_prm_irqstatus;
1551         case 0x00fc: return s->iva2_prm_irqenable;
1552         case 0x0804: return s->ocp.prm_revision;
1553         case 0x0814: return s->ocp.prm_sysconfig;
1554         case 0x0818: return s->ocp.prm_irqstatus_mpu;
1555         case 0x081c: return s->ocp.prm_irqenable_mpu;
1556         case 0x09d4: return s->mpu_pm_evgenctrl;
1557         case 0x09d8: return s->mpu_pm_evgenontim;
1558         case 0x09dc: return s->mpu_pm_evgenofftim;
1559         case 0x0ab8: return s->core_pm_wkst3;
1560         case 0x0af0: return s->core_pm_wken3;
1561         case 0x0af4: return s->core_pm_iva2grpsel3;
1562         case 0x0af8: return s->core_pm_mpugrpsel3;
1563         case 0x0d40: return s->ccr.prm_clksel;
1564         case 0x0d70: return s->ccr.prm_clkout_ctrl;
1565         case 0x0de4: return 0x3; /* TODO: check on real hardware */
1566         case 0x1220: return s->gr.prm_vc_smps_sa;
1567         case 0x1224: return s->gr.prm_vc_smps_vol_ra;
1568         case 0x1228: return s->gr.prm_vc_smps_cmd_ra;
1569         case 0x122c: return s->gr.prm_vc_cmd_val_0;
1570         case 0x1230: return s->gr.prm_vc_cmd_val_1;
1571         case 0x1234: return s->gr.prm_vc_hc_conf;
1572         case 0x1238: return s->gr.prm_vc_i2c_cfg;
1573         case 0x123c: return s->gr.prm_vc_bypass_val;
1574         case 0x1250: return s->gr.prm_rstctrl;
1575         case 0x1254: return s->gr.prm_rsttimer;
1576         case 0x1258: return s->gr.prm_rstst;
1577         case 0x1260: return s->gr.prm_voltctrl;
1578         case 0x1264: return s->gr.prm_sram_pcharge;
1579         case 0x1270: return s->gr.prm_clksrc_ctrl;
1580         case 0x1280: return s->gr.prm_obs;
1581         case 0x1290: return s->gr.prm_voltsetup1;
1582         case 0x1294: return s->gr.prm_voltoffset;
1583         case 0x1298: return s->gr.prm_clksetup;
1584         case 0x129c: return s->gr.prm_polctrl;
1585         case 0x12a0: return s->gr.prm_voltsetup2;
1586         default: break;
1587     }
1588
1589     OMAP_BAD_REG(addr);
1590     return 0;
1591 }
1592
1593 static inline void omap3_prm_clksrc_ctrl_update(struct omap3_prm_s *s,
1594                                                 uint32_t value)
1595 {
1596     if ((value & 0xd0) == 0x40)
1597         omap_clk_setrate(omap_findclk(s->omap, "omap3_sys_clk"), 1, 1);
1598     else if ((value & 0xd0) == 0x80)
1599         omap_clk_setrate(omap_findclk(s->omap, "omap3_sys_clk"), 2, 1);
1600 }
1601
1602 static void omap3_prm_clksel_update(struct omap3_prm_s *s)
1603 {
1604     omap_clk newparent = 0;
1605
1606     switch (s->ccr.prm_clksel & 7) {
1607         case 0: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk12"); break;
1608         case 1: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk13"); break;
1609         case 2: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk192"); break;
1610         case 3: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk26"); break;
1611         case 4: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk384"); break;
1612         case 5: newparent = omap_findclk(s->omap, "omap3_osc_sys_clk168"); break;
1613         default:
1614             fprintf(stderr, "%s: invalid sys_clk input selection (%d) - ignored\n",
1615                     __FUNCTION__, s->ccr.prm_clksel & 7);
1616             break;
1617     }
1618     if (newparent) {
1619         omap_clk_reparent(omap_findclk(s->omap, "omap3_sys_clk"), newparent);
1620         omap_clk_reparent(omap_findclk(s->omap, "omap3_sys_clkout1"), newparent);
1621     }
1622 }
1623
1624 static void omap3_prm_write(void *opaque, target_phys_addr_t addr,
1625                             uint32_t value)
1626 {
1627     struct omap3_prm_s *s = (struct omap3_prm_s *)opaque;
1628
1629     TRACE("%04x = %08x", addr, value);
1630     switch (addr) {
1631         /* IVA2_PRM */
1632         case 0x0050: s->iva2.rm_rstctrl = value & 0x7; break;
1633         case 0x0058: s->iva2.rm_rstst &= ~(value & 0x3f0f); break;
1634         case 0x00c8: s->iva2.pm_wkdep = value & 0xb3; break;
1635         case 0x00e0: s->iva2.pm_pwstctrl = 0xcff000 | (value & 0x300f0f); break;
1636         case 0x00e4: OMAP_RO_REG(addr); break;
1637         case 0x00e8: s->iva2.pm_prepwstst = value & 0xff7;
1638         case 0x00f8:
1639             s->iva2_prm_irqstatus &= ~(value & 0x7);
1640             omap3_prm_int_update(s);
1641             break;
1642         case 0x00fc:
1643             s->iva2_prm_irqenable = value & 0x7;
1644             omap3_prm_int_update(s);
1645             break;
1646         /* OCP_System_Reg_PRM */
1647         case 0x0804: OMAP_RO_REG(addr); break;
1648         case 0x0814: s->ocp.prm_sysconfig = value & 0x1; break;
1649         case 0x0818:
1650             s->ocp.prm_irqstatus_mpu &= ~(value & 0x03c003fd);
1651             omap3_prm_int_update(s);
1652             break;
1653         case 0x081c:
1654             s->ocp.prm_irqenable_mpu = value & 0x03c003fd;
1655             omap3_prm_int_update(s);
1656             break;
1657         /* MPU_PRM */
1658         case 0x0958: s->mpu.rm_rstst &= ~(value & 0x080f); break;
1659         case 0x09c8: s->mpu.pm_wkdep = value & 0xa5; break;
1660         case 0x09d4: s->mpu_pm_evgenctrl = value & 0x1f; break;
1661         case 0x09d8: s->mpu_pm_evgenontim = value; break;
1662         case 0x09dc: s->mpu_pm_evgenofftim = value; break;
1663         case 0x09e0: s->mpu.pm_pwstctrl = value & 0x3010f; break;
1664         case 0x09e4: OMAP_RO_REG(addr); break;
1665         case 0x09e8: s->mpu.pm_prepwstst = value & 0xc7; break;
1666         /* CORE_PRM */
1667         case 0x0a50: s->core.rm_rstctrl = value & 0x3; break; /* TODO: check if available on real hw */
1668         case 0x0a58: s->core.rm_rstst &= ~(value & 0x7); break;
1669         case 0x0aa0: s->core.pm_wken = 0x80000008 | (value & 0x433ffe10); break;
1670         case 0x0aa4: s->core.pm_mpugrpsel = 0x80000008 | (value & 0x433ffe10); break;
1671         case 0x0aa8: s->core.pm_ivagrpsel = 0x80000008 | (value & 0x433ffe10); break;
1672         case 0x0ab0: s->core.pm_wkst = value & 0x433ffe10; break;
1673         case 0x0ab8: s->core_pm_wkst3 &= ~(value & 0x4); break;
1674         case 0x0ae0: s->core.pm_pwstctrl = (value & 0x0f031f); break;
1675         case 0x0ae4: OMAP_RO_REG(addr); break;
1676         case 0x0ae8: s->core.pm_prepwstst = value & 0xf7; break;
1677         case 0x0af0: s->core_pm_wken3 = value & 0x4; break;
1678         case 0x0af4: s->core_pm_iva2grpsel3 = value & 0x4; break;
1679         case 0x0af8: s->core_pm_mpugrpsel3 = value & 0x4; break;
1680         /* SGX_PRM */
1681         case 0x0b58: s->sgx.rm_rstst &= ~(value & 0xf); break;
1682         case 0x0bc8: s->sgx.pm_wkdep = value & 0x16; break;
1683         case 0x0be0: s->sgx.pm_pwstctrl = 0x030104 | (value & 0x3); break;
1684         case 0x0be4: OMAP_RO_REG(addr); break;
1685         case 0x0be8: s->sgx.pm_prepwstst = value & 0x3; break;
1686         /* WKUP_PRM */
1687         case 0x0ca0: s->wkup.pm_wken = 0x2 | (value & 0x0103c9); break;
1688         case 0x0ca4: s->wkup.pm_mpugrpsel = 0x0102 | (value & 0x02c9); break;
1689         case 0x0ca8: s->wkup.pm_ivagrpsel = value & 0x03cb; break;
1690         case 0x0cb0: s->wkup.pm_wkst &= ~(value & 0x0103cb); break;
1691         /* Clock_Control_Reg_PRM */
1692         case 0x0d40:
1693             s->ccr.prm_clksel = value & 0x7;
1694             omap3_prm_clksel_update(s);
1695             break;
1696         case 0x0d70:
1697             s->ccr.prm_clkout_ctrl = value & 0x80;
1698             omap_clk_onoff(omap_findclk(s->omap, "omap3_sys_clkout1"),
1699                            s->ccr.prm_clkout_ctrl & 0x80);
1700             break;
1701         /* DSS_PRM */
1702         case 0x0e58: s->dss.rm_rstst &= ~(value & 0xf); break;
1703         case 0x0ea0: s->dss.pm_wken = value & 1; break;
1704         case 0x0ec8: s->dss.pm_wkdep = value & 0x16; break;
1705         case 0x0ee0: s->dss.pm_pwstctrl = 0x030104 | (value & 3); break;
1706         case 0x0ee4: OMAP_RO_REG(addr); break;
1707         case 0x0ee8: s->dss.pm_prepwstst = value & 3; break;
1708         /* CAM_PRM */
1709         case 0x0f58: s->cam.rm_rstst &= (value & 0xf); break;
1710         case 0x0fc8: s->cam.pm_wkdep = value & 0x16; break;
1711         case 0x0fe0: s->cam.pm_pwstctrl = 0x030104 | (value & 3); break;
1712         case 0x0fe4: OMAP_RO_REG(addr); break;
1713         case 0x0fe8: s->cam.pm_prepwstst = value & 0x3; break;
1714         /* PER_PRM */
1715         case 0x1058: s->per.rm_rstst &= ~(value & 0xf); break;
1716         case 0x10a0: s->per.pm_wken = value & 0x03efff; break;
1717         case 0x10a4: s->per.pm_mpugrpsel = value & 0x03efff; break;
1718         case 0x10a8: s->per.pm_ivagrpsel = value & 0x03efff; break;
1719         case 0x10b0: s->per.pm_wkst &= ~(value & 0x03efff); break;
1720         case 0x10c8: s->per.pm_wkdep = value & 0x17; break;
1721         case 0x10e0: s->per.pm_pwstctrl = 0x030100 | (value & 7); break;
1722         case 0x10e4: OMAP_RO_REG(addr); break;
1723         case 0x10e8: s->per.pm_prepwstst = value & 0x7; break;
1724         /* EMU_PRM */
1725         case 0x1158: s->emu.rm_rstst &= ~(value & 7); break;
1726         case 0x11e4: OMAP_RO_REG(addr); break;
1727         /* Global_Reg_PRM */
1728         case 0x1220: s->gr.prm_vc_smps_sa = value & 0x7f007f; break;
1729         case 0x1224: s->gr.prm_vc_smps_vol_ra = value & 0xff00ff; break;
1730         case 0x1228: s->gr.prm_vc_smps_cmd_ra = value & 0xff00ff; break;
1731         case 0x122c: s->gr.prm_vc_cmd_val_0 = value; break;
1732         case 0x1230: s->gr.prm_vc_cmd_val_1 = value; break;
1733         case 0x1234: s->gr.prm_vc_hc_conf = value & 0x1f001f; break;
1734         case 0x1238: s->gr.prm_vc_i2c_cfg = value & 0x3f; break;
1735         case 0x123c: s->gr.prm_vc_bypass_val = value & 0x01ffff7f; break;
1736         case 0x1250: s->gr.prm_rstctrl = 0; break; /* TODO: resets */
1737         case 0x1254: s->gr.prm_rsttimer = value & 0x1fff; break;
1738         case 0x1258: s->gr.prm_rstst &= ~(value & 0x7fb); break;
1739         case 0x1260: s->gr.prm_voltctrl = value & 0x1f; break;
1740         case 0x1264: s->gr.prm_sram_pcharge = value & 0xff; break;
1741         case 0x1270:
1742             s->gr.prm_clksrc_ctrl = value & 0xd8; /* set osc bypass mode */
1743             omap3_prm_clksrc_ctrl_update(s, s->gr.prm_clksrc_ctrl);
1744             break;
1745         case 0x1280: OMAP_RO_REG(addr); break;
1746         case 0x1290: s->gr.prm_voltsetup1 = value; break;
1747         case 0x1294: s->gr.prm_voltoffset = value & 0xffff; break;
1748         case 0x1298: s->gr.prm_clksetup = value & 0xffff; break;
1749         case 0x129c: s->gr.prm_polctrl = value & 0xf; break;
1750         case 0x12a0: s->gr.prm_voltsetup2 = value & 0xffff; break;
1751         /* NEON_PRM */
1752         case 0x1358: s->neon.rm_rstst &= ~(value & 0xf); break;
1753         case 0x13c8: s->neon.pm_wkdep = value & 0x2; break;
1754         case 0x13e0: s->neon.pm_pwstctrl = 0x4 | (value & 3); break;
1755         case 0x13e4: OMAP_RO_REG(addr); break;
1756         case 0x13e8: s->neon.pm_prepwstst = value & 3; break;
1757         /* USBHOST_PRM */
1758         case 0x1458: s->usbhost.rm_rstst &= ~(value & 0xf); break;
1759         case 0x14a0: s->usbhost.pm_wken = value & 1; break;
1760         case 0x14a4: s->usbhost.pm_mpugrpsel = value & 1; break;
1761         case 0x14a8: s->usbhost.pm_ivagrpsel = value & 1; break;
1762         case 0x14b0: s->usbhost.pm_wkst &= ~(value & 1); break;
1763         case 0x14c8: s->usbhost.pm_wkdep = value & 0x17; break;
1764         case 0x14e0: s->usbhost.pm_pwstctrl = 0x030104 | (value & 0x13); break;
1765         case 0x14e4: OMAP_RO_REG(addr); break;
1766         case 0x14e8: s->usbhost.pm_prepwstst = value & 3; break;
1767         default:
1768             OMAP_BAD_REGV(addr, value);
1769             break;
1770     }
1771 }
1772
1773 static CPUReadMemoryFunc *omap3_prm_readfn[] = {
1774     omap_badwidth_read32,
1775     omap_badwidth_read32,
1776     omap3_prm_read,
1777 };
1778
1779 static CPUWriteMemoryFunc *omap3_prm_writefn[] = {
1780     omap_badwidth_write32,
1781     omap_badwidth_write32,
1782     omap3_prm_write,
1783 };
1784
1785 struct omap3_prm_s *omap3_prm_init(struct omap_target_agent_s *ta,
1786                                    qemu_irq mpu_int, qemu_irq iva_int,
1787                                    struct omap_mpu_state_s *mpu)
1788 {
1789     int iomemtype;
1790     struct omap3_prm_s *s = (struct omap3_prm_s *) qemu_mallocz(sizeof(*s));
1791
1792     s->mpu_irq = mpu_int;
1793     s->iva_irq = iva_int;
1794     s->omap = mpu;
1795     omap3_prm_reset(s);
1796
1797     iomemtype = l4_register_io_memory(0, omap3_prm_readfn,
1798                                       omap3_prm_writefn, s);
1799     omap_l4_attach(ta, 0, iomemtype);
1800     omap_l4_attach(ta, 1, iomemtype);
1801
1802     return s;
1803 }
1804
1805 struct omap3_cm_s {
1806     qemu_irq irq[3];
1807     struct omap_mpu_state_s *mpu;
1808
1809     /* IVA2_CM: base + 0x0000 */
1810     uint32_t cm_fclken_iva2;       /* 00 */
1811     uint32_t cm_clken_pll_iva2;    /* 04 */
1812     uint32_t cm_idlest_iva2;       /* 20 */
1813     uint32_t cm_idlest_pll_iva2;   /* 24 */
1814     uint32_t cm_autoidle_pll_iva2; /* 34 */
1815     uint32_t cm_clksel1_pll_iva2;  /* 40 */
1816     uint32_t cm_clksel2_pll_iva2;  /* 44 */
1817     uint32_t cm_clkstctrl_iva2;    /* 48 */
1818     uint32_t cm_clkstst_iva2;      /* 4c */
1819
1820     /* OCP_System_Reg_CM: base + 0x0800 */
1821     uint32_t cm_revision;  /* 00 */
1822     uint32_t cm_sysconfig; /* 10 */
1823
1824     /* MPU_CM: base + 0x0900 */
1825     uint32_t cm_clken_pll_mpu;    /* 04 */
1826     uint32_t cm_idlest_mpu;       /* 20 */
1827     uint32_t cm_idlest_pll_mpu;   /* 24 */
1828     uint32_t cm_autoidle_pll_mpu; /* 34 */
1829     uint32_t cm_clksel1_pll_mpu;  /* 40 */
1830     uint32_t cm_clksel2_pll_mpu;  /* 44 */
1831     uint32_t cm_clkstctrl_mpu;    /* 48 */
1832     uint32_t cm_clkstst_mpu;      /* 4c */
1833
1834     /* CORE_CM: base + 0x0a00 */
1835     uint32_t cm_fclken1_core;   /* 0a00 */
1836     uint32_t cm_fclken3_core;   /* 0a08 */
1837     uint32_t cm_iclken1_core;   /* 0a10 */
1838     uint32_t cm_iclken2_core;   /* 0a14 */
1839     uint32_t cm_iclken3_core;   /* 0a18 */
1840     uint32_t cm_idlest1_core;   /* 0a20 */
1841     uint32_t cm_idlest2_core;   /* 0a24 */
1842     uint32_t cm_idlest3_core;   /* 0a28 */
1843     uint32_t cm_autoidle1_core; /* 0a30 */
1844     uint32_t cm_autoidle2_core; /* 0a34 */
1845     uint32_t cm_autoidle3_core; /* 0a38 */
1846     uint32_t cm_clksel_core;    /* 0a40 */
1847     uint32_t cm_clkstctrl_core; /* 0a48 */
1848     uint32_t cm_clkstst_core;   /* 0a4c */
1849
1850     /* SGX_CM: base + 0x0b00 */
1851     uint32_t cm_fclken_sgx;    /* 00 */
1852     uint32_t cm_iclken_sgx;    /* 10 */
1853     uint32_t cm_idlest_sgx;    /* 20 */
1854     uint32_t cm_clksel_sgx;    /* 40 */
1855     uint32_t cm_sleepdep_sgx;  /* 44 */
1856     uint32_t cm_clkstctrl_sgx; /* 48 */
1857     uint32_t cm_clkstst_sgx;   /* 4c */
1858
1859     /* WKUP_CM: base + 0x0c00 */
1860     uint32_t cm_fclken_wkup;   /* 00 */
1861     uint32_t cm_iclken_wkup;   /* 10 */
1862     uint32_t cm_idlest_wkup;   /* 20 */
1863     uint32_t cm_autoidle_wkup; /* 30 */
1864     uint32_t cm_clksel_wkup;   /* 40 */
1865     uint32_t cm_c48;           /* 48 */
1866
1867     /* Clock_Control_Reg_CM: base + 0x0d00 */
1868     uint32_t cm_clken_pll;     /* 00 */
1869     uint32_t cm_clken2_pll;    /* 04 */
1870     uint32_t cm_idlest_ckgen;  /* 20 */
1871     uint32_t cm_idlest2_ckgen; /* 24 */
1872     uint32_t cm_autoidle_pll;  /* 30 */
1873     uint32_t cm_autoidle2_pll; /* 34 */
1874     uint32_t cm_clksel1_pll;   /* 40 */
1875     uint32_t cm_clksel2_pll;   /* 44 */
1876     uint32_t cm_clksel3_pll;   /* 48 */
1877     uint32_t cm_clksel4_pll;   /* 4c */
1878     uint32_t cm_clksel5_pll;   /* 50 */
1879     uint32_t cm_clkout_ctrl;   /* 70 */
1880
1881     /* DSS_CM: base + 0x0e00 */
1882     uint32_t cm_fclken_dss;    /* 00 */
1883     uint32_t cm_iclken_dss;    /* 10 */
1884     uint32_t cm_idlest_dss;    /* 20 */
1885     uint32_t cm_autoidle_dss;  /* 30 */
1886     uint32_t cm_clksel_dss;    /* 40 */
1887     uint32_t cm_sleepdep_dss;  /* 44 */
1888     uint32_t cm_clkstctrl_dss; /* 48 */
1889     uint32_t cm_clkstst_dss;   /* 4c */
1890
1891    /* CAM_CM: base + 0x0f00 */
1892     uint32_t cm_fclken_cam;    /* 00 */
1893     uint32_t cm_iclken_cam;    /* 10 */
1894     uint32_t cm_idlest_cam;    /* 20 */
1895     uint32_t cm_autoidle_cam;  /* 30 */
1896     uint32_t cm_clksel_cam;    /* 40 */
1897     uint32_t cm_sleepdep_cam;  /* 44 */
1898     uint32_t cm_clkstctrl_cam; /* 48 */
1899     uint32_t cm_clkstst_cam;   /* 4c */
1900
1901     /* PER_CM: base + 0x1000 */
1902     uint32_t cm_fclken_per;    /* 00 */
1903     uint32_t cm_iclken_per;    /* 10 */
1904     uint32_t cm_idlest_per;    /* 20 */
1905     uint32_t cm_autoidle_per;  /* 30 */
1906     uint32_t cm_clksel_per;    /* 40 */
1907     uint32_t cm_sleepdep_per;  /* 44 */
1908     uint32_t cm_clkstctrl_per; /* 48 */
1909     uint32_t cm_clkstst_per;   /* 4c */
1910
1911     /* EMU_CM: base + 0x1100 */
1912     uint32_t cm_clksel1_emu;   /* 40 */
1913     uint32_t cm_clkstctrl_emu; /* 48 */
1914     uint32_t cm_clkstst_emu;   /* 4c */
1915     uint32_t cm_clksel2_emu;   /* 50 */
1916     uint32_t cm_clksel3_emu;   /* 54 */
1917
1918     /* Global_Reg_CM: base + 0x1200 */
1919     uint32_t cm_polctrl; /* 9c */
1920
1921     /* NEON_CM: base + 0x1300 */
1922     uint32_t cm_idlest_neon;    /* 20 */
1923     uint32_t cm_clkstctrl_neon; /* 48 */
1924
1925     /* USBHOST_CM: base + 0x1400 */
1926     uint32_t cm_fclken_usbhost;    /* 00 */
1927     uint32_t cm_iclken_usbhost;    /* 10 */
1928     uint32_t cm_idlest_usbhost;    /* 20 */
1929     uint32_t cm_autoidle_usbhost;  /* 30 */
1930     uint32_t cm_sleepdep_usbhost;  /* 44 */
1931     uint32_t cm_clkstctrl_usbhost; /* 48 */
1932     uint32_t cm_clkstst_usbhost;   /* 4c */
1933 };
1934
1935 /*
1936 static inline void omap3_cm_fclken_wkup_update(struct omap3_cm_s *s,
1937                 uint32_t value)
1938 {
1939
1940         if (value & 0x28)
1941         omap_clk_onoff(omap_findclk(s->mpu,"omap3_wkup_32k_fclk"), 1);
1942     else
1943         omap_clk_onoff(omap_findclk(s->mpu,"omap3_wkup_32k_fclk"), 0);
1944
1945     if (value &0x1)
1946         omap_clk_onoff(omap_findclk(s->mpu,"omap3_gp1_fclk"), 1);
1947     else
1948         omap_clk_onoff(omap_findclk(s->mpu,"omap3_gp1_fclk"), 0);
1949
1950 }
1951 static inline void omap3_cm_iclken_wkup_update(struct omap3_cm_s *s,
1952                 uint32_t value)
1953 {
1954
1955         if (value & 0x3f)
1956         omap_clk_onoff(omap_findclk(s->mpu,"omap3_wkup_l4_iclk"), 1);
1957     else
1958         omap_clk_onoff(omap_findclk(s->mpu,"omap3_wkup_l4_iclk"), 0);
1959
1960 }
1961 */
1962 static inline void omap3_cm_clksel_wkup_update(struct omap3_cm_s *s,
1963                                                uint32_t value)
1964 {
1965     omap_clk gp1_fclk = omap_findclk(s->mpu, "omap3_gp1_fclk");
1966
1967     if (value & 0x1)
1968         omap_clk_reparent(gp1_fclk, omap_findclk(s->mpu, "omap3_sys_clk"));
1969     else
1970         omap_clk_reparent(gp1_fclk, omap_findclk(s->mpu, "omap3_32k_fclk"));
1971     /*Tell GPTIMER to generate new clk rate */
1972     omap_gp_timer_change_clk(s->mpu->gptimer[0]);
1973
1974     TRACE("omap3_gp1_fclk %lld",
1975           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp1_fclk")));
1976
1977     /*TODO:CM_USIM_CLK CLKSEL_RM */
1978 }
1979
1980 static inline void omap3_cm_iva2_update(struct omap3_cm_s *s)
1981 {
1982     uint32_t m = ((s->cm_clksel1_pll_iva2 >> 8) & 0x7ff);
1983     uint32_t n, divide, m2;
1984     omap_clk iva2_clk = omap_findclk(s->mpu, "omap3_iva2_clk");
1985
1986     switch ((s->cm_clken_pll_iva2 & 0x7)) {
1987         case 0x01: /* low power stop mode */
1988         case 0x05: /* low power bypass mode */
1989             s->cm_idlest_pll_iva2 &= ~1;
1990             break;
1991         case 0x07: /* locked */
1992             if (m < 2)
1993                 s->cm_idlest_pll_iva2 &= ~1;
1994             else
1995                 s->cm_idlest_pll_iva2 |= 1;
1996             break;
1997         default:
1998             break;
1999     }
2000
2001     if (s->cm_idlest_pll_iva2 & 1) {
2002         n = (s->cm_clksel1_pll_iva2 & 0x7f);
2003         m2 = (s->cm_clksel2_pll_iva2 & 0x1f);
2004         omap_clk_reparent(iva2_clk, omap_findclk(s->mpu, "omap3_sys_clk"));
2005         omap_clk_setrate(iva2_clk, (n + 1) * m2, m);
2006     } else {
2007         /* bypass mode */
2008         divide = (s->cm_clksel1_pll_iva2 & 0x380000) >> 19;
2009         omap_clk_reparent(iva2_clk, omap_findclk(s->mpu, "omap3_core_clk"));
2010         omap_clk_setrate(iva2_clk, divide, 1);
2011     }
2012 }
2013
2014 static inline void omap3_cm_mpu_update(struct omap3_cm_s *s)
2015 {
2016     uint32_t m = ((s->cm_clksel1_pll_mpu >> 8) & 0x7ff);
2017     uint32_t n, divide, m2;
2018     omap_clk mpu_clk = omap_findclk(s->mpu, "omap3_mpu_clk");
2019
2020     switch ((s->cm_clken_pll_mpu & 0x7)) {
2021         case 0x05: /* low power bypass mode */
2022             s->cm_idlest_pll_mpu &= ~1;
2023             break;
2024         case 0x07: /* locked */
2025             if (m < 2)
2026                 s->cm_idlest_pll_mpu &= ~1;
2027             else
2028                 s->cm_idlest_pll_mpu |= 1;
2029             break;
2030         default:
2031             break;
2032     }
2033
2034     if (s->cm_idlest_pll_mpu & 1) {
2035         n = (s->cm_clksel1_pll_mpu & 0x7f);
2036         m2 = (s->cm_clksel2_pll_mpu & 0x1f);
2037         omap_clk_reparent(mpu_clk, omap_findclk(s->mpu, "omap3_sys_clk"));
2038         omap_clk_setrate(mpu_clk, (n + 1) * m2, m);
2039     } else {
2040         /* bypass mode */
2041         divide = (s->cm_clksel1_pll_mpu & 0x380000) >> 19;
2042         omap_clk_reparent(mpu_clk, omap_findclk(s->mpu, "omap3_core_clk"));
2043         omap_clk_setrate(mpu_clk, divide, 1);
2044     }
2045 }
2046
2047 static inline void omap3_cm_dpll3_update(struct omap3_cm_s *s)
2048 {
2049     uint32_t m = ((s->cm_clksel1_pll >> 16) & 0x7ff);
2050     uint32_t n, m2, m3;
2051
2052     switch ((s->cm_clken_pll & 0x7)) {
2053         case 0x05: /* low power bypass */
2054         case 0x06: /* fast relock bypass */
2055             s->cm_idlest_ckgen &= ~1;
2056             break;
2057         case 0x07: /* locked */
2058             if (m < 2)
2059                 s->cm_idlest_ckgen &= ~1;
2060             else
2061                 s->cm_idlest_ckgen |= 1;
2062             break;
2063         default:
2064             break;
2065     }
2066
2067     if (s->cm_idlest_ckgen & 1) {
2068         n = (s->cm_clksel1_pll & 0x3f00) >> 8;
2069         m2 = (s->cm_clksel1_pll & 0xf8000000) >> 27;
2070         m3 = (s->cm_clksel1_emu & 0x1f0000) >> 16;
2071
2072         if (s->cm_clksel2_emu & 0x80000) {
2073                 /* override control of DPLL3 */
2074                 m = (s->cm_clksel2_emu & 0x7ff) >> 8;
2075                 n = s->cm_clksel2_emu & 0x7f;
2076         }
2077
2078         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core_clk"), (n + 1) * m2, m);
2079         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core2_clk"), (n + 1) * m2, m * 2);
2080         omap_clk_setrate(omap_findclk(s->mpu, "omap3_emu_core_alwon_clk"), (n + 1) * m3, m * 2);
2081     } else {
2082         /* bypass mode */
2083         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core_clk"), 1, 1);
2084         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core2_clk"), 1, 1);
2085         omap_clk_setrate(omap_findclk(s->mpu, "omap3_emu_core_alwon_clk"), 1, 1);
2086     }
2087 }
2088
2089 static inline void omap3_cm_dpll4_update(struct omap3_cm_s *s)
2090 {
2091     uint32_t m = ((s->cm_clksel2_pll >> 8) & 0x7ff);
2092     uint32_t n, m2, m3, m4, m5, m6;
2093
2094     switch (((s->cm_clken_pll >> 16) & 0x7)) {
2095         case 0x01: /* lower power stop mode */
2096             s->cm_idlest_ckgen &= ~2;
2097             break;
2098         case 0x07: /* locked */
2099             if (m < 2)
2100                 s->cm_idlest_ckgen &= ~2;
2101             else
2102                 s->cm_idlest_ckgen |= 2;
2103             break;
2104         default:
2105             break;
2106     }
2107
2108     if (s->cm_idlest_ckgen & 2) {
2109         n = (s->cm_clksel2_pll & 0x7f);
2110         m2 = s->cm_clksel3_pll & 0x1f;
2111         m3 = (s->cm_clksel_dss & 0x1f00) >> 8;
2112         m4 = s->cm_clksel_dss & 0x1f;
2113         m5 = s->cm_clksel_cam & 0x1f;
2114         m6 = (s->cm_clksel1_emu & 0x1f000000) >> 24;
2115
2116         if (s->cm_clksel3_emu & 0x80000) {
2117                 /* override control of DPLL4 */
2118                 m = (s->cm_clksel3_emu & 0x7ff) >> 8;
2119                 n =  s->cm_clksel3_emu & 0x7f;
2120         }
2121
2122         omap_clk_setrate(omap_findclk(s->mpu, "omap3_96m_fclk"), (n + 1) * m2, m * 2);
2123         omap_clk_setrate(omap_findclk(s->mpu, "omap3_54m_fclk"), (n + 1) * m3, m * 2);
2124         omap_clk_setrate(omap_findclk(s->mpu, "omap3_dss1_alwon_fclk"), (n + 1) * m4, m * 2);
2125         omap_clk_setrate(omap_findclk(s->mpu, "omap3_cam_mclk"), (n + 1) * m5, m * 2);
2126         omap_clk_setrate(omap_findclk(s->mpu, "omap3_per_alwon_clk"), (n + 1) * m6, m * 2);
2127     } else {
2128         /* bypass mode */
2129         omap_clk_setrate(omap_findclk(s->mpu, "omap3_96m_fclk"), 1, 1);
2130         omap_clk_setrate(omap_findclk(s->mpu, "omap3_54m_fclk"), 1, 1);
2131         omap_clk_setrate(omap_findclk(s->mpu, "omap3_dss1_alwon_fclk"), 1, 1);
2132         omap_clk_setrate(omap_findclk(s->mpu, "omap3_cam_mclk"), 1, 1);
2133         omap_clk_setrate(omap_findclk(s->mpu, "omap3_per_alwon_clk"), 1, 1);
2134     }
2135 }
2136
2137 static inline void omap3_cm_dpll5_update(struct omap3_cm_s *s)
2138 {
2139     uint32_t m = ((s->cm_clksel4_pll >> 8) & 0x7ff);
2140     uint32_t n, m2;
2141
2142     switch ((s->cm_clken2_pll & 0x7)) {
2143         case 0x01: /* low power stop mode */
2144             s->cm_idlest2_ckgen &= ~1;
2145             break;
2146         case 0x07: /* locked */
2147             if (m < 2)
2148                 s->cm_idlest2_ckgen &= ~1;
2149             else
2150                 s->cm_idlest2_ckgen |= 1;
2151             break;
2152         default:
2153             break;
2154     }
2155
2156     if (s->cm_idlest2_ckgen & 1) {
2157         m = (s->cm_clksel4_pll & 0x7ff00)>>8;
2158         n = s->cm_clksel4_pll & 0x3f00;
2159         m2 = s->cm_clksel5_pll & 0x1f;
2160
2161         omap_clk_setrate(omap_findclk(s->mpu, "omap3_120m_fclk"), (n + 1) * m2, m);
2162     } else {
2163         /* bypass mode */
2164         omap_clk_setrate(omap_findclk(s->mpu, "omap3_120m_fclk"), 1, 1);
2165     }
2166 }
2167
2168 static inline void omap3_cm_48m_update(struct omap3_cm_s *s)
2169 {
2170     if (s->cm_clksel1_pll & 0x8)
2171     {
2172         /*parent is sysaltclk */
2173         omap_clk_reparent(omap_findclk(s->mpu, "omap3_48m_fclk"),
2174                           omap_findclk(s->mpu, "omap3_sys_altclk"));
2175         omap_clk_reparent(omap_findclk(s->mpu, "omap3_12m_fclk"),
2176                           omap_findclk(s->mpu, "omap3_sys_altclk"));
2177         /*TODO:need to set rate ? */
2178
2179     }
2180     else
2181     {
2182         omap_clk_reparent(omap_findclk(s->mpu, "omap3_12m_fclk"),
2183                           omap_findclk(s->mpu, "omap3_96m_fclk"));
2184         omap_clk_reparent(omap_findclk(s->mpu, "omap3_48m_fclk"),
2185                           omap_findclk(s->mpu, "omap3_96m_fclk"));
2186         omap_clk_setrate(omap_findclk(s->mpu, "omap3_48m_fclk"), 2, 1);
2187         omap_clk_setrate(omap_findclk(s->mpu, "omap3_12m_fclk"), 8, 1);
2188
2189     }
2190
2191 }
2192
2193 static inline void omap3_cm_gp10_update(struct omap3_cm_s *s)
2194 {
2195     omap_clk gp10_fclk = omap_findclk(s->mpu, "omap3_gp10_fclk");
2196
2197     if (s->cm_clksel_core & 0x40)
2198         omap_clk_reparent(gp10_fclk, omap_findclk(s->mpu, "omap3_sys_clk"));
2199     else
2200         omap_clk_reparent(gp10_fclk, omap_findclk(s->mpu, "omap3_32k_fclk"));
2201
2202     /*Tell GPTIMER10 to generate new clk rate */
2203     omap_gp_timer_change_clk(s->mpu->gptimer[9]);
2204     TRACE("omap3_gp10_fclk %lld",
2205           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp10_fclk")));
2206 }
2207
2208 static inline void omap3_cm_gp11_update(struct omap3_cm_s *s)
2209 {
2210     omap_clk gp11_fclk = omap_findclk(s->mpu, "omap3_gp11_fclk");
2211
2212     if (s->cm_clksel_core & 0x80)
2213         omap_clk_reparent(gp11_fclk, omap_findclk(s->mpu, "omap3_sys_clk"));
2214     else
2215         omap_clk_reparent(gp11_fclk, omap_findclk(s->mpu, "omap3_32k_fclk"));
2216     /*Tell GPTIMER11 to generate new clk rate */
2217     omap_gp_timer_change_clk(s->mpu->gptimer[10]);
2218     TRACE("omap3_gp11_fclk %lld",
2219           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp11_fclk")));
2220 }
2221
2222 static inline void omap3_cm_l3clk_update(struct omap3_cm_s *s)
2223 {
2224     omap_clk l3_iclk = omap_findclk(s->mpu, "omap3_l3_iclk");
2225     if ((s->cm_clksel_core & 0x3) == 0x1)
2226         omap_clk_setrate(l3_iclk, 1, 1);
2227     else if ((s->cm_clksel_core & 0x3) == 0x2)
2228         omap_clk_setrate(l3_iclk, 2, 1);
2229 }
2230
2231 static inline void omap3_cm_l4clk_update(struct omap3_cm_s *s)
2232 {
2233     omap_clk l4_iclk = omap_findclk(s->mpu, "omap3_l4_iclk");
2234     if ((s->cm_clksel_core & 0xc) == 0x4)
2235         omap_clk_setrate(l4_iclk, 1, 1);
2236     else if ((s->cm_clksel_core & 0xc) == 0x8)
2237         omap_clk_setrate(l4_iclk, 2, 1);
2238 }
2239
2240 static inline void omap3_cm_per_gptimer_update(struct omap3_cm_s *s)
2241 {
2242     uint32_t cm_clksel_per = s->cm_clksel_per;
2243
2244     if (cm_clksel_per & 0x1)
2245         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp2_fclk"),
2246                           omap_findclk(s->mpu, "omap3_sys_clk"));
2247     else
2248         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp2_fclk"),
2249                           omap_findclk(s->mpu, "omap3_32k_fclk"));
2250     omap_gp_timer_change_clk(s->mpu->gptimer[1]);
2251
2252     if (cm_clksel_per & 0x2)
2253         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp3_fclk"),
2254                           omap_findclk(s->mpu, "omap3_sys_clk"));
2255     else
2256         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp3_fclk"),
2257                           omap_findclk(s->mpu, "omap3_32k_fclk"));
2258     omap_gp_timer_change_clk(s->mpu->gptimer[2]);
2259
2260     if (cm_clksel_per & 0x4)
2261         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp4_fclk"),
2262                           omap_findclk(s->mpu, "omap3_sys_clk"));
2263     else
2264         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp4_fclk"),
2265                           omap_findclk(s->mpu, "omap3_32k_fclk"));
2266     omap_gp_timer_change_clk(s->mpu->gptimer[3]);
2267
2268     if (cm_clksel_per & 0x8)
2269         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp5_fclk"),
2270                           omap_findclk(s->mpu, "omap3_sys_clk"));
2271     else
2272         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp5_fclk"),
2273                           omap_findclk(s->mpu, "omap3_32k_fclk"));
2274     omap_gp_timer_change_clk(s->mpu->gptimer[4]);
2275
2276     if (cm_clksel_per & 0x10)
2277         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp6_fclk"),
2278                           omap_findclk(s->mpu, "omap3_sys_clk"));
2279     else
2280         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp6_fclk"),
2281                           omap_findclk(s->mpu, "omap3_32k_fclk"));
2282     omap_gp_timer_change_clk(s->mpu->gptimer[5]);
2283
2284     if (cm_clksel_per & 0x20)
2285         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp7_fclk"),
2286                           omap_findclk(s->mpu, "omap3_sys_clk"));
2287     else
2288         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp7_fclk"),
2289                           omap_findclk(s->mpu, "omap3_32k_fclk"));
2290     omap_gp_timer_change_clk(s->mpu->gptimer[6]);
2291
2292
2293     if (cm_clksel_per & 0x40)
2294         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp8_fclk"),
2295                           omap_findclk(s->mpu, "omap3_sys_clk"));
2296     else
2297         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp8_fclk"),
2298                           omap_findclk(s->mpu, "omap3_32k_fclk"));
2299     omap_gp_timer_change_clk(s->mpu->gptimer[7]);
2300
2301     if (cm_clksel_per & 0x80)
2302         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp9_fclk"),
2303                           omap_findclk(s->mpu, "omap3_sys_clk"));
2304     else
2305         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp9_fclk"),
2306                           omap_findclk(s->mpu, "omap3_32k_fclk"));
2307     omap_gp_timer_change_clk(s->mpu->gptimer[8]);
2308
2309     /*TODO:Tell GPTIMER to generate new clk rate */
2310     TRACE("omap3_gp2_fclk %lld",
2311           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp2_fclk")));
2312     TRACE("omap3_gp3_fclk %lld",
2313           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp3_fclk")));
2314         TRACE("omap3_gp4_fclk %lld",
2315           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp4_fclk")));
2316     TRACE("omap3_gp5_fclk %lld",
2317           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp5_fclk")));
2318     TRACE("omap3_gp6_fclk %lld",
2319           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp6_fclk")));
2320     TRACE("omap3_gp7_fclk %lld",
2321           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp7_fclk")));
2322     TRACE("omap3_gp8_fclk %lld",
2323           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp8_fclk")));
2324     TRACE("omap3_gp9_fclk %lld",
2325           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp9_fclk")));
2326 }
2327
2328 static inline void omap3_cm_clkout2_update(struct omap3_cm_s *s)
2329 {
2330         uint32 divor;
2331
2332         if (!s->cm_clkout_ctrl&0x80)
2333                 return;
2334
2335         switch (s->cm_clkout_ctrl&0x3)
2336         {
2337                 case 0x0:
2338                         omap_clk_reparent(omap_findclk(s->mpu, "omap3_sys_clkout2"),
2339                           omap_findclk(s->mpu, "omap3_core_clk"));
2340                         break;
2341                 case 0x1:
2342                         omap_clk_reparent(omap_findclk(s->mpu, "omap3_sys_clkout2"),
2343                           omap_findclk(s->mpu, "omap3_sys_clk"));
2344                         break;
2345                 case 0x2:
2346                         omap_clk_reparent(omap_findclk(s->mpu, "omap3_sys_clkout2"),
2347                           omap_findclk(s->mpu, "omap3_96m_fclk"));
2348                         break;
2349                 case 0x3:
2350                         omap_clk_reparent(omap_findclk(s->mpu, "omap3_sys_clkout2"),
2351                           omap_findclk(s->mpu, "omap3_54m_fclk"));
2352                         break;
2353         }
2354
2355         divor = (s->cm_clkout_ctrl&0x31)>>3;
2356         divor = 1<<divor;
2357         omap_clk_setrate(omap_findclk(s->mpu, "omap3_sys_clkout2"), divor, 1);
2358
2359 }
2360
2361 static void omap3_cm_reset(struct omap3_cm_s *s)
2362 {
2363     s->cm_fclken_iva2 = 0x0;
2364     s->cm_clken_pll_iva2 = 0x11;
2365     s->cm_idlest_iva2 = 0x1;
2366     s->cm_idlest_pll_iva2 = 0;
2367     s->cm_autoidle_pll_iva2 = 0x0;
2368     s->cm_clksel1_pll_iva2 = 0x80000;
2369     s->cm_clksel2_pll_iva2 = 0x1;
2370     s->cm_clkstctrl_iva2 = 0x0;
2371     s->cm_clkstst_iva2 = 0x0;
2372
2373     s->cm_revision = 0x10;
2374     s->cm_sysconfig = 0x1;
2375
2376     s->cm_clken_pll_mpu = 0x15;
2377     s->cm_idlest_mpu = 0x1;
2378     s->cm_idlest_pll_mpu = 0;
2379     s->cm_autoidle_pll_mpu = 0x0;
2380     s->cm_clksel1_pll_mpu = 0x80000;
2381     s->cm_clksel2_pll_mpu = 0x1;
2382     s->cm_clkstctrl_mpu = 0x0;
2383     s->cm_clkstst_mpu = 0x0;
2384
2385     s->cm_fclken1_core = 0x0;
2386     s->cm_fclken3_core = 0x0;
2387     s->cm_iclken1_core = 0x42;
2388     s->cm_iclken2_core = 0x0;
2389     s->cm_iclken3_core = 0x0;
2390     /*allow access to devices*/
2391     s->cm_idlest1_core = 0x0;
2392     s->cm_idlest2_core = 0x0;
2393     /*ide status =0 */
2394     s->cm_idlest3_core = 0xa;
2395     s->cm_autoidle1_core = 0x0;
2396     s->cm_autoidle2_core = 0x0;
2397     s->cm_autoidle3_core = 0x0;
2398     s->cm_clksel_core = 0x105;
2399     s->cm_clkstctrl_core = 0x0;
2400     s->cm_clkstst_core = 0x0;
2401
2402     s->cm_fclken_sgx = 0x0;
2403     s->cm_iclken_sgx = 0x0;
2404     s->cm_idlest_sgx = 0x1;
2405     s->cm_clksel_sgx = 0x0;
2406     s->cm_sleepdep_sgx = 0x0;
2407     s->cm_clkstctrl_sgx = 0x0;
2408     s->cm_clkstst_sgx = 0x0;
2409
2410     s->cm_fclken_wkup = 0x0;
2411     s->cm_iclken_wkup = 0x0;
2412     /*assume all clock can be accessed*/
2413     s->cm_idlest_wkup = 0x0;
2414     s->cm_autoidle_wkup = 0x0;
2415     s->cm_clksel_wkup = 0x12;
2416
2417     s->cm_clken_pll = 0x110015;
2418     s->cm_clken2_pll = 0x11;
2419     s->cm_idlest_ckgen = 0x3f3c; /* FIXME: provide real clock statuses */
2420     s->cm_idlest2_ckgen = 0xa; /* FIXME: provide real clock statuses */
2421     s->cm_autoidle_pll = 0x0;
2422     s->cm_autoidle2_pll = 0x0;
2423     s->cm_clksel1_pll = 0x8000040;
2424     s->cm_clksel2_pll = 0x0;
2425     s->cm_clksel3_pll = 0x1;
2426     s->cm_clksel4_pll = 0x0;
2427     s->cm_clksel5_pll = 0x1;
2428     s->cm_clkout_ctrl = 0x3;
2429
2430
2431     s->cm_fclken_dss = 0x0;
2432     s->cm_iclken_dss = 0x0;
2433     /*dss can be accessed*/
2434     s->cm_idlest_dss = 0x0;
2435     s->cm_autoidle_dss = 0x0;
2436     s->cm_clksel_dss = 0x1010;
2437     s->cm_sleepdep_dss = 0x0;
2438     s->cm_clkstctrl_dss = 0x0;
2439     s->cm_clkstst_dss = 0x0;
2440
2441     s->cm_fclken_cam = 0x0;
2442     s->cm_iclken_cam = 0x0;
2443     s->cm_idlest_cam = 0x1;
2444     s->cm_autoidle_cam = 0x0;
2445     s->cm_clksel_cam = 0x10;
2446     s->cm_sleepdep_cam = 0x0;
2447     s->cm_clkstctrl_cam = 0x0;
2448     s->cm_clkstst_cam = 0x0;
2449
2450     s->cm_fclken_per = 0x0;
2451     s->cm_iclken_per = 0x0;
2452     //s->cm_idlest_per = 0x3ffff;
2453     s->cm_idlest_per = 0x0; //enable GPIO access
2454     s->cm_autoidle_per = 0x0;
2455     s->cm_clksel_per = 0x0;
2456     s->cm_sleepdep_per = 0x0;
2457     s->cm_clkstctrl_per = 0x0;
2458     s->cm_clkstst_per = 0x0;
2459
2460     s->cm_clksel1_emu = 0x10100a50;
2461     s->cm_clkstctrl_emu = 0x2;
2462     s->cm_clkstst_emu = 0x0;
2463     s->cm_clksel2_emu = 0x0;
2464     s->cm_clksel3_emu = 0x0;
2465
2466     s->cm_polctrl = 0x0;
2467
2468     s->cm_idlest_neon = 0x1;
2469     s->cm_clkstctrl_neon = 0x0;
2470
2471     s->cm_fclken_usbhost = 0x0;
2472     s->cm_iclken_usbhost = 0x0;
2473     s->cm_idlest_usbhost = 0x3;
2474     s->cm_autoidle_usbhost = 0x0;
2475     s->cm_sleepdep_usbhost = 0x0;
2476     s->cm_clkstctrl_usbhost = 0x0;
2477     s->cm_clkstst_usbhost = 0x0;
2478 }
2479
2480 static uint32_t omap3_cm_read(void *opaque, target_phys_addr_t addr)
2481 {
2482     struct omap3_cm_s *s = (struct omap3_cm_s *) opaque;
2483
2484     switch (addr) {
2485         /* IVA2_CM */
2486         case 0x0000: return s->cm_fclken_iva2;
2487         case 0x0004: return s->cm_clken_pll_iva2;
2488         case 0x0020: return s->cm_idlest_iva2;
2489         case 0x0024: return s->cm_idlest_pll_iva2;
2490         case 0x0034: return s->cm_autoidle_pll_iva2;
2491         case 0x0040: return s->cm_clksel1_pll_iva2;
2492         case 0x0044: return s->cm_clksel2_pll_iva2;
2493         case 0x0048: return s->cm_clkstctrl_iva2;
2494         case 0x004c: return s->cm_clkstst_iva2;
2495         /* OCP_System_Reg_CM */
2496         case 0x0800: return s->cm_revision;
2497         case 0x0810: return s->cm_sysconfig;
2498         /* MPU_CM */
2499         case 0x0904: return s->cm_clken_pll_mpu;
2500         case 0x0920: return s->cm_idlest_mpu & 0x0; /*MPU is active*/
2501         case 0x0924: return s->cm_idlest_pll_mpu;
2502         case 0x0934: return s->cm_autoidle_pll_mpu;
2503         case 0x0940: return s->cm_clksel1_pll_mpu;
2504         case 0x0944: return s->cm_clksel2_pll_mpu;
2505         case 0x0948: return s->cm_clkstctrl_mpu;
2506         case 0x094c: return s->cm_clkstst_mpu;
2507         /* CORE_CM */
2508         case 0x0a00: return s->cm_fclken1_core;
2509         case 0x0a08: return s->cm_fclken3_core;
2510         case 0x0a10: return s->cm_iclken1_core;
2511         case 0x0a14: return s->cm_iclken2_core;
2512         case 0x0a20: return s->cm_idlest1_core;
2513         case 0x0a24: return s->cm_idlest2_core;
2514         case 0x0a28: return s->cm_idlest3_core;
2515         case 0x0a30: return s->cm_autoidle1_core;
2516         case 0x0a34: return s->cm_autoidle2_core;
2517         case 0x0a38: return s->cm_autoidle3_core;
2518         case 0x0a40: return s->cm_clksel_core;
2519         case 0x0a48: return s->cm_clkstctrl_core;
2520         case 0x0a4c: return s->cm_clkstst_core;
2521         /* SGX_CM */
2522         case 0x0b00: return s->cm_fclken_sgx;
2523         case 0x0b10: return s->cm_iclken_sgx;
2524         case 0x0b20: return s->cm_idlest_sgx & 0x0;
2525         case 0x0b40: return s->cm_clksel_sgx;
2526         case 0x0b48: return s->cm_clkstctrl_sgx;
2527         case 0x0b4c: return s->cm_clkstst_sgx;
2528         /* WKUP_CM */
2529         case 0x0c00: return s->cm_fclken_wkup;
2530         case 0x0c10: return s->cm_iclken_wkup;
2531         case 0x0c20: return 0; /* TODO: Check if the timer can be accessed. */
2532         case 0x0c30: return s->cm_idlest_wkup;
2533         case 0x0c40: return s->cm_clksel_wkup;
2534         case 0x0c48: return s->cm_c48;
2535         /* Clock_Control_Reg_CM */
2536         case 0x0d00: return s->cm_clken_pll;
2537         case 0x0d04: return s->cm_clken2_pll;
2538         case 0x0d20: return s->cm_idlest_ckgen;
2539         case 0x0d24: return s->cm_idlest2_ckgen;
2540         case 0x0d30: return s->cm_autoidle_pll;
2541         case 0x0d34: return s->cm_autoidle2_pll;
2542         case 0x0d40: return s->cm_clksel1_pll;
2543         case 0x0d44: return s->cm_clksel2_pll;
2544         case 0x0d48: return s->cm_clksel3_pll;
2545         case 0x0d4c: return s->cm_clksel4_pll;
2546         case 0x0d50: return s->cm_clksel5_pll;
2547         case 0x0d70: return s->cm_clkout_ctrl;
2548         /* DSS_CM */
2549         case 0x0e00: return s->cm_fclken_dss;
2550         case 0x0e10: return s->cm_iclken_dss;
2551         case 0x0e20: return s->cm_idlest_dss;
2552         case 0x0e30: return s->cm_autoidle_dss;
2553         case 0x0e40: return s->cm_clksel_dss;
2554         case 0x0e44: return s->cm_sleepdep_dss;
2555         case 0x0e48: return s->cm_clkstctrl_dss;
2556         case 0x0e4c: return s->cm_clkstst_dss;
2557         /* CAM_CM */
2558         case 0x0f00: return s->cm_fclken_cam;
2559         case 0x0f10: return s->cm_iclken_cam;
2560         case 0x0f20: return s->cm_idlest_cam & 0x0;
2561         case 0x0f30: return s->cm_autoidle_cam;
2562         case 0x0f40: return s->cm_clksel_cam;
2563         case 0x0f44: return s->cm_sleepdep_cam;
2564         case 0x0f48: return s->cm_clkstctrl_cam;
2565         case 0x0f4c: return s->cm_clkstst_cam;
2566         /* PER_CM */
2567         case 0x1000: return s->cm_fclken_per;
2568         case 0x1010: return s->cm_iclken_per;
2569         case 0x1020: return s->cm_idlest_per ;
2570         case 0x1030: return s->cm_autoidle_per;
2571         case 0x1040: return s->cm_clksel_per;
2572         case 0x1044: return s->cm_sleepdep_per;
2573         case 0x1048: return s->cm_clkstctrl_per;
2574         case 0x104c: return s->cm_clkstst_per;
2575         /* EMU_CM */
2576         case 0x1140: return s->cm_clksel1_emu;
2577         case 0x1148: return s->cm_clkstctrl_emu;
2578         case 0x114c: return s->cm_clkstst_emu & 0x0;
2579         case 0x1150: return s->cm_clksel2_emu;
2580         case 0x1154: return s->cm_clksel3_emu;
2581         /* Global_Reg_CM */
2582         case 0x129c: return s->cm_polctrl;
2583         /* NEON_CM */
2584         case 0x1320: return s->cm_idlest_neon & 0x0;
2585         case 0x1348: return s->cm_clkstctrl_neon;
2586         /* USBHOST_CM */
2587         case 0x1400: return s->cm_fclken_usbhost;
2588         case 0x1410: return s->cm_iclken_usbhost;
2589         case 0x1420: return s->cm_idlest_usbhost & 0x0;
2590         case 0x1430: return s->cm_autoidle_usbhost;
2591         case 0x1444: return s->cm_sleepdep_usbhost;
2592         case 0x1448: return s->cm_clkstctrl_usbhost;
2593         case 0x144c: return s->cm_clkstst_usbhost;
2594         /* unknown */
2595         default: break;
2596     }
2597     OMAP_BAD_REG(addr);
2598     return 0;
2599 }
2600
2601 static void omap3_cm_write(void *opaque,
2602                            target_phys_addr_t addr,
2603                            uint32_t value)
2604 {
2605     struct omap3_cm_s *s = (struct omap3_cm_s *)opaque;
2606
2607     switch (addr) {
2608         case 0x0020:
2609         case 0x0024:
2610         case 0x004c:
2611         case 0x0800:
2612         case 0x0920:
2613         case 0x0924:
2614         case 0x094c:
2615         case 0x0a20:
2616         case 0x0a24:
2617         case 0x0a28:
2618         case 0x0a4c:
2619         case 0x0b20:
2620         case 0x0b4c:
2621         case 0x0c20:
2622         case 0x0d20:
2623         case 0x0d24:
2624         case 0x0e20:
2625         case 0x0e4c:
2626         case 0x0f20:
2627         case 0x0f4c:
2628         case 0x1020:
2629         case 0x104c:
2630         case 0x114c:
2631         case 0x1320:
2632         case 0x1420:
2633         case 0x144c:
2634             OMAP_RO_REGV(addr, value);
2635             break;
2636         /* IVA2_CM */
2637         case 0x0000: s->cm_fclken_iva2 = value & 0x1; break;
2638         case 0x0004: s->cm_clken_pll_iva2 = value & 0x7ff; omap3_cm_iva2_update(s); break;
2639         case 0x0034: s->cm_autoidle_pll_iva2 = value & 0x7; break;
2640         case 0x0040: s->cm_clksel1_pll_iva2 = value & 0x3fff7f; omap3_cm_iva2_update(s); break;
2641         case 0x0044: s->cm_clksel2_pll_iva2 = value & 0x1f; omap3_cm_iva2_update(s); break;
2642         case 0x0048: s->cm_clkstctrl_iva2 = value & 0x3; break;
2643         /* OCP_System_Reg_CM */
2644         case 0x0810: s->cm_sysconfig = value & 0x1; break;
2645         /* MPU_CM */
2646         case 0x0904: s->cm_clken_pll_mpu = value & 0x7ff; omap3_cm_mpu_update(s); break;
2647         case 0x0934: s->cm_autoidle_pll_mpu = value & 0x7; break;
2648         case 0x0940: s->cm_clksel1_pll_mpu = value & 0x3fff7f; omap3_cm_mpu_update(s); break;
2649         case 0x0944: s->cm_clksel2_pll_mpu = value & 0x1f; omap3_cm_mpu_update(s); break;
2650         case 0x0948: s->cm_clkstctrl_mpu = value & 0x3; break;
2651         /* CORE_CM */
2652         case 0xa00: s->cm_fclken1_core = value & 0x43fffe00; break;
2653         case 0xa08: s->cm_fclken3_core = value & 0x7; break;
2654         case 0xa10:
2655             s->cm_iclken1_core = value & 0x637ffed2;
2656             s->cm_idlest1_core = ~s->cm_iclken1_core;
2657             /* TODO: replace code below with real implementation */
2658             s->cm_idlest1_core &= ~0x20; /* HS OTG USB idle */
2659             s->cm_idlest1_core |= 4; /* SDMA in standby */
2660             break;
2661         case 0xa14: s->cm_iclken2_core = value & 0x1f; break;
2662         case 0xa18:
2663             s->cm_iclken3_core = value & 0x4;
2664             s->cm_idlest3_core = 0xd & ~(s->cm_iclken3_core & 4);
2665             break;
2666         case 0xa30: s->cm_autoidle1_core = value & 0x7ffffed0; break;
2667         case 0xa34: s->cm_autoidle2_core = value & 0x1f; break;
2668         case 0xa38: s->cm_autoidle3_core = value & 0x2; break;
2669         case 0xa40:
2670             s->cm_clksel_core = (value & 0xff);
2671             s->cm_clksel_core |= 0x100;
2672             omap3_cm_gp10_update(s);
2673             omap3_cm_gp11_update(s);
2674             omap3_cm_l3clk_update(s);
2675             omap3_cm_l4clk_update(s);
2676             break;
2677         case 0xa48: s->cm_clkstctrl_core = value & 0xf; break;
2678         /* SGX_CM */
2679         case 0xb00: s->cm_fclken_sgx = value & 0x2; break;
2680         case 0xb10: s->cm_iclken_sgx = value & 0x1; break;
2681         case 0xb40: s->cm_clksel_sgx = value; break; /* TODO: SGX clock */
2682         case 0xb44: s->cm_sleepdep_sgx = value &0x2; break;
2683         case 0xb48: s->cm_clkstctrl_sgx = value & 0x3; break;
2684         /* WKUP_CM */
2685         case 0xc00: s->cm_fclken_wkup = value & 0x2e9; break;
2686         case 0xc10: s->cm_iclken_wkup = value & 0x2ff; break;
2687         case 0xc30: s->cm_autoidle_wkup = value & 0x23f; break;
2688         case 0xc40:
2689             s->cm_clksel_wkup = value & 0x7f;
2690             omap3_cm_clksel_wkup_update(s, s->cm_clksel_wkup);
2691             break;
2692         /* Clock_Control_Reg_CM */
2693         case 0xd00:
2694             s->cm_clken_pll = value & 0xffff17ff;
2695             omap3_cm_dpll3_update(s);
2696             omap3_cm_dpll4_update(s);
2697             break;
2698         case 0xd04:
2699             s->cm_clken2_pll = value & 0x7ff;
2700             omap3_cm_dpll5_update(s);
2701             break;
2702         case 0xd30: s->cm_autoidle_pll = value & 0x3f; break;
2703         case 0xd34: s->cm_autoidle2_pll = value & 0x7; break;
2704         case 0xd40:
2705             s->cm_clksel1_pll = value & 0xffffbffc;
2706             omap3_cm_dpll3_update(s);
2707             omap3_cm_48m_update(s);
2708             break;
2709         case 0xd44:
2710             s->cm_clksel2_pll = value & 0x7ff7f;
2711             omap3_cm_dpll4_update(s);
2712             break;
2713         case 0xd48:                /*CM_CLKSEL3_PLL */
2714             s->cm_clksel3_pll = value & 0x1f;
2715             omap3_cm_dpll4_update(s);
2716             break;
2717         case 0xd4c:                /*CM_CLKSEL4_PLL */
2718             s->cm_clksel4_pll = value & 0x7ff7f;
2719             omap3_cm_dpll5_update(s);
2720             break;
2721         case 0xd50:                /*CM_CLKSEL5_PLL */
2722             s->cm_clksel5_pll = value & 0x1f;
2723             omap3_cm_dpll5_update(s);
2724             break;
2725         case 0xd70:
2726             s->cm_clkout_ctrl = value & 0xbb;
2727             omap3_cm_clkout2_update(s);
2728             break;
2729         /* DSS_CM */
2730         case 0xe00: s->cm_fclken_dss = value & 0x7; break;
2731         case 0xe10: s->cm_iclken_dss = value & 0x1; break;
2732         case 0xe30: s->cm_autoidle_dss = value & 0x1; break;
2733         case 0xe40:
2734             s->cm_clksel_dss = value & 0x1f1f;
2735             omap3_cm_dpll4_update(s);
2736             break;
2737         case 0xe44: s->cm_sleepdep_dss = value & 0x7; break;
2738         case 0xe48: s->cm_clkstctrl_dss = value & 0x3; break;
2739         /* CAM_CM */
2740         case 0xf00: s->cm_fclken_cam = value & 0x3; break;
2741         case 0xf10: s->cm_iclken_cam = value & 0x1; break;
2742         case 0xf30: s->cm_autoidle_cam = value & 0x1; break;
2743         case 0xf40:
2744             s->cm_clksel_cam = value & 0x1f;
2745             omap3_cm_dpll4_update(s);
2746             break;
2747         case 0xf44: s->cm_sleepdep_cam = value & 0x2; break;
2748         case 0xf48: s->cm_clkstctrl_cam = value & 0x3; break;
2749         /* PER_CM */
2750         case 0x1000: s->cm_fclken_per = value & 0x3ffff; break;
2751         case 0x1010: s->cm_iclken_per = value & 0x3ffff; break;
2752         case 0x1030: s->cm_autoidle_per = value &0x3ffff; break;
2753         case 0x1040:
2754             s->cm_clksel_per = value & 0xff;
2755             omap3_cm_per_gptimer_update(s);
2756             break;
2757         case 0x1044: s->cm_sleepdep_per = value & 0x6; break;
2758         case 0x1048: s->cm_clkstctrl_per = value &0x7; break;
2759         /* EMU_CM */
2760         case 0x1140:
2761             s->cm_clksel1_emu = value & 0x1f1f3fff;
2762             omap3_cm_dpll3_update(s);
2763             omap3_cm_dpll4_update(s);
2764             break;
2765         case 0x1148: s->cm_clkstctrl_emu = value & 0x3; break;
2766         case 0x1150:
2767             s->cm_clksel2_emu = value & 0xfff7f;
2768             omap3_cm_dpll3_update(s);
2769             break;
2770         case 0x1154:
2771             s->cm_clksel3_emu = value & 0xfff7f;
2772             omap3_cm_dpll4_update(s);
2773             break;
2774         /* Global_Reg_CM */
2775         case 0x129c: s->cm_polctrl = value & 0x1; break;
2776         /* NEON_CM */
2777         case 0x1348: s->cm_clkstctrl_neon = value & 0x3; break;
2778         /* USBHOST_CM */
2779         case 0x1400: s->cm_fclken_usbhost = value & 0x3; break;
2780         case 0x1410: s->cm_iclken_usbhost = value & 0x1; break;
2781         case 0x1430: s->cm_autoidle_usbhost = value & 0x1; break;
2782         case 0x1444: s->cm_sleepdep_usbhost = value & 0x6; break;
2783         case 0x1448: s->cm_clkstctrl_usbhost = value & 0x3; break;
2784         /* unknown */
2785         default: OMAP_BAD_REGV(addr, value); break;
2786     }
2787 }
2788
2789
2790
2791 static CPUReadMemoryFunc *omap3_cm_readfn[] = {
2792     omap_badwidth_read32,
2793     omap_badwidth_read32,
2794     omap3_cm_read,
2795 };
2796
2797 static CPUWriteMemoryFunc *omap3_cm_writefn[] = {
2798     omap_badwidth_write32,
2799     omap_badwidth_write32,
2800     omap3_cm_write,
2801 };
2802
2803 struct omap3_cm_s *omap3_cm_init(struct omap_target_agent_s *ta,
2804                                  qemu_irq mpu_int, qemu_irq dsp_int,
2805                                  qemu_irq iva_int, struct omap_mpu_state_s *mpu)
2806 {
2807     int iomemtype;
2808     struct omap3_cm_s *s = (struct omap3_cm_s *) qemu_mallocz(sizeof(*s));
2809
2810     s->irq[0] = mpu_int;
2811     s->irq[1] = dsp_int;
2812     s->irq[2] = iva_int;
2813     s->mpu = mpu;
2814     omap3_cm_reset(s);
2815
2816     iomemtype = l4_register_io_memory(0, omap3_cm_readfn, omap3_cm_writefn, s);
2817     omap_l4_attach(ta, 0, iomemtype);
2818     omap_l4_attach(ta, 1, iomemtype);
2819
2820     return s;
2821 }
2822
2823 #define OMAP3_SEC_WDT          1
2824 #define OMAP3_MPU_WDT         2
2825 #define OMAP3_IVA2_WDT        3
2826 /*omap3 watchdog timer*/
2827 struct omap3_wdt_s
2828 {
2829     qemu_irq irq;               /*IVA2 IRQ */
2830     struct omap_mpu_state_s *mpu;
2831     omap_clk clk;
2832     QEMUTimer *timer;
2833
2834     int active;
2835     int64_t rate;
2836     int64_t time;
2837     //int64_t ticks_per_sec;
2838
2839     uint32_t wd_sysconfig;
2840     uint32_t wd_sysstatus;
2841     uint32_t wisr;
2842     uint32_t wier;
2843     uint32_t wclr;
2844     uint32_t wcrr;
2845     uint32_t wldr;
2846     uint32_t wtgr;
2847     uint32_t wwps;
2848     uint32_t wspr;
2849
2850     /*pre and ptv in wclr */
2851     uint32_t pre;
2852     uint32_t ptv;
2853     //uint32_t val;
2854
2855     uint16_t writeh;            /* LSB */
2856     uint16_t readh;             /* MSB */
2857 };
2858
2859 static inline void omap3_wdt_timer_update(struct omap3_wdt_s *wdt_timer)
2860 {
2861     int64_t expires;
2862     if (wdt_timer->active) {
2863         expires = muldiv64(0xffffffffll - wdt_timer->wcrr,
2864                            ticks_per_sec, wdt_timer->rate);
2865         qemu_mod_timer(wdt_timer->timer, wdt_timer->time + expires);
2866     } else
2867         qemu_del_timer(wdt_timer->timer);
2868 }
2869
2870 static void omap3_wdt_clk_setup(struct omap3_wdt_s *timer)
2871 {
2872     /*TODO: Add irq as user to clk */
2873 }
2874
2875 static inline uint32_t omap3_wdt_timer_read(struct omap3_wdt_s *timer)
2876 {
2877     uint64_t distance;
2878
2879     if (timer->active) {
2880         distance = qemu_get_clock(vm_clock) - timer->time;
2881         distance = muldiv64(distance, timer->rate, ticks_per_sec);
2882
2883         if (distance >= 0xffffffff - timer->wcrr)
2884             return 0xffffffff;
2885         else
2886             return timer->wcrr + distance;
2887     } else
2888         return timer->wcrr;
2889 }
2890
2891 /*
2892 static inline void omap3_wdt_timer_sync(struct omap3_wdt_s *timer)
2893 {
2894     if (timer->active) {
2895         timer->val = omap3_wdt_timer_read(timer);
2896         timer->time = qemu_get_clock(vm_clock);
2897     }
2898 }*/
2899
2900 static void omap3_wdt_reset(struct omap3_wdt_s *s, int wdt_index)
2901 {
2902     s->wd_sysconfig = 0x0;
2903     s->wd_sysstatus = 0x0;
2904     s->wisr = 0x0;
2905     s->wier = 0x0;
2906     s->wclr = 0x20;
2907     s->wcrr = 0x0;
2908     switch (wdt_index) {
2909         case OMAP3_MPU_WDT:
2910         case OMAP3_IVA2_WDT:
2911             s->wldr = 0xfffb0000;
2912             break;
2913         case OMAP3_SEC_WDT:
2914             s->wldr = 0xffa60000;
2915             break;
2916         default:
2917             break;
2918     }
2919     s->wtgr = 0x0;
2920     s->wwps = 0x0;
2921     s->wspr = 0x0;
2922
2923     switch (wdt_index) {
2924         case OMAP3_SEC_WDT:
2925         case OMAP3_MPU_WDT:
2926             s->active = 1;
2927             break;
2928         case OMAP3_IVA2_WDT:
2929             s->active = 0;
2930             break;
2931         default:
2932             break;
2933     }
2934     s->pre = s->wclr & (1 << 5);
2935     s->ptv = (s->wclr & 0x1c) >> 2;
2936     s->rate = omap_clk_getrate(s->clk) >> (s->pre ? s->ptv : 0);
2937
2938     s->active = 1;
2939     s->time = qemu_get_clock(vm_clock);
2940     omap3_wdt_timer_update(s);
2941 }
2942
2943 static uint32_t omap3_wdt_read32(void *opaque, target_phys_addr_t addr,
2944                                  int wdt_index)
2945 {
2946     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
2947
2948     switch (addr) {
2949         case 0x10: return s->wd_sysconfig;
2950         case 0x14: return s->wd_sysstatus;
2951         case 0x18: return s->wisr & 0x1;
2952         case 0x1c: return s->wier & 0x1;
2953         case 0x24: return s->wclr & 0x3c;
2954         case 0x28: /* WCRR */
2955             s->wcrr = omap3_wdt_timer_read(s);
2956             s->time = qemu_get_clock(vm_clock);
2957             return s->wcrr;
2958         case 0x2c: return s->wldr;
2959         case 0x30: return s->wtgr;
2960         case 0x34: return s->wwps;
2961         case 0x48: return s->wspr;
2962         default: break;
2963     }
2964     OMAP_BAD_REG(addr);
2965     return 0;
2966 }
2967
2968 static uint32_t omap3_mpu_wdt_read16(void *opaque, target_phys_addr_t addr)
2969 {
2970     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
2971     uint32_t ret;
2972
2973     if (addr & 2)
2974         return s->readh;
2975
2976     ret = omap3_wdt_read32(opaque, addr, OMAP3_MPU_WDT);
2977     s->readh = ret >> 16;
2978     return ret & 0xffff;
2979 }
2980
2981 static uint32_t omap3_mpu_wdt_read32(void *opaque, target_phys_addr_t addr)
2982 {
2983     return omap3_wdt_read32(opaque, addr, OMAP3_MPU_WDT);
2984 }
2985
2986 static void omap3_wdt_write32(void *opaque, target_phys_addr_t addr,
2987                               uint32_t value, int wdt_index)
2988 {
2989     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
2990
2991     switch (addr) {
2992     case 0x14: /* WD_SYSSTATUS */
2993     case 0x34: /* WWPS */
2994         OMAP_RO_REGV(addr, value);
2995         break;
2996     case 0x10: /*WD_SYSCONFIG */
2997         s->wd_sysconfig = value & 0x33f;
2998         break;
2999     case 0x18: /* WISR */
3000          s->wisr = value & 0x1;
3001         break;
3002     case 0x1c: /* WIER */
3003         s->wier = value & 0x1;
3004         break;
3005     case 0x24: /* WCLR */
3006         s->wclr = value & 0x3c;
3007         break;
3008     case 0x28: /* WCRR */
3009         s->wcrr = value;
3010         s->time = qemu_get_clock(vm_clock);
3011         omap3_wdt_timer_update(s);
3012         break;
3013     case 0x2c: /* WLDR */
3014         s->wldr = value; /* It will take effect after next overflow */
3015         break;
3016     case 0x30: /* WTGR */
3017         if (value != s->wtgr) {
3018             s->wcrr = s->wldr;
3019             s->pre = s->wclr & (1 << 5);
3020             s->ptv = (s->wclr & 0x1c) >> 2;
3021             s->rate = omap_clk_getrate(s->clk) >> (s->pre ? s->ptv : 0);
3022             s->time = qemu_get_clock(vm_clock);
3023             omap3_wdt_timer_update(s);
3024         }
3025         s->wtgr = value;
3026         break;
3027     case 0x48: /* WSPR */
3028         if (((value & 0xffff) == 0x5555) && ((s->wspr & 0xffff) == 0xaaaa)) {
3029             s->active = 0;
3030             s->wcrr = omap3_wdt_timer_read(s);
3031             omap3_wdt_timer_update(s);
3032         }
3033         if (((value & 0xffff) == 0x4444) && ((s->wspr & 0xffff) == 0xbbbb)) {
3034             s->active = 1;
3035             s->time = qemu_get_clock(vm_clock);
3036             omap3_wdt_timer_update(s);
3037         }
3038         s->wspr = value;
3039         break;
3040     default:
3041         OMAP_BAD_REGV(addr, value);
3042         break;
3043     }
3044 }
3045
3046 static void omap3_mpu_wdt_write16(void *opaque, target_phys_addr_t addr,
3047                                   uint32_t value)
3048 {
3049     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
3050
3051     if (addr & 2)
3052         return omap3_wdt_write32(opaque, addr, (value << 16) | s->writeh,
3053                                  OMAP3_MPU_WDT);
3054     else
3055         s->writeh = (uint16_t) value;
3056 }
3057
3058 static void omap3_mpu_wdt_write32(void *opaque, target_phys_addr_t addr,
3059                                   uint32_t value)
3060 {
3061     omap3_wdt_write32(opaque, addr, value, OMAP3_MPU_WDT);
3062 }
3063
3064 static CPUReadMemoryFunc *omap3_mpu_wdt_readfn[] = {
3065     omap_badwidth_read32,
3066     omap3_mpu_wdt_read16,
3067     omap3_mpu_wdt_read32,
3068 };
3069
3070 static CPUWriteMemoryFunc *omap3_mpu_wdt_writefn[] = {
3071     omap_badwidth_write32,
3072     omap3_mpu_wdt_write16,
3073     omap3_mpu_wdt_write32,
3074 };
3075
3076 static void omap3_mpu_wdt_timer_tick(void *opaque)
3077 {
3078     struct omap3_wdt_s *wdt_timer = (struct omap3_wdt_s *) opaque;
3079
3080     /*TODO:Sent reset pulse to PRCM */
3081     wdt_timer->wcrr = wdt_timer->wldr;
3082
3083     /*after overflow, generate the new wdt_timer->rate */
3084     wdt_timer->pre = wdt_timer->wclr & (1 << 5);
3085     wdt_timer->ptv = (wdt_timer->wclr & 0x1c) >> 2;
3086     wdt_timer->rate =
3087         omap_clk_getrate(wdt_timer->clk) >> (wdt_timer->pre ? wdt_timer->
3088                                              ptv : 0);
3089
3090     wdt_timer->time = qemu_get_clock(vm_clock);
3091     omap3_wdt_timer_update(wdt_timer);
3092 }
3093
3094 static struct omap3_wdt_s *omap3_mpu_wdt_init(struct omap_target_agent_s *ta,
3095                                               qemu_irq irq, omap_clk fclk,
3096                                               omap_clk iclk,
3097                                               struct omap_mpu_state_s *mpu)
3098 {
3099     int iomemtype;
3100     struct omap3_wdt_s *s = (struct omap3_wdt_s *) qemu_mallocz(sizeof(*s));
3101
3102     s->irq = irq;
3103     s->clk = fclk;
3104     s->timer = qemu_new_timer(vm_clock, omap3_mpu_wdt_timer_tick, s);
3105
3106     omap3_wdt_reset(s, OMAP3_MPU_WDT);
3107     if (irq != NULL)
3108         omap3_wdt_clk_setup(s);
3109
3110     iomemtype = l4_register_io_memory(0, omap3_mpu_wdt_readfn,
3111                                       omap3_mpu_wdt_writefn, s);
3112     omap_l4_attach(ta, 0, iomemtype);
3113
3114     return s;
3115
3116 }
3117
3118 struct omap3_scm_s {
3119     struct omap_mpu_state_s *mpu;
3120
3121         uint8 interface[48];     /*0x4800 2000*/
3122         uint8 padconfs[576];     /*0x4800 2030*/
3123         uint32 general[228];     /*0x4800 2270*/
3124         uint8 mem_wkup[1024];    /*0x4800 2600*/
3125         uint8 padconfs_wkup[84]; /*0x4800 2a00*/
3126         uint32 general_wkup[8];  /*0x4800 2a60*/
3127 };
3128
3129 #define PADCONFS_VALUE(wakeup0,wakeup1,offmode0,offmode1, \
3130                                                 inputenable0,inputenable1,pupd0,pupd1,muxmode0,muxmode1,offset) \
3131         do { \
3132                  *(padconfs+offset/4) = (wakeup0 <<14)|(offmode0<<9)|(inputenable0<<8)|(pupd0<<3)|(muxmode0); \
3133                  *(padconfs+offset/4) |= (wakeup1 <<30)|(offmode1<<25)|(inputenable1<<24)|(pupd1<<19)|(muxmode1<<16); \
3134 } while (0)
3135
3136
3137 static void omap3_scm_reset(struct omap3_scm_s *s)
3138 {
3139     uint32 * padconfs;
3140     padconfs = (uint32 *)(s->padconfs);
3141     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x0);
3142     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x4);
3143     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x8);
3144     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0xc);
3145     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x10);
3146     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x14);
3147     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x18);
3148     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x1c);
3149     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x20);
3150     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x24);
3151     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x28);
3152     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x2c);
3153     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x30);
3154     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x34);
3155     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x38);
3156     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x3c);
3157     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x40);
3158     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x44);
3159     PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,7,0x48);
3160     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x4c);
3161     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x50);
3162     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x54);
3163     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x58);
3164     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,0,0x5c);
3165     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x60);
3166     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x64);
3167     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x68);
3168     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x6c);
3169     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x70);
3170     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x74);
3171     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x78);
3172     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x7c);
3173     PADCONFS_VALUE(0,0,0,0,1,1,0,3,0,7,0x80);
3174     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x84);
3175     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x88);
3176     PADCONFS_VALUE(0,0,0,0,1,1,3,0,7,0,0x8c);
3177     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x90);
3178     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x94);
3179     PADCONFS_VALUE(0,0,0,0,1,1,1,0,7,0,0x98);
3180     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,7,0x9c);
3181     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0xa0);
3182     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0xa4);
3183     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0xa8);
3184     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xac);
3185     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb0);
3186     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb4);
3187     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb8);
3188     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xbc);
3189     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc0);
3190     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc4);
3191     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc8);
3192     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xcc);
3193     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd0);
3194     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd4);
3195     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd8);
3196     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xdc);
3197     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe0);
3198     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe4);
3199     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe8);
3200     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xec);
3201     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf0);
3202     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf4);
3203     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf8);
3204     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xfc);
3205     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x100);
3206     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x104);
3207     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x108);
3208     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x10c);
3209     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x110);
3210     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x114);
3211     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x118);
3212     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x11c);
3213     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x120);
3214     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x124);
3215     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x128);
3216     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x12c);
3217     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x130);
3218     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x134);
3219     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x138);
3220     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x13c);
3221     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x140);
3222     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x144);
3223     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x148);
3224     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x14c);
3225     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x150);
3226     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x154);
3227     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x158);
3228     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x15c);
3229     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x160);
3230     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x164);
3231     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x168);
3232     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x16c);
3233     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x170);
3234     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x174);
3235     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x178);
3236     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x17c);
3237     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x180);
3238     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x184);
3239     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x188);
3240     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x18c);
3241     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x190);
3242     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x194);
3243     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x198);
3244     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x19c);
3245     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x1a0);
3246     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1a4);
3247     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x1a8);
3248     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1ac);
3249     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1b0);
3250     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1b4);
3251     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1b8);
3252     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1bc);
3253     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c0);
3254     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c4);
3255     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c8);
3256     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1cc);
3257     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d0);
3258     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d4);
3259     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d8);
3260     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1dc);
3261     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e0);
3262     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e4);
3263     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e8);
3264     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1ec);
3265     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f0);
3266     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f4);
3267     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f8);
3268     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1fc);
3269     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x200);
3270     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x204);
3271     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x208);
3272     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x20c);
3273     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x210);
3274     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x214);
3275     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x218);
3276     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x21c);
3277     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x220);
3278     PADCONFS_VALUE(0,0,0,0,1,1,3,1,0,0,0x224);
3279     PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,0,0x228);
3280     PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,0,0x22c);
3281     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x230);
3282     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x234);
3283
3284         padconfs = (uint32 *)(s->general);
3285     memset(s->general, 0, sizeof(s->general));
3286         s->general[0x01] = 0x4000000;  /* CONTROL_DEVCONF_0 */
3287         s->general[0x1c] = 0x1;        /* 0x480022e0?? */
3288     s->general[0x20] = 0x30f;      /* CONTROL_STATUS:
3289                                     * - device type  = GP Device
3290                                     * - sys_boot:6   = oscillator bypass mode
3291                                     * - sys_boot:0-5 = NAND, USB, UART3, MMC1*/
3292         s->general[0x75] = 0x7fc0;     /* CONTROL_PROG_IO0 */
3293         s->general[0x76] = 0xaa;       /* CONTROL_PROG_IO1 */
3294         s->general[0x7c] = 0x2700;     /* CONTROL_SDRC_SHARING */
3295         s->general[0x7d] = 0x300000;   /* CONTROL_SDRC_MCFG0 */
3296         s->general[0x7e] = 0x300000;   /* CONTROL_SDRC_MCFG1 */
3297         s->general[0x81] = 0xffff;     /* CONTROL_MODEM_GPMC_DT_FW_REQ_INFO */
3298         s->general[0x82] = 0xffff;     /* CONTROL_MODEM_GPMC_DT_FW_RD */
3299         s->general[0x83] = 0xffff;     /* CONTROL_MODEM_GPMC_DT_FW_WR */
3300         s->general[0x84] = 0x6;        /* CONTROL_MODEM_GPMC_BOOT_CODE */
3301         s->general[0x85] = 0xffffffff; /* CONTROL_MODEM_SMS_RG_ATT1 */
3302         s->general[0x86] = 0xffff;     /* CONTROL_MODEM_SMS_RG_RDPERM1 */
3303         s->general[0x87] = 0xffff;     /* CONTROL_MODEM_SMS_RG_WRPERM1 */
3304         s->general[0x88] = 0x1;        /* CONTROL_MODEM_D2D_FW_DEBUG_MODE */
3305         s->general[0x8b] = 0xffffffff; /* CONTROL_DPF_OCM_RAM_FW_REQINFO */
3306         s->general[0x8c] = 0xffff;     /* CONTROL_DPF_OCM_RAM_FW_WR */
3307         s->general[0x8e] = 0xffff;     /* CONTROL_DPF_REGION4_GPMC_FW_REQINFO */
3308         s->general[0x8f] = 0xffff;     /* CONTROL_DPF_REGION4_GPMC_FW_WR */
3309         s->general[0x91] = 0xffff;     /* CONTROL_DPF_REGION1_IVA2_FW_REQINFO */
3310         s->general[0x92] = 0xffff;     /* CONTROL_DPF_REGION1_IVA2_FW_WR */
3311         s->general[0xac] = 0x109;      /* CONTROL_PBIAS_LITE */
3312         s->general[0xb2] = 0xffff;     /* CONTROL_DPF_MAD2D_FW_ADDR_MATCH */
3313         s->general[0xb3] = 0xffff;     /* CONTROL_DPF_MAD2D_FW_REQINFO */
3314         s->general[0xb4] = 0xffff;     /* CONTROL_DPF_MAD2D_FW_WR */
3315         PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x368); /* PADCONF_ETK_CLK */
3316     PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x36c); /* PADCONF_ETK_D0 */
3317     PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x370); /* PADCONF_ETK_D2 */
3318     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x374); /* PADCONF_ETK_D4 */
3319     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x378); /* PADCONF_ETK_D6 */
3320     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x37c); /* PADCONF_ETK_D8 */
3321     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x380); /* PADCONF_ETK_D10 */
3322     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x384); /* PADCONF_ETK_D12 */
3323     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x388); /* PADCONF_ETK_D14 */
3324
3325         padconfs = (uint32 *)(s->padconfs_wkup);
3326         PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x0);
3327         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x4);
3328         PADCONFS_VALUE(0,0,0,0,1,1,3,0,0,0,0x8);
3329         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0xc);
3330         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x10);
3331         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x14);
3332         PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x18);
3333         PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c);
3334         PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x20);
3335         PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x24);
3336         PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x2c);
3337
3338         s->general_wkup[0] = 0x66ff; /* 0x48002A60?? */
3339 }
3340
3341 static uint32_t omap3_scm_read8(void *opaque, target_phys_addr_t addr)
3342 {
3343     struct omap3_scm_s *s = (struct omap3_scm_s *) opaque;
3344     uint8_t* temp;
3345
3346     switch (addr) {
3347         case 0x000 ... 0x02f: return s->interface[addr];
3348         case 0x030 ... 0x26f: return s->padconfs[addr - 0x30];
3349         case 0x270 ... 0x5ff: temp = (uint8_t *)s->general; return temp[addr - 0x270];
3350         case 0x600 ... 0x9ff: return s->mem_wkup[addr - 0x600];
3351         case 0xa00 ... 0xa5f: return s->padconfs_wkup[addr - 0xa00];
3352         case 0xa60 ... 0xa7f: temp = (uint8_t *)s->general_wkup; return temp[addr - 0xa60];
3353         default: break;
3354     }
3355     OMAP_BAD_REG(addr);
3356     return 0;
3357 }
3358
3359 static uint32_t omap3_scm_read16(void *opaque, target_phys_addr_t addr)
3360 {
3361     uint32_t v;
3362     v = omap3_scm_read8(opaque, addr);
3363     v |= omap3_scm_read8(opaque, addr + 1) << 8;
3364     return v;
3365 }
3366
3367 static uint32_t omap3_scm_read32(void *opaque, target_phys_addr_t addr)
3368 {
3369     uint32_t v;
3370     v = omap3_scm_read8(opaque, addr);
3371     v |= omap3_scm_read8(opaque, addr + 1) << 8;
3372     v |= omap3_scm_read8(opaque, addr + 2) << 16;
3373     v |= omap3_scm_read8(opaque, addr + 3) << 24;
3374     return v;
3375 }
3376
3377 static void omap3_scm_write8(void *opaque, target_phys_addr_t addr,
3378                              uint32_t value)
3379 {
3380     struct omap3_scm_s *s = (struct omap3_scm_s *) opaque;
3381     uint8_t* temp;
3382
3383     switch (addr) {
3384         case 0x000 ... 0x02f: s->interface[addr] = value; break;
3385         case 0x030 ... 0x26f: s->padconfs[addr-0x30] = value; break;
3386         case 0x270 ... 0x5ff: temp = (uint8_t *)s->general; temp[addr-0x270] = value; break;
3387         case 0x600 ... 0x9ff: s->mem_wkup[addr-0x600] = value; break;
3388         case 0xa00 ... 0xa5f: s->padconfs_wkup[addr-0xa00] = value; break;
3389         case 0xa60 ... 0xa7f: temp = (uint8_t *)s->general_wkup; temp[addr-0xa60] = value; break;
3390         default: OMAP_BAD_REGV(addr, value); break;
3391     }
3392 }
3393
3394 static void omap3_scm_write16(void *opaque, target_phys_addr_t addr,
3395                               uint32_t value)
3396 {
3397     omap3_scm_write8(opaque, addr + 0, (value) & 0xff);
3398     omap3_scm_write8(opaque, addr + 1, (value >> 8) & 0xff);
3399 }
3400
3401 static void omap3_scm_write32(void *opaque, target_phys_addr_t addr,
3402                               uint32_t value)
3403 {
3404     omap3_scm_write8(opaque, addr + 0, (value) & 0xff);
3405     omap3_scm_write8(opaque, addr + 1, (value >> 8) & 0xff);
3406     omap3_scm_write8(opaque, addr + 2, (value >> 16) & 0xff);
3407     omap3_scm_write8(opaque, addr + 3, (value >> 24) & 0xff);
3408 }
3409
3410 static CPUReadMemoryFunc *omap3_scm_readfn[] = {
3411     omap3_scm_read8,
3412     omap3_scm_read16,
3413     omap3_scm_read32,
3414 };
3415
3416 static CPUWriteMemoryFunc *omap3_scm_writefn[] = {
3417     omap3_scm_write8,
3418     omap3_scm_write16,
3419     omap3_scm_write32,
3420 };
3421
3422 static struct omap3_scm_s *omap3_scm_init(struct omap_target_agent_s *ta,
3423                                           struct omap_mpu_state_s *mpu)
3424 {
3425     int iomemtype;
3426     struct omap3_scm_s *s = (struct omap3_scm_s *) qemu_mallocz(sizeof(*s));
3427
3428     s->mpu = mpu;
3429
3430     omap3_scm_reset(s);
3431
3432     iomemtype = l4_register_io_memory(0, omap3_scm_readfn,
3433                                       omap3_scm_writefn, s);
3434     omap_l4_attach(ta, 0, iomemtype);
3435
3436     return s;
3437 }
3438
3439 /*dummy SDRAM Memory Scheduler emulation*/
3440 struct omap3_sms_s
3441 {
3442     struct omap_mpu_state_s *mpu;
3443
3444     uint32 sms_sysconfig;
3445     uint32 sms_sysstatus;
3446     uint32 sms_rg_att[8];
3447     uint32 sms_rg_rdperm[8];
3448     uint32 sms_rg_wrperm[8];
3449     uint32 sms_rg_start[7];
3450     uint32 sms_rg_end[7];
3451     uint32 sms_security_control;
3452     uint32 sms_class_arbiter0;
3453     uint32 sms_class_arbiter1;
3454     uint32 sms_class_arbiter2;
3455     uint32 sms_interclass_arbiter;
3456     uint32 sms_class_rotation[3];
3457     uint32 sms_err_addr;
3458     uint32 sms_err_type;
3459     uint32 sms_pow_ctrl;
3460     uint32 sms_rot_control[12];
3461     uint32 sms_rot_size[12];
3462     uint32 sms_rot_physical_ba[12];
3463 };
3464
3465 static uint32_t omap3_sms_read32(void *opaque, target_phys_addr_t addr)
3466 {
3467     struct omap3_sms_s *s = (struct omap3_sms_s *) opaque;
3468
3469     switch (addr)
3470     {
3471     case 0x10:
3472         return s->sms_sysconfig;
3473     case 0x14:
3474         return s->sms_sysstatus;
3475     case 0x48:
3476     case 0x68:
3477     case 0x88:
3478     case 0xa8:
3479     case 0xc8:
3480     case 0xe8:
3481     case 0x108:
3482     case 0x128:
3483         return s->sms_rg_att[(addr-0x48)/0x20];
3484     case 0x50:
3485     case 0x70:
3486     case 0x90:
3487     case 0xb0:
3488     case 0xd0:
3489     case 0xf0:
3490     case 0x110:
3491     case 0x130:
3492         return s->sms_rg_rdperm[(addr-0x50)/0x20];
3493     case 0x58:
3494     case 0x78:
3495     case 0x98:
3496     case 0xb8:
3497     case 0xd8:
3498     case 0xf8:
3499     case 0x118:
3500         return s->sms_rg_wrperm[(addr-0x58)/0x20];
3501     case 0x60:
3502     case 0x80:
3503     case 0xa0:
3504     case 0xc0:
3505     case 0xe0:
3506     case 0x100:
3507     case 0x120:
3508         return s->sms_rg_start[(addr-0x60)/0x20];
3509
3510     case 0x64:
3511     case 0x84:
3512     case 0xa4:
3513     case 0xc4:
3514     case 0xe4:
3515     case 0x104:
3516     case 0x124:
3517         return s->sms_rg_end[(addr-0x64)/0x20];
3518     case 0x140:
3519         return s->sms_security_control;
3520     case 0x150:
3521         return s->sms_class_arbiter0;
3522         case 0x154:
3523                 return s->sms_class_arbiter1;
3524         case 0x158:
3525                 return s->sms_class_arbiter2;
3526         case 0x160:
3527                 return s->sms_interclass_arbiter;
3528         case 0x164:
3529         case 0x168:
3530         case 0x16c:
3531                 return s->sms_class_rotation[(addr-0x164)/4];
3532         case 0x170:
3533                 return s->sms_err_addr;
3534         case 0x174:
3535                 return s->sms_err_type;
3536         case 0x178:
3537                 return s->sms_pow_ctrl;
3538         case 0x180:
3539         case 0x190:
3540         case 0x1a0:
3541         case 0x1b0:
3542         case 0x1c0:
3543         case 0x1d0:
3544         case 0x1e0:
3545         case 0x1f0:
3546         case 0x200:
3547         case 0x210:
3548         case 0x220:
3549         case 0x230:
3550                 return s->sms_rot_control[(addr-0x180)/0x10];
3551         case 0x184:
3552         case 0x194:
3553         case 0x1a4:
3554         case 0x1b4:
3555         case 0x1c4:
3556         case 0x1d4:
3557         case 0x1e4:
3558         case 0x1f4:
3559         case 0x204:
3560         case 0x214:
3561         case 0x224:
3562         case 0x234:
3563                 return s->sms_rot_size[(addr-0x184)/0x10];
3564
3565         case 0x188:
3566         case 0x198:
3567         case 0x1a8:
3568         case 0x1b8:
3569         case 0x1c8:
3570         case 0x1d8:
3571         case 0x1e8:
3572         case 0x1f8:
3573         case 0x208:
3574         case 0x218:
3575         case 0x228:
3576         case 0x238:
3577                 return s->sms_rot_size[(addr-0x188)/0x10];
3578
3579     default:
3580         break;
3581     }
3582     OMAP_BAD_REG(addr);
3583     return 0;
3584 }
3585
3586 static void omap3_sms_write32(void *opaque, target_phys_addr_t addr,
3587                               uint32_t value)
3588 {
3589     struct omap3_sms_s *s = (struct omap3_sms_s *) opaque;
3590     //int i;
3591
3592     switch (addr)
3593     {
3594     case 0x14:
3595         OMAP_RO_REG(addr);
3596         return;
3597     case 0x10:
3598         s->sms_sysconfig = value & 0x1f;
3599         break;
3600
3601     case 0x48:
3602     case 0x68:
3603     case 0x88:
3604     case 0xa8:
3605     case 0xc8:
3606     case 0xe8:
3607     case 0x108:
3608     case 0x128:
3609         s->sms_rg_att[(addr-0x48)/0x20] = value;
3610         break;
3611     case 0x50:
3612     case 0x70:
3613     case 0x90:
3614     case 0xb0:
3615     case 0xd0:
3616     case 0xf0:
3617     case 0x110:
3618     case 0x130:
3619         s->sms_rg_rdperm[(addr-0x50)/0x20] = value&0xffff;
3620         break;
3621     case 0x58:
3622     case 0x78:
3623     case 0x98:
3624     case 0xb8:
3625     case 0xd8:
3626     case 0xf8:
3627     case 0x118:
3628         s->sms_rg_wrperm[(addr-0x58)/0x20] = value&0xffff;
3629         break;
3630     case 0x60:
3631     case 0x80:
3632     case 0xa0:
3633     case 0xc0:
3634     case 0xe0:
3635     case 0x100:
3636     case 0x120:
3637         s->sms_rg_start[(addr-0x60)/0x20] = value;
3638         break;
3639     case 0x64:
3640     case 0x84:
3641     case 0xa4:
3642     case 0xc4:
3643     case 0xe4:
3644     case 0x104:
3645     case 0x124:
3646         s->sms_rg_end[(addr-0x64)/0x20] = value;
3647         break;
3648     case 0x140:
3649         s->sms_security_control = value &0xfffffff;
3650         break;
3651     case 0x150:
3652         s->sms_class_arbiter0 = value;
3653         break;
3654         case 0x154:
3655                 s->sms_class_arbiter1 = value;
3656                 break;
3657         case 0x158:
3658                 s->sms_class_arbiter2 = value;
3659                 break;
3660         case 0x160:
3661                 s->sms_interclass_arbiter = value;
3662                 break;
3663         case 0x164:
3664         case 0x168:
3665         case 0x16c:
3666                 s->sms_class_rotation[(addr-0x164)/4] = value;
3667                 break;
3668         case 0x170:
3669                 s->sms_err_addr = value;
3670                 break;
3671         case 0x174:
3672                 s->sms_err_type = value;
3673                 break;
3674         case 0x178:
3675                 s->sms_pow_ctrl = value;
3676                 break;
3677         case 0x180:
3678         case 0x190:
3679         case 0x1a0:
3680         case 0x1b0:
3681         case 0x1c0:
3682         case 0x1d0:
3683         case 0x1e0:
3684         case 0x1f0:
3685         case 0x200:
3686         case 0x210:
3687         case 0x220:
3688         case 0x230:
3689                 s->sms_rot_control[(addr-0x180)/0x10] = value;
3690                 break;
3691         case 0x184:
3692         case 0x194:
3693         case 0x1a4:
3694         case 0x1b4:
3695         case 0x1c4:
3696         case 0x1d4:
3697         case 0x1e4:
3698         case 0x1f4:
3699         case 0x204:
3700         case 0x214:
3701         case 0x224:
3702         case 0x234:
3703                 s->sms_rot_size[(addr-0x184)/0x10] = value;
3704                 break;
3705
3706         case 0x188:
3707         case 0x198:
3708         case 0x1a8:
3709         case 0x1b8:
3710         case 0x1c8:
3711         case 0x1d8:
3712         case 0x1e8:
3713         case 0x1f8:
3714         case 0x208:
3715         case 0x218:
3716         case 0x228:
3717         case 0x238:
3718                 s->sms_rot_size[(addr-0x188)/0x10] = value;
3719                 break;
3720         default:
3721         OMAP_BAD_REGV(addr, value);
3722         break;
3723     }
3724 }
3725
3726 static CPUReadMemoryFunc *omap3_sms_readfn[] = {
3727     omap_badwidth_read32,
3728     omap_badwidth_read32,
3729     omap3_sms_read32,
3730 };
3731
3732 static CPUWriteMemoryFunc *omap3_sms_writefn[] = {
3733     omap_badwidth_write32,
3734     omap_badwidth_write32,
3735     omap3_sms_write32,
3736 };
3737
3738 static void omap3_sms_reset(struct omap3_sms_s *s)
3739 {
3740         s->sms_sysconfig = 0x1;
3741         s->sms_class_arbiter0 = 0x500000;
3742         s->sms_class_arbiter1 = 0x500;
3743         s->sms_class_arbiter2 = 0x55000;
3744         s->sms_interclass_arbiter = 0x400040;
3745         s->sms_class_rotation[0] = 0x1;
3746         s->sms_class_rotation[1] = 0x1;
3747         s->sms_class_rotation[2] = 0x1;
3748         s->sms_pow_ctrl = 0x80;
3749 }
3750
3751 static struct omap3_sms_s *omap3_sms_init(struct omap_mpu_state_s *mpu)
3752 {
3753     int iomemtype;
3754     struct omap3_sms_s *s = (struct omap3_sms_s *) qemu_mallocz(sizeof(*s));
3755
3756     s->mpu = mpu;
3757
3758     omap3_sms_reset(s);
3759
3760     iomemtype = cpu_register_io_memory(0, omap3_sms_readfn,
3761                                        omap3_sms_writefn, s);
3762     cpu_register_physical_memory(0x6c000000, 0x10000, iomemtype);
3763
3764     return s;
3765 }
3766
3767 #define OMAP3_BOOT_ROM_SIZE 0x1c000 /* 80 + 32 kB */
3768
3769 static const struct dma_irq_map omap3_dma_irq_map[] = {
3770     {0, OMAP_INT_3XXX_SDMA_IRQ0},
3771     {0, OMAP_INT_3XXX_SDMA_IRQ1},
3772     {0, OMAP_INT_3XXX_SDMA_IRQ2},
3773     {0, OMAP_INT_3XXX_SDMA_IRQ3},
3774 };
3775
3776 static int omap3_validate_addr(struct omap_mpu_state_s *s,
3777                                target_phys_addr_t addr)
3778 {
3779     return 1;
3780 }
3781
3782 struct omap_mpu_state_s *omap3530_mpu_init(unsigned long sdram_size,
3783                                            const char *core)
3784 {
3785     struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
3786         qemu_mallocz(sizeof(struct omap_mpu_state_s));
3787     ram_addr_t sram_base, q2_base, bootrom_base;
3788     qemu_irq *cpu_irq;
3789     qemu_irq dma_irqs[4];
3790     int i;
3791
3792     s->mpu_model = omap3530;
3793     s->env = cpu_init("cortex-a8-r2");
3794     if (!s->env) {
3795         fprintf(stderr, "Unable to find CPU definition\n");
3796         exit(1);
3797     }
3798     s->sdram_size = sdram_size;
3799     s->sram_size = OMAP3XXX_SRAM_SIZE;
3800
3801     /* Clocks */
3802     omap_clk_init(s);
3803
3804     /* Memory-mapped stuff */
3805
3806     q2_base = qemu_ram_alloc(s->sdram_size);
3807     cpu_register_physical_memory(OMAP3_Q2_BASE, s->sdram_size,
3808                                  q2_base | IO_MEM_RAM);
3809     sram_base = qemu_ram_alloc(s->sram_size);
3810     cpu_register_physical_memory(OMAP3_SRAM_BASE, s->sram_size,
3811                                  sram_base | IO_MEM_RAM);
3812     bootrom_base = qemu_ram_alloc(OMAP3XXX_BOOTROM_SIZE);
3813     cpu_register_physical_memory(OMAP3_Q1_BASE, OMAP3_BOOT_ROM_SIZE,
3814                                  bootrom_base | IO_MEM_ROM);
3815     cpu_register_physical_memory(0, OMAP3_BOOT_ROM_SIZE,
3816                                  bootrom_base | IO_MEM_ROM);
3817
3818     s->l4 = omap_l4_init(OMAP3_L4_BASE,
3819                          sizeof(omap3_l4_agent_info)
3820                          / sizeof(struct omap3_l4_agent_info_s));
3821
3822     cpu_irq = arm_pic_init_cpu(s->env);
3823     s->ih[0] = omap2_inth_init(s, 0x48200000, 0x1000, 3, &s->irq[0],
3824                                cpu_irq[ARM_PIC_CPU_IRQ],
3825                                cpu_irq[ARM_PIC_CPU_FIQ],
3826                                omap_findclk(s, "omap3_mpu_intc_fclk"),
3827                                omap_findclk(s, "omap3_mpu_intc_iclk"));
3828
3829     for (i = 0; i < 4; i++)
3830         dma_irqs[i] =
3831             s->irq[omap3_dma_irq_map[i].ih][omap3_dma_irq_map[i].intr];
3832     s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
3833                             omap_findclk(s, "omap3_sdma_fclk"),
3834                             omap_findclk(s, "omap3_sdma_iclk"));
3835     s->port->addr_valid = omap3_validate_addr;
3836
3837     /* Register SDRAM and SRAM ports for fast DMA transfers.  */
3838     soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
3839     soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
3840
3841
3842     s->omap3_cm = omap3_cm_init(omap3_l4ta_init(s->l4, L4A_CM), NULL, NULL, NULL, s);
3843
3844     s->omap3_prm = omap3_prm_init(omap3_l4ta_init(s->l4, L4A_PRM),
3845                                   s->irq[0][OMAP_INT_3XXX_PRCM_MPU_IRQ],
3846                                   NULL, s);
3847
3848     s->omap3_mpu_wdt = omap3_mpu_wdt_init(omap3_l4ta_init(s->l4, L4A_WDTIMER2),
3849                                           NULL,
3850                                           omap_findclk(s, "omap3_wkup_32k_fclk"),
3851                                           omap_findclk(s, "omap3_wkup_l4_iclk"),
3852                                           s);
3853
3854     s->omap3_l3 = omap3_l3_init(OMAP3_L3_BASE,
3855                                 omap3_l3_region,
3856                                 sizeof(omap3_l3_region)
3857                                 / sizeof(struct omap_l3_region_s));
3858     s->omap3_scm = omap3_scm_init(omap3_l4ta_init(s->l4, L4A_SCM), s);
3859
3860     s->omap3_sms = omap3_sms_init(s);
3861
3862     s->gptimer[0] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER1),
3863                                        s->irq[0][OMAP_INT_3XXX_GPT1_IRQ],
3864                                        omap_findclk(s, "omap3_gp1_fclk"),
3865                                        omap_findclk(s, "omap3_wkup_l4_iclk"));
3866     s->gptimer[1] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER2),
3867                                        s->irq[0][OMAP_INT_3XXX_GPT2_IRQ],
3868                                        omap_findclk(s, "omap3_gp2_fclk"),
3869                                        omap_findclk(s, "omap3_per_l4_iclk"));
3870     s->gptimer[2] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER3),
3871                                        s->irq[0][OMAP_INT_3XXX_GPT3_IRQ],
3872                                        omap_findclk(s, "omap3_gp3_fclk"),
3873                                        omap_findclk(s, "omap3_per_l4_iclk"));
3874     s->gptimer[3] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER4),
3875                                        s->irq[0][OMAP_INT_3XXX_GPT4_IRQ],
3876                                        omap_findclk(s, "omap3_gp4_fclk"),
3877                                        omap_findclk(s, "omap3_per_l4_iclk"));
3878     s->gptimer[4] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER5),
3879                                        s->irq[0][OMAP_INT_3XXX_GPT5_IRQ],
3880                                        omap_findclk(s, "omap3_gp5_fclk"),
3881                                        omap_findclk(s, "omap3_per_l4_iclk"));
3882     s->gptimer[5] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER6),
3883                                        s->irq[0][OMAP_INT_3XXX_GPT6_IRQ],
3884                                        omap_findclk(s, "omap3_gp6_fclk"),
3885                                        omap_findclk(s, "omap3_per_l4_iclk"));
3886     s->gptimer[6] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER7),
3887                                        s->irq[0][OMAP_INT_3XXX_GPT7_IRQ],
3888                                        omap_findclk(s, "omap3_gp7_fclk"),
3889                                        omap_findclk(s, "omap3_per_l4_iclk"));
3890     s->gptimer[7] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER8),
3891                                        s->irq[0][OMAP_INT_3XXX_GPT8_IRQ],
3892                                        omap_findclk(s, "omap3_gp8_fclk"),
3893                                        omap_findclk(s, "omap3_per_l4_iclk"));
3894     s->gptimer[8] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER9),
3895                                        s->irq[0][OMAP_INT_3XXX_GPT9_IRQ],
3896                                        omap_findclk(s, "omap3_gp9_fclk"),
3897                                        omap_findclk(s, "omap3_per_l4_iclk"));
3898     s->gptimer[9] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER10),
3899                                        s->irq[0][OMAP_INT_3XXX_GPT10_IRQ],
3900                                        omap_findclk(s, "omap3_gp10_fclk"),
3901                                        omap_findclk(s, "omap3_core_l4_iclk"));
3902     s->gptimer[10] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER11),
3903                                        s->irq[0][OMAP_INT_3XXX_GPT11_IRQ],
3904                                        omap_findclk(s, "omap3_gp12_fclk"),
3905                                        omap_findclk(s, "omap3_core_l4_iclk"));
3906     s->gptimer[11] = omap_gp_timer_init(omap3_l4ta_init(s->l4, L4A_GPTIMER12),
3907                                         s->irq[0][OMAP_INT_3XXX_GPT12_IRQ],
3908                                         omap_findclk(s, "omap3_gp12_fclk"),
3909                                         omap_findclk(s, "omap3_wkup_l4_iclk"));
3910
3911
3912     omap_synctimer_init(omap3_l4ta_init(s->l4, L4A_32KTIMER), s,
3913                         omap_findclk(s, "omap3_sys_32k"), NULL);
3914
3915     s->sdrc = omap_sdrc_init(0x6d000000);
3916
3917     s->gpmc = omap_gpmc_init(s, 0x6e000000, s->irq[0][OMAP_INT_3XXX_GPMC_IRQ]);
3918
3919
3920     s->uart[0] = omap2_uart_init(omap3_l4ta_init(s->l4, L4A_UART1),
3921                                  s->irq[0][OMAP_INT_3XXX_UART1_IRQ],
3922                                  omap_findclk(s, "omap3_uart1_fclk"),
3923                                  omap_findclk(s, "omap3_uart1_iclk"),
3924                                  s->drq[OMAP3XXX_DMA_UART1_TX],
3925                                  s->drq[OMAP3XXX_DMA_UART1_RX], 0);
3926     s->uart[1] = omap2_uart_init(omap3_l4ta_init(s->l4, L4A_UART2),
3927                                  s->irq[0][OMAP_INT_3XXX_UART2_IRQ],
3928                                  omap_findclk(s, "omap3_uart2_fclk"),
3929                                  omap_findclk(s, "omap3_uart2_iclk"),
3930                                  s->drq[OMAP3XXX_DMA_UART2_TX],
3931                                  s->drq[OMAP3XXX_DMA_UART2_RX], 0);
3932     s->uart[2] = omap2_uart_init(omap3_l4ta_init(s->l4, L4A_UART3),
3933                                  s->irq[0][OMAP_INT_3XXX_UART3_IRQ],
3934                                  omap_findclk(s, "omap3_uart2_fclk"),
3935                                  omap_findclk(s, "omap3_uart3_iclk"),
3936                                  s->drq[OMAP3XXX_DMA_UART3_TX],
3937                                  s->drq[OMAP3XXX_DMA_UART3_RX], 0);
3938
3939     s->dss = omap_dss_init(s, omap3_l4ta_init(s->l4, L4A_DSS),
3940                     s->irq[0][OMAP_INT_3XXX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
3941                    NULL,NULL,NULL,NULL,NULL);
3942
3943     s->gpif = omap3_gpif_init();
3944     omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO1),
3945                     &s->irq[0][OMAP_INT_3XXX_GPIO1_MPU_IRQ],
3946                     NULL,NULL,0);
3947     omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO2),
3948                     &s->irq[0][OMAP_INT_3XXX_GPIO2_MPU_IRQ],
3949                     NULL,NULL,1);
3950     omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO3),
3951                     &s->irq[0][OMAP_INT_3XXX_GPIO3_MPU_IRQ],
3952                     NULL,NULL,2);
3953     omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO4),
3954                     &s->irq[0][OMAP_INT_3XXX_GPIO4_MPU_IRQ],
3955                     NULL,NULL,3);
3956     omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO5),
3957                     &s->irq[0][OMAP_INT_3XXX_GPIO5_MPU_IRQ],
3958                     NULL,NULL,4);
3959     omap3_gpio_init(s, s->gpif ,omap3_l4ta_init(s->l4, L4A_GPIO6),
3960                     &s->irq[0][OMAP_INT_3XXX_GPIO6_MPU_IRQ],
3961                     NULL,NULL,5);
3962
3963     omap_tap_init(omap3_l4ta_init(s->l4, L4A_TAP), s);
3964
3965     s->omap3_mmc[0] = omap3_mmc_init(omap3_l4ta_init(s->l4, L4A_MMC1),
3966                                      s->irq[0][OMAP_INT_3XXX_MMC1_IRQ],
3967                                      &s->drq[OMAP3XXX_DMA_MMC1_TX],
3968                                      omap_findclk(s, "omap3_mmc1_fclk"),
3969                                      omap_findclk(s, "omap3_mmc1_iclk"));
3970
3971     s->omap3_mmc[1] = omap3_mmc_init(omap3_l4ta_init(s->l4, L4A_MMC2),
3972                                      s->irq[0][OMAP_INT_3XXX_MMC2_IRQ],
3973                                      &s->drq[OMAP3XXX_DMA_MMC2_TX],
3974                                      omap_findclk(s, "omap3_mmc2_fclk"),
3975                                      omap_findclk(s, "omap3_mmc2_iclk"));
3976
3977     s->omap3_mmc[2] = omap3_mmc_init(omap3_l4ta_init(s->l4, L4A_MMC3),
3978                                      s->irq[0][OMAP_INT_3XXX_MMC3_IRQ],
3979                                      &s->drq[OMAP3XXX_DMA_MMC3_TX],
3980                                      omap_findclk(s, "omap3_mmc3_fclk"),
3981                                      omap_findclk(s, "omap3_mmc3_iclk"));
3982
3983     s->i2c[0] = omap3_i2c_init(omap3_l4ta_init(s->l4, L4A_I2C1),
3984                                s->irq[0][OMAP_INT_3XXX_I2C1_IRQ],
3985                                &s->drq[OMAP3XXX_DMA_I2C1_TX],
3986                                omap_findclk(s, "omap3_i2c1_fclk"),
3987                                omap_findclk(s, "omap3_i2c1_iclk"),
3988                                8);
3989     s->i2c[1] = omap3_i2c_init(omap3_l4ta_init(s->l4, L4A_I2C2),
3990                                s->irq[0][OMAP_INT_3XXX_I2C2_IRQ],
3991                                &s->drq[OMAP3XXX_DMA_I2C2_TX],
3992                                omap_findclk(s, "omap3_i2c2_fclk"),
3993                                omap_findclk(s, "omap3_i2c2_iclk"),
3994                                8);
3995     s->i2c[2] = omap3_i2c_init(omap3_l4ta_init(s->l4, L4A_I2C3),
3996                                s->irq[0][OMAP_INT_3XXX_I2C3_IRQ],
3997                                &s->drq[OMAP3XXX_DMA_I2C3_TX],
3998                                omap_findclk(s, "omap3_i2c3_fclk"),
3999                                omap_findclk(s, "omap3_i2c3_iclk"),
4000                                64);
4001
4002     s->omap3_usb = omap3_hsusb_init(omap3_l4ta_init(s->l4, L4A_USBHS_OTG),
4003                                     omap3_l4ta_init(s->l4, L4A_USBHS_HOST),
4004                                     omap3_l4ta_init(s->l4, L4A_USBHS_TLL),
4005                                     s->irq[0][OMAP_INT_3XXX_HSUSB_MC],
4006                                     s->irq[0][OMAP_INT_3XXX_HSUSB_DMA],
4007                                     s->irq[0][OMAP_INT_3XXX_OHCI_IRQ],
4008                                     s->irq[0][OMAP_INT_3XXX_EHCI_IRQ],
4009                                     s->irq[0][OMAP_INT_3XXX_TLL_IRQ]);
4010     return s;
4011 }