git.maemo.org Git - qemu/blob - hw/omap3.c

   1 /*\r
   2  * TI OMAP3 processors emulation.\r
   3  *\r
   4  * Copyright (C) 2008 yajin <yajin@vm-kernel.org>\r
   5  *\r
   6  * This program is free software; you can redistribute it and/or\r
   7  * modify it under the terms of the GNU General Public License as\r
   8  * published by the Free Software Foundation; either version 2 or\r
   9  * (at your option) version 3 of the License.\r
  10  *\r
  11  * This program is distributed in the hope that it will be useful,\r
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  14  * GNU General Public License for more details.\r
  15  *\r
  16  * You should have received a copy of the GNU General Public License\r
  17  * along with this program; if not, write to the Free Software\r
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\r
  19  * MA 02111-1307 USA\r
  20  */\r
  21 \r
  22 #include "hw.h"\r
  23 #include "arm-misc.h"\r
  24 #include "omap.h"\r
  25 #include "sysemu.h"\r
  26 #include "qemu-timer.h"\r
  27 #include "qemu-char.h"\r
  28 #include "flash.h"\r
  29 #include "soc_dma.h"\r
  30 #include "audio/audio.h"\r
  31 \r
  32 //#define _OMAP3_DEBUG_\r
  33 \r
  34 #ifdef _OMAP3_DEBUG_\r
  35 #define OMAP3_DEBUG(x)    do {  printf x ; } while(0)\r
  36 #else\r
  37 #define OMAP3_DEBUG(x) \r
  38 #endif\r
  39 \r
  40 static uint32_t omap3_l4ta_read(void *opaque, target_phys_addr_t addr)\r
  41 {\r
  42     struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;\r
  43 \r
  44     switch (addr)\r
  45     {\r
  46         //case 0x00:        /* COMPONENT */\r
  47         //    return s->component;\r
  48     case 0x20:                 /* AGENT_CONTROL */\r
  49         return s->control;\r
  50 \r
  51     case 0x24:                 /* AGENT_CONTROL_H */\r
  52         return s->control_h;\r
  53 \r
  54     case 0x28:                 /* AGENT_STATUS */\r
  55         return s->status;\r
  56     }\r
  57 \r
  58     OMAP_BAD_REG(addr);\r
  59     return 0;\r
  60 }\r
  61 \r
  62 static void omap3_l4ta_write(void *opaque, target_phys_addr_t addr,\r
  63                              uint32_t value)\r
  64 {\r
  65     struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;\r
  66 \r
  67     switch (addr)\r
  68     {\r
  69         //case 0x00:        /* COMPONENT */\r
  70         //  OMAP_RO_REG(addr);\r
  71         // break;\r
  72     case 0x20:                 /* AGENT_CONTROL */\r
  73         s->control = value & 0x00000700;\r
  74         break;\r
  75     case 0x24:                 /* AGENT_CONTROL_H */\r
  76         s->control_h = value & 0x100;\r
  77         break;\r
  78     case 0x28:                 /* AGENT_STATUS */\r
  79         if (value & 0x100)\r
  80             s->status &= ~0x100;        /* REQ_TIMEOUT */\r
  81         break;\r
  82     default:\r
  83         OMAP_BAD_REG(addr);\r
  84     }\r
  85 }\r
  86 \r
  87 static CPUReadMemoryFunc *omap3_l4ta_readfn[] = {\r
  88     omap_badwidth_read16,\r
  89     omap3_l4ta_read,\r
  90     omap_badwidth_read16,\r
  91 };\r
  92 \r
  93 static CPUWriteMemoryFunc *omap3_l4ta_writefn[] = {\r
  94     omap_badwidth_write32,\r
  95     omap_badwidth_write32,\r
  96     omap3_l4ta_write,\r
  97 };\r
  98 \r
  99 \r
 100 \r
 101 static struct omap_l4_region_s omap3_l4_region[] = {\r
 102     [1] = {0x40800, 0x800, 32}, /* Initiator agent */\r
 103     [2] = {0x41000, 0x1000, 32},        /* Link agent */\r
 104     [0] = {0x40000, 0x800, 32}, /* Address and protection */\r
 105 \r
 106     [3] = {0x002000, 0x1000, 32 | 16 | 8},      /* System Control module */\r
 107     [4] = {0x003000, 0x1000, 32 | 16 | 8},      /* L4TA1 */\r
 108 \r
 109     [5] = {0x004000, 0x2000, 32},       /*CM Region A */\r
 110     [6] = {0x006000, 0x0800, 32},       /*CM Region B */\r
 111     [7] = {0x007000, 0x1000, 32 | 16 | 8},      /*  L4TA2 */\r
 112 \r
 113     [8] = {0x050000, 0x0400, 32},       /*Display subsystem top */\r
 114     [9] = {0x050400, 0x0400, 32},       /*Display controller */\r
 115     [10] = {0x050800, 0x0400, 32},      /*RFBI*/\r
 116     [11] = {0x050c00, 0x0400, 32},       /*Video encoder */\r
 117     [12] = {0x051000, 0x1000, 32 | 16 | 8},     /*  L4TA3 */\r
 118 \r
 119     [13] = {0x056000, 0x1000, 32},      /*  SDMA */\r
 120     [14] = {0x057000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 121 \r
 122     [15] = {0x060000, 0x1000, 16 | 8},  /*  I2C3 */\r
 123     [16] = {0x061000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 124 \r
 125     [17] = {0x062000, 0x1000, 32},      /*  USBTLL */\r
 126     [18] = {0x063000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 127 \r
 128     [19] = {0x064000, 0x1000, 32},      /* HS USB HOST */\r
 129     [20] = {0x065000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 130 \r
 131     [21] = {0x06a000, 0x1000, 32 | 16 | 8},     /* UART1 */\r
 132     [22] = {0x06b000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 133 \r
 134     [23] = {0x06c000, 0x1000, 32 | 16 | 8},     /* UART2 */\r
 135     [24] = {0x06d000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 136 \r
 137     [25] = {0x070000, 0x1000, 16 | 8},  /*  I2C1 */\r
 138     [26] = {0x071000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 139 \r
 140     [27] = {0x072000, 0x1000, 16 | 8},  /*  I2C2 */\r
 141     [28] = {0x073000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 142 \r
 143     [29] = {0x074000, 0x1000, 32},      /*  mcbsp1 */\r
 144     [30] = {0x075000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 145 \r
 146     [31] = {0x086000, 0x1000, 32 | 16}, /*  GPTIMER10 */\r
 147     [32] = {0x087000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 148 \r
 149     [33] = {0x088000, 0x1000, 32 | 16}, /*  GPTIMER11 */\r
 150     [34] = {0x089000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 151 \r
 152     [35] = {0x094000, 0x1000, 32 | 16 | 8},     /*  MAILBOX */\r
 153     [36] = {0x095000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 154 \r
 155     [37] = {0x096000, 0x1000, 32},      /*  mcbsp5 */\r
 156     [38] = {0x097000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 157 \r
 158     [39] = {0x098000, 0x1000, 32 | 16 | 8},     /*  MCSPI1 */\r
 159     [40] = {0x099000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 160 \r
 161     [41] = {0x09a000, 0x1000, 32 | 16 | 8},     /*  MCSPI2 */\r
 162     [42] = {0x09b000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 163 \r
 164     [43] = {0x09c000, 0x1000, 32},      /*  MMC/SD/SDIO */\r
 165     [44] = {0x09d000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 166 \r
 167     [45] = {0x09e000, 0x1000, 32},      /*  MS-PRO */\r
 168     [46] = {0x09f000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 169 \r
 170     [47] = {0x09e000, 0x1000, 32},      /*  MS-PRO */\r
 171     [48] = {0x09f000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 172 \r
 173     [49] = {0x0ab000, 0x1000, 32},      /*  HS USB OTG */\r
 174     [50] = {0x0ac000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 175 \r
 176     [51] = {0x0ad000, 0x1000, 32},      /*  MMC/SD/SDIO3 */\r
 177     [52] = {0x0ae000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 178 \r
 179     [53] = {0x0b0000, 0x1000, 32 | 16}, /*  MG */\r
 180     [54] = {0x0b1000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 181 \r
 182     [55] = {0x0b2000, 0x1000, 32},      /*  HDQ/1-WIRE */\r
 183     [56] = {0x0b3000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 184 \r
 185     [57] = {0x0b4000, 0x1000, 32},      /*  MMC/SD/SDIO2 */\r
 186     [58] = {0x0b5000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 187 \r
 188     [59] = {0x0b6000, 0x1000, 32},      /*  icr mpu  */\r
 189     [60] = {0x0b7000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 190 \r
 191     [61] = {0x0b8000, 0x1000, 32 | 16 | 8},     /*  MCSPI3  */\r
 192     [62] = {0x0b9000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 193 \r
 194     [63] = {0x0ba000, 0x1000, 32 | 16 | 8},     /*  MCSPI4  */\r
 195     [64] = {0x0bb000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 196 \r
 197     [65] = {0x0bc000, 0x4000, 32 | 16 | 8},     /*  CAMERA ISP  */\r
 198     [66] = {0x0c0000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 199 \r
 200     [67] = {0x0c7000, 0x1000, 32 | 16}, /*  MODEM  */\r
 201     [68] = {0x0c8000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 202 \r
 203     [69] = {0x0c9000, 0x1000, 32 | 16 | 8},     /*  SR1  */\r
 204     [70] = {0x0ca000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 205 \r
 206     [71] = {0x0cb000, 0x1000, 32 | 16 | 8},     /*  SR2  */\r
 207     [72] = {0x0cc000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 208 \r
 209     [73] = {0x0cd000, 0x1000, 32},      /*  ICR MODEM  */\r
 210     [74] = {0x0ce000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 211 \r
 212     [75] = {0x30a000, 0x1000, 32 | 16 | 8},     /*  CONTRL MODULE ID  */\r
 213     [76] = {0x30b000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 214 \r
 215     \r
 216     [77] = {0x306000, 0x2000, 32},      /* PRM REGION A  */\r
 217     [78] = {0x308000, 0x800, 32},       /* PRM REGION B  */\r
 218     [79] = {0x309000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 219 \r
 220      /*L4 WAKEUP MEMORY SPACE */\r
 221     [80] = {0x304000, 0x1000, 32 | 16}, /* GPTIMER12  */\r
 222     [81] = {0x305000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 223     \r
 224     [82] = {0x30a000, 0x800, 32 | 16 | 8},        /*TAP.undocument*/\r
 225     [83] = {0x30a800, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 226 \r
 227 \r
 228     [84] = {0x310000, 0x1000, 32 | 16 | 8},     /* GPIO1  */\r
 229     [85] = {0x311000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 230 \r
 231     [86] = {0x314000, 0x1000, 32 | 16}, /* WDTIMER2  */\r
 232     [87] = {0x315000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 233 \r
 234     [88] = {0x318000, 0x1000, 32 | 16}, /* GPTIMER1  */\r
 235     [89] = {0x319000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 236 \r
 237     [90] = {0x320000, 0x1000, 32 | 16}, /* 32K Timer */\r
 238     [91] = {0x321000, 0x1000, 32 | 16 | 8},     /*  L4TA2 */\r
 239 \r
 240     [92] = {0x328000, 0x800, 32 | 16 | 8},      /* AP  */\r
 241     [93] = {0x328800, 0x800, 32 | 16 | 8},      /* IP  */\r
 242     [94] = {0x329000, 0x1000, 32 | 16 | 8},     /* LA  */\r
 243     [95] = {0x32a000, 0x800, 32 | 16 | 8},      /* LA  */\r
 244     [96] = {0x340000, 0x1000, 32 | 16 | 8},     /*  L4TA4 */\r
 245 \r
 246     /*L4 Peripheral MEMORY SPACE */\r
 247     [97] = {0x1000000, 0x800, 32 | 16 | 8},     /* AP  */\r
 248     [98] = {0x1000800, 0x800, 32 | 16 | 8},     /* IP  */\r
 249     [99] = {0x1001000, 0x1000, 32 | 16 | 8},    /* LA  */\r
 250 \r
 251     [100] = {0x1020000, 0x1000, 32 | 16 | 8},    /* UART3 */\r
 252     [101] = {0x1021000, 0x1000, 32 | 16 | 8},    /*  L4TA4 */\r
 253 \r
 254     [102] = {0x1022000, 0x1000, 32},     /* MCBSP 2 */\r
 255     [103] = {0x1023000, 0x1000, 32 | 16 | 8},    /*  L4TA4 */\r
 256     \r
 257     [104] = {0x1024000, 0x1000, 32},    /* MCBSP 3 */\r
 258     [105] = {0x1025000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 259 \r
 260     [106] = {0x1026000, 0x1000, 32},    /* MCBSP 4 */\r
 261     [107] = {0x1027000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 262 \r
 263     [108] = {0x1028000, 0x1000, 32},    /* MCBSP 2 (sidetone) */\r
 264     [109] = {0x1029000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 265 \r
 266     [110] = {0x102a000, 0x1000, 32},    /* MCBSP 3 (sidetone) */\r
 267     [111] = {0x102b000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 268 \r
 269     [112] = {0x1030000, 0x1000, 32 | 16},       /* WDTIMER3  */\r
 270     [113] = {0x1031000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 271 \r
 272     [114] = {0x1032000, 0x1000, 32 | 16},       /* GPTIMER2 */\r
 273     [115] = {0x1033000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 274 \r
 275     [116] = {0x1034000, 0x1000, 32 | 16},       /* GPTIMER3 */\r
 276     [117] = {0x1035000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 277 \r
 278     [118] = {0x1036000, 0x1000, 32 | 16},       /* GPTIMER4 */\r
 279     [119] = {0x1037000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 280 \r
 281     [120] = {0x1038000, 0x1000, 32 | 16},       /* GPTIMER5 */\r
 282     [121] = {0x1039000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 283 \r
 284     [122] = {0x103a000, 0x1000, 32 | 16},       /* GPTIMER6 */\r
 285     [123] = {0x103b000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 286 \r
 287     [124] = {0x103c000, 0x1000, 32 | 16},       /* GPTIMER7 */\r
 288     [125] = {0x103d000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 289 \r
 290     [126] = {0x103e000, 0x1000, 32 | 16},       /* GPTIMER8 */\r
 291     [127] = {0x103f000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 292 \r
 293     [128] = {0x1040000, 0x1000, 32 | 16},       /* GPTIMER9 */\r
 294     [129] = {0x1041000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 295 \r
 296     [130] = {0x1050000, 0x1000, 32 | 16 | 8},   /* GPIO2 */\r
 297     [131] = {0x1051000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 298 \r
 299     [132] = {0x1052000, 0x1000, 32 | 16 | 8},   /* GPIO3 */\r
 300     [133] = {0x1053000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 301 \r
 302     [134] = {0x1054000, 0x1000, 32 | 16 | 8},   /* GPIO4 */\r
 303     [135] = {0x1055000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 304 \r
 305     [136] = {0x1056000, 0x1000, 32 | 16 | 8},   /* GPIO5 */\r
 306     [137] = {0x1057000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 307 \r
 308     [138] = {0x1058000, 0x1000, 32 | 16 | 8},   /* GPIO6 */\r
 309     [139] = {0x1059000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 310 \r
 311     /*L4 Emulation MEMORY SPACE */\r
 312     [140] = {0xc006000, 0x800, 32 | 16 | 8},    /* AP  */\r
 313     [141] = {0xc006800, 0x800, 32 | 16 | 8},    /* IP  */\r
 314     [142] = {0xc007000, 0x1000, 32 | 16 | 8},   /* LA  */\r
 315     [143] = {0xc008000, 0x800, 32 | 16 | 8},    /* DAP  */\r
 316 \r
 317     [144] = {0xc010000, 0x8000, 32 | 16 | 8},   /* MPU Emulation */\r
 318     [145] = {0xc018000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 319 \r
 320     [146] = {0xc019000, 0x8000, 32},    /* TPIU */\r
 321     [147] = {0xc01a000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 322 \r
 323     [148] = {0xc01b000, 0x8000, 32},    /* ETB */\r
 324     [149] = {0xc01c000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 325 \r
 326     [150] = {0xc01d000, 0x8000, 32},    /* DAOCTL */\r
 327     [151] = {0xc01e000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 328 \r
 329     [152] = {0xc706000, 0x2000, 32},    /* PR Region A */\r
 330     [153] = {0xc706800, 0x800, 32},     /* PR Region B */\r
 331     [154] = {0xc709000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 332 \r
 333     [155] = {0xc710000, 0x1000, 32 | 16 | 8},   /* GPIO1 */\r
 334     [156] = {0xc711000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 335 \r
 336     [157] = {0xc714000, 0x1000, 32 | 16},       /* WDTIMER 2 */\r
 337     [158] = {0xc715000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 338 \r
 339     [159] = {0xc718000, 0x1000, 32 | 16 | 8},   /* GPTIMER 1 */\r
 340     [160] = {0xc719000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 341 \r
 342     [161] = {0xc720000, 0x1000, 32 | 16},       /* 32k timer */\r
 343     [162] = {0xc721000, 0x1000, 32 | 16 | 8},   /*  L4TA4 */\r
 344 \r
 345     [163] = {0xc728000, 0x800, 32 | 16 | 8},    /* AP  */\r
 346     [164] = {0xc728800, 0x800, 32 | 16 | 8},    /* IP  */\r
 347     [165] = {0xc729000, 0x1000, 32 | 16 | 8},   /* LA  */\r
 348     [166] = {0xc72a000, 0x800, 32 | 16 | 8},    /* DAP  */\r
 349 \r
 350 };\r
 351 static struct omap_l4_agent_info_s omap3_l4_agent_info[] = {\r
 352     {0, 0, 2, 1},                /* System Control module */\r
 353     {1, 5, 3, 2},                /* CM */\r
 354     {2, 77, 3, 2},               /* PRM */\r
 355     {3, 86, 2, 1},               /* WDTIMER 2 */\r
 356     {4, 3, 2, 1},                 /* SCM */\r
 357     {5, 88, 2, 1},               /* GP TIMER 1 */\r
 358     {6, 114, 2, 1},              /* GP TIMER 2 */\r
 359     {7, 116, 2, 1},              /* GP TIMER 3 */\r
 360     {8, 118, 2, 1},              /* GP TIMER 4 */\r
 361     {9, 120, 2, 1},              /* GP TIMER 5 */\r
 362     {10, 122, 2, 1},              /* GP TIMER 6 */\r
 363     {11, 124, 2, 1},              /* GP TIMER 7 */\r
 364     {12, 126, 2, 1},              /* GP TIMER 8 */\r
 365     {13, 128, 2, 1},              /* GP TIMER 9 */\r
 366     {14, 31, 2, 1},              /* GP TIMER 10 */\r
 367     {15, 33, 2, 1},              /* GP TIMER 11 */\r
 368     {16, 80, 2, 1},              /* GP TIMER 12 */\r
 369     {17, 90, 2, 1},                /* 32K Sync timer */\r
 370     {18, 21, 2, 1},                /* uart1 */\r
 371     {19, 23, 2, 1},                /* uart2 */\r
 372     {20, 100, 2, 1},              /* uart3 */\r
 373     {21, 8, 5, 4},                /* Display */\r
 374     {22, 84, 2, 1},               /* GPIO 1 */\r
 375     {23, 130, 2, 1},              /* GPIO 2 */\r
 376     {24, 132, 2, 1},              /* GPIO 3 */\r
 377     {25, 134, 2, 1},              /* GPIO 4 */\r
 378     {26, 136, 2, 1},              /* GPIO 5 */\r
 379     {27, 138, 2, 1},              /* GPIO 6 */\r
 380     {28,82, 2, 1},                 /* TAP */\r
 381     {29,43, 2, 1},                 /* MMC1 */\r
 382     {30,57, 2, 1},                 /* MMC2 */\r
 383     {31,51, 2, 1},                 /* MMC3 */\r
 384     {32,25, 2, 1},                 /* I2C1 */\r
 385     {33,27, 2, 1},                 /* I2C2 */\r
 386     {34,15, 2, 1},                 /* I2C3 */\r
 387     \r
 388     \r
 389 };\r
 390 \r
 391 static struct omap_target_agent_s *omap3_l4ta_get(struct omap_l4_s *bus, int cs)\r
 392 {\r
 393     int i, iomemtype;\r
 394     struct omap_target_agent_s *ta = 0;\r
 395     struct omap_l4_agent_info_s *info = 0;\r
 396 \r
 397     for (i = 0; i < bus->ta_num; i++)\r
 398         if (omap3_l4_agent_info[i].ta == cs)\r
 399         {\r
 400             ta = &bus->ta[i];\r
 401             info = &omap3_l4_agent_info[i];\r
 402             break;\r
 403         }\r
 404     if (!ta)\r
 405     {\r
 406         fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs);\r
 407         exit(-1);\r
 408     }\r
 409 \r
 410     ta->bus = bus;\r
 411     ta->start = &omap3_l4_region[info->region];\r
 412     ta->regions = info->regions;\r
 413 \r
 414     ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);\r
 415     ta->status = 0x00000000;\r
 416     ta->control = 0x00000200;   /* XXX 01000200 for L4TAO */\r
 417 \r
 418     iomemtype = l4_register_io_memory(0, omap3_l4ta_readfn,\r
 419                                       omap3_l4ta_writefn, ta);\r
 420     ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);\r
 421 \r
 422     return ta;\r
 423 }\r
 424 \r
 425 \r
 426 struct omap3_prm_s\r
 427 {\r
 428     qemu_irq irq[3];\r
 429     struct omap_mpu_state_s *mpu;\r
 430 \r
 431     /*IVA2_PRM Register */\r
 432     uint32_t rm_rstctrl_iva2;   /*0x4830 6050 */\r
 433     uint32_t rm_rstst_iva2;     /*0x4830 6058 */\r
 434     uint32_t pm_wkdep_iva2;     /*0x4830 60C8 */\r
 435     uint32_t pm_pwstctrl_iva2;  /*0x4830 60E0 */\r
 436     uint32_t pm_pwstst_iva2;    /*0x4830 60E4 */\r
 437     uint32_t pm_prepwstst_iva2; /*0x4830 60E8 */\r
 438     uint32_t pm_irqstatus_iva2; /*0x4830 60F8 */\r
 439     uint32_t pm_irqenable_iva2; /*0x4830 60FC */\r
 440 \r
 441     /*OCP_System_Reg_PRM Registerr */\r
 442     uint32_t prm_revision;      /*0x4830 6804 */\r
 443     uint32_t prm_sysconfig;     /*0x4830 6814 */\r
 444     uint32_t prm_irqstatus_mpu; /*0x4830 6818 */\r
 445     uint32_t prm_irqenable_mpu; /*0x4830 681c */\r
 446 \r
 447     /*MPU_PRM Register */\r
 448     uint32_t rm_rstst_mpu;      /*0x4830 6958 */\r
 449     uint32_t pm_wkdep_mpu;      /*0x4830 69c8 */\r
 450     uint32_t pm_evgenctrl_mpu;  /*0x4830 69d4 */\r
 451     uint32_t pm_evgenontim_mpu; /*0x4830 69d8 */\r
 452     uint32_t pm_evgenofftim_mpu;        /*0x4830 69dc */\r
 453     uint32_t pm_pwstctrl_mpu;   /*0x4830 69e0 */\r
 454     uint32_t pm_pwstst_mpu;     /*0x4830 69e4 */\r
 455     uint32_t pm_perpwstst_mpu;  /*0x4830 69e8 */\r
 456 \r
 457     /*CORE_PRM Register */\r
 458     uint32_t rm_rstst_core;     /*0x4830 6a58 */\r
 459     uint32_t pm_wken1_core;     /*0x4830 6aa0 */\r
 460     uint32_t pm_mpugrpsel1_core;        /*0x4830 6aa4 */\r
 461     uint32_t pm_iva2grpsel1_core;       /*0x4830 6aa8 */\r
 462     uint32_t pm_wkst1_core;     /*0x4830 6ab0 */\r
 463     uint32_t pm_wkst3_core;     /*0x4830 6ab8 */\r
 464     uint32_t pm_pwstctrl_core;  /*0x4830 6ae0 */\r
 465     uint32_t pm_pwstst_core;    /*0x4830 6ae4 */\r
 466     uint32_t pm_prepwstst_core; /*0x4830 6ae8 */\r
 467     uint32_t pm_wken3_core;     /*0x4830 6af0 */\r
 468     uint32_t pm_iva2grpsel3_core;       /*0x4830 6af4 */\r
 469     uint32_t pm_mpugrpsel3_core;        /*0x4830 6af8 */\r
 470 \r
 471     /*SGX_PRM Register */\r
 472     uint32_t rm_rstst_sgx;      /*0x4830 6b58 */\r
 473     uint32_t pm_wkdep_sgx;      /*0x4830 6bc8 */\r
 474     uint32_t pm_pwstctrl_sgx;   /*0x4830 6be0 */\r
 475     uint32_t pm_pwstst_sgx;     /*0x4830 6be4 */\r
 476     uint32_t pm_prepwstst_sgx;  /*0x4830 6be8 */\r
 477 \r
 478     /*WKUP_PRM Register */\r
 479     uint32_t pm_wken_wkup;      /*0x4830 6ca0 */\r
 480     uint32_t pm_mpugrpsel_wkup; /*0x4830 6ca4 */\r
 481     uint32_t pm_iva2grpsel_wkup;        /*0x4830 6ca8 */\r
 482     uint32_t pm_wkst_wkup;      /*0x4830 6cb0 */\r
 483 \r
 484     /*Clock_Control_Reg_PRM Register */\r
 485     uint32_t prm_clksel;        /*0x4830 6D40 */\r
 486     uint32_t prm_clkout_ctrl;   /*0x4830 6D70 */\r
 487 \r
 488     /*DSS_PRM Register */\r
 489     uint32_t rm_rstst_dss;      /*0x4830 6e58 */\r
 490     uint32_t pm_wken_dss;       /*0x4830 6ea0 */\r
 491     uint32_t pm_wkdep_dss;      /*0x4830 6ec8 */\r
 492     uint32_t pm_pwstctrl_dss;   /*0x4830 6ee0 */\r
 493     uint32_t pm_pwstst_dss;     /*0x4830 6ee4 */\r
 494     uint32_t pm_prepwstst_dss;  /*0x4830 6ee8 */\r
 495 \r
 496     /*CAM_PRM Register */\r
 497     uint32_t rm_rstst_cam;      /*0x4830 6f58 */\r
 498     uint32_t pm_wken_cam;       /*0x4830 6fc8 */\r
 499     uint32_t pm_pwstctrl_cam;   /*0x4830 6fe0 */\r
 500     uint32_t pm_pwstst_cam;     /*0x4830 6fe4 */\r
 501     uint32_t pm_prepwstst_cam;  /*0x4830 6fe8 */\r
 502 \r
 503     /*PER_PRM Register */\r
 504     uint32_t rm_rstst_per;      /*0x4830 7058 */\r
 505     uint32_t pm_wken_per;       /*0x4830 70a0 */\r
 506     uint32_t pm_mpugrpsel_per;  /*0x4830 70a4 */\r
 507     uint32_t pm_iva2grpsel_per; /*0x4830 70a8 */\r
 508     uint32_t pm_wkst_per;       /*0x4830 70b0 */\r
 509     uint32_t pm_wkdep_per;      /*0x4830 70c8 */\r
 510     uint32_t pm_pwstctrl_per;   /*0x4830 70e0 */\r
 511     uint32_t pm_pwstst_per;     /*0x4830 70e4 */\r
 512     uint32_t pm_perpwstst_per;  /*0x4830 70e8 */\r
 513 \r
 514     /*EMU_PRM Register */\r
 515     uint32_t rm_rstst_emu;      /*0x4830 7158 */\r
 516     uint32_t pm_pwstst_emu;     /*0x4830 71e4 */\r
 517 \r
 518     /*Global_Reg_PRM Register */\r
 519     uint32_t prm_vc_smps_sa;    /*0x4830 7220 */\r
 520     uint32_t prm_vc_smps_vol_ra;        /*0x4830 7224 */\r
 521     uint32_t prm_vc_smps_cmd_ra;        /*0x4830 7228 */\r
 522     uint32_t prm_vc_cmd_val_0;  /*0x4830 722c */\r
 523     uint32_t prm_vc_cmd_val_1;  /*0x4830 7230 */\r
 524     uint32_t prm_vc_hc_conf;    /*0x4830 7234 */\r
 525     uint32_t prm_vc_i2c_cfg;    /*0x4830 7238 */\r
 526     uint32_t prm_vc_bypass_val; /*0x4830 723c */\r
 527     uint32_t prm_rstctrl;       /*0x4830 7250 */\r
 528     uint32_t prm_rsttimer;      /*0x4830 7254 */\r
 529     uint32_t prm_rstst;         /*0x4830 7258 */\r
 530     uint32_t prm_voltctrl;      /*0x4830 7260 */\r
 531     uint32_t prm_sram_pcharge;  /*0x4830 7264 */\r
 532     uint32_t prm_clksrc_ctrl;   /*0x4830 7270 */\r
 533     uint32_t prm_obs;           /*0x4830 7280 */\r
 534     uint32_t prm_voltsetup1;    /*0x4830 7290 */\r
 535     uint32_t prm_voltoffset;    /*0x4830 7294 */\r
 536     uint32_t prm_clksetup;      /*0x4830 7298 */\r
 537     uint32_t prm_polctrl;       /*0x4830 729c */\r
 538     uint32_t prm_voltsetup2;    /*0x4830 72a0 */\r
 539 \r
 540     /*NEON_PRM Register */\r
 541     uint32_t rm_rstst_neon;     /*0x4830 7358 */\r
 542     uint32_t pm_wkdep_neon;     /*0x4830 73c8 */\r
 543     uint32_t pm_pwstctrl_neon;  /*0x4830 73e0 */\r
 544     uint32_t pm_pwstst_neon;    /*0x4830 73e4 */\r
 545     uint32_t pm_prepwstst_neon; /*0x4830 73e8 */\r
 546 \r
 547     /*USBHOST_PRM Register */\r
 548     uint32_t rm_rstst_usbhost;  /*0x4830 7458 */\r
 549     uint32_t rm_wken_usbhost;   /*0x4830 74a0 */\r
 550     uint32_t rm_mpugrpsel_usbhost;      /*0x4830 74a4 */\r
 551     uint32_t rm_iva2grpsel_usbhost;     /*0x4830 74a8 */\r
 552     uint32_t rm_wkst_usbhost;   /*0x4830 74b0 */\r
 553     uint32_t rm_wkdep_usbhost;  /*0x4830 74c8 */\r
 554     uint32_t rm_pwstctrl_usbhost;       /*0x4830 74e0 */\r
 555     uint32_t rm_pwstst_usbhost; /*0x4830 74e4 */\r
 556     uint32_t rm_prepwstst_usbhost;      /*0x4830 74e8 */\r
 557 \r
 558 };\r
 559 \r
 560 static void omap3_prm_reset(struct omap3_prm_s *s)\r
 561 {\r
 562     s->rm_rstctrl_iva2 = 0x7;\r
 563     s->rm_rstst_iva2 = 0x1;\r
 564     s->pm_wkdep_iva2 = 0xb3;\r
 565     s->pm_pwstctrl_iva2 = 0xff0f07;\r
 566     s->pm_pwstst_iva2 = 0xff7;\r
 567     s->pm_prepwstst_iva2 = 0x0;\r
 568     s->pm_irqstatus_iva2 = 0x0;\r
 569     s->pm_irqenable_iva2 = 0x0;\r
 570 \r
 571     s->prm_revision = 0x10;\r
 572     s->prm_sysconfig = 0x1;\r
 573     s->prm_irqstatus_mpu = 0x0;\r
 574     s->prm_irqenable_mpu = 0x0;\r
 575 \r
 576     s->rm_rstst_mpu = 0x1;\r
 577     s->pm_wkdep_mpu = 0xa5;\r
 578     s->pm_evgenctrl_mpu = 0x12;\r
 579     s->pm_evgenontim_mpu = 0x0;\r
 580     s->pm_evgenofftim_mpu = 0x0;\r
 581     s->pm_pwstctrl_mpu = 0x30107;\r
 582     s->pm_pwstst_mpu = 0xc7;\r
 583     s->pm_pwstst_mpu = 0x0;\r
 584 \r
 585     s->rm_rstst_core = 0x1;\r
 586     s->pm_wken1_core = 0xc33ffe18;\r
 587     s->pm_mpugrpsel1_core = 0xc33ffe18;\r
 588     s->pm_iva2grpsel1_core = 0xc33ffe18;\r
 589     s->pm_wkst1_core = 0x0;\r
 590     s->pm_wkst3_core = 0x0;\r
 591     s->pm_pwstctrl_core = 0xf0307;\r
 592     s->pm_pwstst_core = 0xf7;\r
 593     s->pm_prepwstst_core = 0x0;\r
 594     s->pm_wken3_core = 0x4;\r
 595     s->pm_iva2grpsel3_core = 0x4;\r
 596     s->pm_mpugrpsel3_core = 0x4;\r
 597 \r
 598     s->rm_rstst_sgx = 0x1;\r
 599     s->pm_wkdep_sgx = 0x16;\r
 600     s->pm_pwstctrl_sgx = 0x30107;\r
 601     s->pm_pwstst_sgx = 0x3;\r
 602     s->pm_prepwstst_sgx = 0x0;\r
 603 \r
 604     s->pm_wken_wkup = 0x3cb;\r
 605     s->pm_mpugrpsel_wkup = 0x3cb;\r
 606     s->pm_iva2grpsel_wkup = 0x0;\r
 607     s->pm_wkst_wkup = 0x0;\r
 608 \r
 609     s->prm_clksel = 0x4;\r
 610     s->prm_clkout_ctrl = 0x80;\r
 611 \r
 612     s->rm_rstst_dss = 0x1;\r
 613     s->pm_wken_dss = 0x1;\r
 614     s->pm_wkdep_dss = 0x16;\r
 615     s->pm_pwstctrl_dss = 0x30107;\r
 616     s->pm_pwstst_dss = 0x3;\r
 617     s->pm_prepwstst_dss = 0x0;\r
 618 \r
 619     s->rm_rstst_cam = 0x1;\r
 620     s->pm_wken_cam = 0x16;\r
 621     s->pm_pwstctrl_cam = 0x30107;\r
 622     s->pm_pwstst_cam = 0x3;\r
 623     s->pm_prepwstst_cam = 0x0;\r
 624 \r
 625     s->rm_rstst_per = 0x1;\r
 626     s->pm_wken_per = 0x3efff;\r
 627     s->pm_mpugrpsel_per = 0x3efff;\r
 628     s->pm_iva2grpsel_per = 0x3efff;\r
 629     s->pm_wkst_per = 0x0;\r
 630     s->pm_wkdep_per = 0x17;\r
 631     s->pm_pwstctrl_per = 0x30107;\r
 632     s->pm_pwstst_per = 0x7;\r
 633     s->pm_perpwstst_per = 0x0;\r
 634 \r
 635     s->rm_rstst_emu = 0x1;\r
 636     s->pm_pwstst_emu = 0x13;\r
 637 \r
 638     s->prm_vc_smps_sa = 0x0;\r
 639     s->prm_vc_smps_vol_ra = 0x0;\r
 640     s->prm_vc_smps_cmd_ra = 0x0;\r
 641     s->prm_vc_cmd_val_0 = 0x0;\r
 642     s->prm_vc_cmd_val_1 = 0x0;\r
 643     s->prm_vc_hc_conf = 0x0;\r
 644     s->prm_vc_i2c_cfg = 0x18;\r
 645     s->prm_vc_bypass_val = 0x0;\r
 646     s->prm_rstctrl = 0x0;\r
 647     s->prm_rsttimer = 0x1006;\r
 648     s->prm_rstst = 0x1;\r
 649     s->prm_voltctrl = 0x0;\r
 650     s->prm_sram_pcharge = 0x50;\r
 651     s->prm_clksrc_ctrl = 0x43;\r
 652     s->prm_obs = 0x0;\r
 653     s->prm_voltsetup1 = 0x0;\r
 654     s->prm_voltoffset = 0x0;\r
 655     s->prm_clksetup = 0x0;\r
 656     s->prm_polctrl = 0xa;\r
 657     s->prm_voltsetup2 = 0x0;\r
 658 \r
 659     s->rm_rstst_neon = 0x1;\r
 660     s->pm_wkdep_neon = 0x2;\r
 661     s->pm_pwstctrl_neon = 0x7;\r
 662     s->pm_pwstst_neon = 0x3;\r
 663     s->pm_prepwstst_neon = 0x0;\r
 664 \r
 665     s->rm_rstst_usbhost = 0x1;\r
 666     s->rm_wken_usbhost = 0x1;\r
 667     s->rm_mpugrpsel_usbhost = 0x1;\r
 668     s->rm_iva2grpsel_usbhost = 0x1;\r
 669     s->rm_wkst_usbhost = 0x0;\r
 670     s->rm_wkdep_usbhost = 0x17;\r
 671     s->rm_pwstctrl_usbhost = 0x30107;\r
 672     s->rm_pwstst_usbhost = 0x3;\r
 673     s->rm_prepwstst_usbhost = 0x0;\r
 674 \r
 675 }\r
 676 \r
 677 static uint32_t omap3_prm_read(void *opaque, target_phys_addr_t addr)\r
 678 {\r
 679     struct omap3_prm_s *s = (struct omap3_prm_s *) opaque;\r
 680 \r
 681     switch (addr)\r
 682     {\r
 683     case 0x50:\r
 684         return s->rm_rstctrl_iva2;\r
 685     case 0x58:\r
 686         return s->rm_rstst_iva2;\r
 687     case 0xc8:\r
 688         return s->pm_wkdep_iva2 ;\r
 689     case 0xe0:\r
 690         return s->pm_pwstctrl_iva2;\r
 691     case 0xe4:\r
 692         return s->pm_pwstst_iva2;\r
 693     case 0xe8:\r
 694         return s->pm_prepwstst_iva2;\r
 695     case 0xf8:\r
 696         return s->pm_irqstatus_iva2;\r
 697     case 0xfc:\r
 698         return s->pm_irqenable_iva2;\r
 699 \r
 700     case 0x804:\r
 701         return s->prm_revision;\r
 702     case 0x814:\r
 703         return s->prm_sysconfig;\r
 704     case 0x818:\r
 705         return s->prm_irqstatus_mpu;\r
 706     case 0x81c:\r
 707         return s->prm_irqenable_mpu;\r
 708 \r
 709     case 0x958:\r
 710         return s->rm_rstst_mpu;\r
 711     case 0x9c8:\r
 712         return s->pm_wkdep_mpu;\r
 713     case 0x9d4:\r
 714         return s->pm_evgenctrl_mpu;\r
 715     case 0x9d8:\r
 716         return s->pm_evgenontim_mpu;\r
 717     case 0x9dc:\r
 718         return s->pm_evgenofftim_mpu;\r
 719     case 0x9e0:\r
 720         return s->pm_pwstctrl_mpu;\r
 721     case 0x9e4:\r
 722         return s->pm_pwstst_mpu;\r
 723     case 0x9e8:\r
 724         return s->pm_perpwstst_mpu;\r
 725 \r
 726     case 0xa58:\r
 727         return s->rm_rstst_core;\r
 728     case 0xaa0:\r
 729         return s->pm_wken1_core;\r
 730     case 0xaa4:\r
 731         return s->pm_mpugrpsel1_core;\r
 732     case 0xaa8:\r
 733         return s->pm_iva2grpsel1_core;\r
 734     case 0xab0:\r
 735         return s->pm_wkst1_core;\r
 736     case 0xab8:\r
 737         return s->pm_wkst3_core;\r
 738     case 0xae0:\r
 739         return s->pm_pwstctrl_core;\r
 740     case 0xae4:\r
 741         return s->pm_pwstst_core;\r
 742     case 0xae8:\r
 743         return s->pm_prepwstst_core;\r
 744 \r
 745     case 0xb58:\r
 746         return s->rm_rstst_sgx;\r
 747     case 0xbc8:\r
 748         return s->pm_wkdep_sgx;\r
 749     case 0xbe0:\r
 750         return s->pm_pwstctrl_sgx;\r
 751     case 0xbe4:\r
 752         return s->pm_pwstst_sgx;\r
 753     case 0xbe8:\r
 754         return s->pm_prepwstst_sgx;\r
 755 \r
 756         \r
 757     case 0xca0:\r
 758         return s->pm_wken_wkup;\r
 759          case 0xca4:\r
 760         return s->pm_mpugrpsel_wkup ;\r
 761     case 0xca8:\r
 762         return s->pm_iva2grpsel_wkup ;\r
 763          case 0xcb0:\r
 764         return s->pm_wkst_wkup ;\r
 765 \r
 766         \r
 767     case 0xd40:\r
 768         return s->prm_clksel;\r
 769     case 0xd70:\r
 770         return s->prm_clkout_ctrl;\r
 771 \r
 772      case 0xe58:\r
 773         return s->rm_rstst_dss;\r
 774      case 0xea0:\r
 775         return s->pm_wken_dss;\r
 776      case 0xec8:\r
 777         return s->pm_wkdep_dss;\r
 778      case 0xee0:\r
 779         return s->pm_pwstctrl_dss;\r
 780      case 0xee4:\r
 781         return s->pm_pwstst_dss;\r
 782      case 0xee8:\r
 783         return s->pm_prepwstst_dss;\r
 784 \r
 785      case 0xf58:\r
 786         return s->rm_rstst_cam;\r
 787      case 0xfc8:\r
 788         return s->pm_wken_cam ;\r
 789     case 0xfe0:\r
 790         return s->pm_pwstctrl_cam;\r
 791     case 0xfe4:\r
 792         return s->pm_pwstst_cam;\r
 793     case 0xfe8:\r
 794         return s->pm_prepwstst_cam;\r
 795 \r
 796     case 0x1058:\r
 797         return s->rm_rstst_per;\r
 798     case 0x10a0:\r
 799         return s->pm_wken_per ;\r
 800     case 0x10a4:\r
 801         return s->pm_mpugrpsel_per;\r
 802     case 0x10a8:\r
 803         return s->pm_iva2grpsel_per;\r
 804     case 0x10b0:\r
 805         return s->pm_wkst_per;\r
 806     case 0x10c8:\r
 807         return s->pm_wkdep_per;\r
 808     case 0x10e0:\r
 809         return s->pm_pwstctrl_per;\r
 810     case 0x10e4:\r
 811         return s->pm_pwstst_per;\r
 812     case 0x10e8:\r
 813         return s->pm_perpwstst_per;\r
 814 \r
 815         \r
 816     case 0x1220:\r
 817         return s->prm_vc_smps_sa;\r
 818     case 0x1224:\r
 819         return s->prm_vc_smps_vol_ra ;\r
 820     case 0x1228:\r
 821         return s->prm_vc_smps_cmd_ra ;\r
 822     case 0x122c:\r
 823         return s->prm_vc_cmd_val_0 ;\r
 824     case 0x1230:\r
 825         return s->prm_vc_cmd_val_1 ;\r
 826     case 0x1234:\r
 827         return s->prm_vc_hc_conf;\r
 828     case 0x1238:\r
 829         return s->prm_vc_i2c_cfg;\r
 830     case 0x123c:\r
 831         return s->prm_vc_bypass_val;\r
 832         case 0x1250:\r
 833         return s->prm_rstctrl;\r
 834         case 0x1254:\r
 835         return s->prm_rsttimer;\r
 836     case 0x1258:\r
 837         return s->prm_rstst;\r
 838     case 0x1260:\r
 839         return s->prm_voltctrl;\r
 840     case 0x1264:\r
 841         return s->prm_sram_pcharge;     \r
 842     case 0x1270:\r
 843         return s->prm_clksrc_ctrl;\r
 844     case 0x1280:\r
 845         return s->prm_obs;\r
 846     case 0x1290:\r
 847         return s->prm_voltsetup1;\r
 848     case 0x1294:\r
 849         return s->prm_voltoffset;\r
 850     case 0x1298:\r
 851         return s->prm_clksetup;\r
 852     case 0x129c:\r
 853         return s->prm_polctrl;\r
 854     case 0x12a0:\r
 855         return s->prm_voltsetup2;\r
 856 \r
 857     case 0x1358:\r
 858         return s->rm_rstst_neon;\r
 859     case 0x13c8:\r
 860                 return s->pm_wkdep_neon ;\r
 861         case 0x13e0:\r
 862                 return s->pm_pwstctrl_neon;\r
 863         case 0x13e4:\r
 864                 return s->pm_pwstst_neon;\r
 865         case 0x13e8:\r
 866                 return s->pm_prepwstst_neon;\r
 867 \r
 868         case 0x1458:\r
 869                 return s->rm_rstst_usbhost;\r
 870    case 0x14a0:\r
 871                 return s->rm_wken_usbhost ;\r
 872         case 0x14a4:\r
 873                 return s->rm_mpugrpsel_usbhost;\r
 874         case 0x14a8:\r
 875                 return s->rm_iva2grpsel_usbhost;\r
 876         case 0x14b0:\r
 877                 return s->rm_wkst_usbhost;\r
 878     case 0x14c8:\r
 879         return s->rm_wkdep_usbhost;\r
 880     case 0x14e0:\r
 881         return s->rm_pwstctrl_usbhost;\r
 882     case 0x14e4:\r
 883         return s->rm_pwstst_usbhost;\r
 884     case 0x14e8:\r
 885         return s->rm_prepwstst_usbhost;\r
 886 \r
 887     default:\r
 888          printf("prm READ offset %x\n",addr);\r
 889         exit(-1);\r
 890     }\r
 891 }\r
 892 \r
 893 static inline void omap3_prm_clksrc_ctrl_update(struct omap3_prm_s *s,\r
 894                                                 uint32_t value)\r
 895 {\r
 896     if ((value & 0xd0) == 0x40)\r
 897         omap_clk_setrate(omap_findclk(s->mpu, "omap3_sys_clk"), 1, 1);\r
 898     else if ((value & 0xd0) == 0x80)\r
 899         omap_clk_setrate(omap_findclk(s->mpu, "omap3_sys_clk"), 2, 1);\r
 900     //OMAP3_DEBUG(("omap3_sys_clk %d \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_sys_clk"))));\r
 901 }\r
 902 static void omap3_prm_write(void *opaque, target_phys_addr_t addr,\r
 903                             uint32_t value)\r
 904 {\r
 905     struct omap3_prm_s *s = (struct omap3_prm_s *) opaque;\r
 906 \r
 907     switch (addr)\r
 908     {\r
 909     case 0xc8:\r
 910         s->pm_wkdep_iva2 = value & 0xb3;\r
 911         break;\r
 912     case 0xe0:\r
 913         s->pm_pwstctrl_iva2 = value & 0xff0f0f;\r
 914         break;\r
 915     case 0xe4:\r
 916         s->pm_pwstst_iva2 = value & 0x100ff7;\r
 917         break;\r
 918     case 0xe8:\r
 919         s->pm_prepwstst_iva2 = value & 0xff7;\r
 920         break;\r
 921     case 0x814:\r
 922         s->prm_sysconfig = value &0x1;\r
 923         break;\r
 924     case 0x818:\r
 925         s->prm_irqstatus_mpu = 0x0;\r
 926         break;\r
 927     case 0x81c:\r
 928         s->prm_irqenable_mpu = 0x3ffffff;\r
 929         break;\r
 930     case 0x9c8:\r
 931         s->pm_wkdep_mpu = value & 0xa5;;\r
 932         break;\r
 933     case 0x9e0:\r
 934         s->pm_pwstctrl_mpu = value & 0x3010f;\r
 935         break;\r
 936     case 0x9e4:\r
 937         s->pm_pwstst_mpu = value & 0x1000c7;\r
 938         break;\r
 939     case 0x9e8:\r
 940         s->pm_perpwstst_mpu = value & 0xc7;\r
 941         break;\r
 942     case 0xae0:\r
 943         s->pm_pwstctrl_core = value & 0xf0307;\r
 944         break;\r
 945     case 0xae4:\r
 946         s->pm_pwstst_core = value & 0x1000f3;\r
 947         break;\r
 948     case 0xae8:\r
 949         s->pm_prepwstst_core = value & 0xf7;\r
 950         break;\r
 951     case 0xbc8:\r
 952         s->pm_wkdep_sgx = value & 0x17;\r
 953         break;\r
 954    case 0xbe0:\r
 955                 s->pm_pwstctrl_sgx = value & 0x30107;\r
 956                 break;\r
 957         case 0xbe4:\r
 958                 s->pm_pwstst_sgx = value & 0x100003;;\r
 959                 break;\r
 960         case 0xbe8:\r
 961                 s->pm_prepwstst_sgx = value & 0x3;\r
 962                 break;          \r
 963     case 0xca0:\r
 964         s->pm_wken_wkup = value & 0x3cb;\r
 965         break;\r
 966     case 0xca4:\r
 967         s->pm_mpugrpsel_wkup = value & 0x3cb;\r
 968         break;\r
 969     case 0xca8:\r
 970         s->pm_iva2grpsel_wkup = value & 0x3cb;\r
 971         break;\r
 972          case 0xcac:\r
 973         s->pm_wkst_wkup = value & 0x3cb;\r
 974         break;\r
 975     case 0xd40:\r
 976         s->prm_clksel = value & 0x7;\r
 977         break;\r
 978     case 0xec8:\r
 979          s->pm_wkdep_dss = value & 0x16;\r
 980          break;\r
 981     case 0xee0:\r
 982         s->pm_pwstctrl_dss = value & 0x30107;\r
 983         break;\r
 984     case 0xee4:\r
 985         s->pm_pwstst_dss = value & 0x100003;\r
 986         break;\r
 987     case 0xee8:\r
 988         s->pm_prepwstst_dss = value &0x3;\r
 989         break;\r
 990     case 0xfc8:\r
 991         s->pm_wken_cam = value & 0x16;\r
 992          break;\r
 993     case 0xfe0:\r
 994         s->pm_pwstctrl_cam = value & 0x30107;\r
 995         break;\r
 996     case 0xfe4:\r
 997         s->pm_pwstst_cam = value & 0x100003;\r
 998         break;\r
 999     case 0xfe8:\r
1000         s->pm_prepwstst_cam = value & 0x3;\r
1001         break;\r
1002     case 0x10c8:\r
1003         s->pm_wkdep_per = value & 0x17;\r
1004                 break;\r
1005     case 0x10a0:\r
1006         s->pm_wken_per = value & 0x3efff;\r
1007         break;\r
1008     case 0x10e0:\r
1009                 s->pm_pwstctrl_per = value & 0x30107;\r
1010                 break;\r
1011         case 0x10e4:\r
1012                 s->pm_pwstst_per = value & 0x100003;;\r
1013                 break;\r
1014         case 0x10e8:\r
1015                 s->pm_perpwstst_per = value & 0x3;\r
1016                 break;          \r
1017     case 0x1220:\r
1018         s->prm_vc_smps_sa = value & 0x7f007f;\r
1019         break;\r
1020     case 0x1224:\r
1021         s->prm_vc_smps_vol_ra = value & 0xff00ff;\r
1022         break;\r
1023     case 0x1228:\r
1024         s->prm_vc_smps_cmd_ra = value & 0xff00ff;\r
1025         break;\r
1026     case 0x122c:\r
1027         s->prm_vc_cmd_val_0 = value ;\r
1028         break;\r
1029     case 0x1230:\r
1030         s->prm_vc_cmd_val_1 = value ;\r
1031         break;\r
1032     case 0x1234:\r
1033         s->prm_vc_hc_conf = value & 0x1f001f;\r
1034         break;\r
1035     case 0x1238:\r
1036         s->prm_vc_i2c_cfg = value & 0x3f;\r
1037         break;\r
1038     case 0x123c:\r
1039         s->prm_vc_bypass_val = value;\r
1040         break;\r
1041     case 0x1250:\r
1042         s->prm_rstctrl = value & 0x7;\r
1043         /*TODO: Software reset*/\r
1044         break;\r
1045     case 0x1254:\r
1046         s->prm_rsttimer = value & 0x1fff;\r
1047         break;\r
1048     case 0x1258:\r
1049         s->prm_rstst = value & 0x7ff;\r
1050         break;\r
1051     case 0x1260:\r
1052         s->prm_voltctrl = value & 0x1f;\r
1053         break;\r
1054     case 0x1264:\r
1055         s->prm_sram_pcharge = value &0xff;\r
1056         break;\r
1057     case 0x1270:\r
1058         s->prm_clksrc_ctrl = value & (0xd8);\r
1059         omap3_prm_clksrc_ctrl_update(s, s->prm_clksrc_ctrl);\r
1060         break;\r
1061     case 0x1290:\r
1062         s->prm_voltsetup1 = value;\r
1063         break;\r
1064     case 0x1294:\r
1065         s->prm_voltoffset = value&0xffff;\r
1066         break;\r
1067     case 0x1298:\r
1068         s->prm_clksetup = value&0xffff;\r
1069         break;\r
1070     case 0x129c:\r
1071          s->prm_polctrl = value&0xf;\r
1072          break;\r
1073     case 0x12a0:\r
1074         s->prm_voltsetup2 = value & 0xffff;\r
1075         break;\r
1076    case 0x13c8:\r
1077                 s->pm_wkdep_neon = value & 0x2;\r
1078                 break;\r
1079         case 0x13e0:\r
1080                 s->pm_pwstctrl_neon = value & 0x7;\r
1081                 break;\r
1082         case 0x13e4:\r
1083                 s->pm_pwstst_neon = value & 0x100003;\r
1084                 break;\r
1085    case 0x13e8:\r
1086                 s->pm_prepwstst_neon = value & 0x3;\r
1087                 break;\r
1088    case 0x14a0:\r
1089                 s->rm_wken_usbhost = value &0x1;\r
1090                 break;\r
1091     case 0x14c8:\r
1092         s->rm_wkdep_usbhost = value & 0x17;\r
1093         break;\r
1094     case 0x14e0:\r
1095         s->rm_pwstctrl_usbhost = value & 0x30117;\r
1096         break;\r
1097     case 0x14e4:\r
1098         s->rm_pwstst_usbhost = value & 0x100002;\r
1099         break;\r
1100     case 0x14e8:\r
1101         s->rm_prepwstst_usbhost = value & 0x2;\r
1102         break;\r
1103 \r
1104     default:\r
1105         printf("omap3_prm_write addr %x value %x \n", addr, value);\r
1106         exit(-1);\r
1107     }\r
1108 }\r
1109 \r
1110 \r
1111 static CPUReadMemoryFunc *omap3_prm_readfn[] = {\r
1112     omap_badwidth_read32,\r
1113     omap_badwidth_read32,\r
1114     omap3_prm_read,\r
1115 };\r
1116 \r
1117 static CPUWriteMemoryFunc *omap3_prm_writefn[] = {\r
1118     omap_badwidth_write32,\r
1119     omap_badwidth_write32,\r
1120     omap3_prm_write,\r
1121 };\r
1122 \r
1123 struct omap3_prm_s *omap3_prm_init(struct omap_target_agent_s *ta,\r
1124                                    qemu_irq mpu_int, qemu_irq dsp_int,\r
1125                                    qemu_irq iva_int,\r
1126                                    struct omap_mpu_state_s *mpu)\r
1127 {\r
1128     int iomemtype;\r
1129     struct omap3_prm_s *s = (struct omap3_prm_s *) qemu_mallocz(sizeof(*s));\r
1130 \r
1131     s->irq[0] = mpu_int;\r
1132     s->irq[1] = dsp_int;\r
1133     s->irq[2] = iva_int;\r
1134     s->mpu = mpu;\r
1135     omap3_prm_reset(s);\r
1136 \r
1137     iomemtype = l4_register_io_memory(0, omap3_prm_readfn,\r
1138                                       omap3_prm_writefn, s);\r
1139     omap_l4_attach(ta, 0, iomemtype);\r
1140     omap_l4_attach(ta, 1, iomemtype);\r
1141 \r
1142     return s;\r
1143 }\r
1144 \r
1145 \r
1146 struct omap3_cm_s\r
1147 {\r
1148     qemu_irq irq[3];\r
1149     struct omap_mpu_state_s *mpu;\r
1150 \r
1151     /*IVA2_CM Register */\r
1152     uint32_t cm_fclken_iva2;    /*0x4800 4000 */\r
1153     uint32_t cm_clken_pll_iva2; /*0x4800 4004 */\r
1154     uint32_t cm_idlest_iva2;    /*0x4800 4020 */\r
1155     uint32_t cm_idlest_pll_iva2;        /*0x4800 4024 */\r
1156     uint32_t cm_autoidle_pll_iva2;      /*0x4800 4034 */\r
1157     uint32_t cm_clksel1_pll_iva2;       /*0x4800 4040 */\r
1158     uint32_t cm_clksel2_pll_iva2;       /*0x4800 4044 */\r
1159     uint32_t cm_clkstctrl_iva2; /*0x4800 4048 */\r
1160     uint32_t cm_clkstst_iva2;   /*0x4800 404c */\r
1161 \r
1162     /*OCP_System_Reg_CM */\r
1163     uint32_t cm_revision;       /*0x4800 4800 */\r
1164     uint32_t cm_sysconfig;      /*0x4800 4810 */\r
1165 \r
1166     /*MPU_CM Register */\r
1167     uint32_t cm_clken_pll_mpu;  /*0x4800 4904 */\r
1168     uint32_t cm_idlest_mpu;     /*0x4800 4920 */\r
1169     uint32_t cm_idlest_pll_mpu; /*0x4800 4924 */\r
1170     uint32_t cm_autoidle_pll_mpu;       /*0x4800 4934 */\r
1171     uint32_t cm_clksel1_pll_mpu;        /*0x4800 4940 */\r
1172     uint32_t cm_clksel2_pll_mpu;        /*0x4800 4944 */\r
1173     uint32_t cm_clkstctrl_mpu;  /*0x4800 4948 */\r
1174     uint32_t cm_clkstst_mpu;    /*0x4800 494c */\r
1175 \r
1176     /*CORE_CM Register */\r
1177     uint32_t cm_fclken1_core;   /*0x4800 4a00 */\r
1178     uint32_t cm_fclken3_core;   /*0x4800 4a08 */\r
1179     uint32_t cm_iclken1_core;   /*0x4800 4a10 */\r
1180     uint32_t cm_iclken2_core;   /*0x4800 4a14 */\r
1181     uint32_t cm_iclken3_core;   /*0x4800 4a18 */\r
1182     uint32_t cm_idlest1_core;   /*0x4800 4a20 */\r
1183     uint32_t cm_idlest2_core;   /*0x4800 4a24 */\r
1184     uint32_t cm_idlest3_core;   /*0x4800 4a28 */\r
1185     uint32_t cm_autoidle1_core; /*0x4800 4a30 */\r
1186     uint32_t cm_autoidle2_core; /*0x4800 4a34 */\r
1187     uint32_t cm_autoidle3_core; /*0x4800 4a38 */\r
1188     uint32_t cm_clksel_core;    /*0x4800 4a40 */\r
1189     uint32_t cm_clkstctrl_core; /*0x4800 4a48 */\r
1190     uint32_t cm_clkstst_core;   /*0x4800 4a4c */\r
1191 \r
1192     /*SGX_CM Register */\r
1193     uint32_t cm_fclken_sgx;     /*0x4800 4b00 */\r
1194     uint32_t cm_iclken_sgx;     /*0x4800 4b10 */\r
1195     uint32_t cm_idlest_sgx;     /*0x4800 4b20 */\r
1196     uint32_t cm_clksel_sgx;     /*0x4800 4b40 */\r
1197     uint32_t cm_sleepdep_sgx;   /*0x4800 4b44 */\r
1198     uint32_t cm_clkstctrl_sgx;  /*0x4800 4b48 */\r
1199     uint32_t cm_clkstst_sgx;    /*0x4800 4b4c */\r
1200 \r
1201     /*WKUP_CM Register */\r
1202     uint32_t cm_fclken_wkup;    /*0x4800 4c00 */\r
1203     uint32_t cm_iclken_wkup;    /*0x4800 4c10 */\r
1204     uint32_t cm_idlest_wkup;    /*0x4800 4c20 */\r
1205     uint32_t cm_autoidle_wkup;  /*0x4800 4c30 */\r
1206     uint32_t cm_clksel_wkup;    /*0x4800 4c40 */\r
1207     uint32_t cm_c48;                  /*0x4800 4c48 */\r
1208 \r
1209     /*Clock_Control_Reg_CM Register */\r
1210     uint32_t cm_clken_pll;      /*0x4800 4d00 */\r
1211     uint32_t cm_clken2_pll;     /*0x4800 4d04 */\r
1212     uint32_t cm_idlest_ckgen;   /*0x4800 4d20 */\r
1213     uint32_t cm_idlest2_ckgen;  /*0x4800 4d24 */\r
1214     uint32_t cm_autoidle_pll;   /*0x4800 4d30 */\r
1215     uint32_t cm_autoidle2_pll;  /*0x4800 4d34 */\r
1216     uint32_t cm_clksel1_pll;    /*0x4800 4d40 */\r
1217     uint32_t cm_clksel2_pll;    /*0x4800 4d44 */\r
1218     uint32_t cm_clksel3_pll;    /*0x4800 4d48 */\r
1219     uint32_t cm_clksel4_pll;    /*0x4800 4d4c */\r
1220     uint32_t cm_clksel5_pll;    /*0x4800 4d50 */\r
1221     uint32_t cm_clkout_ctrl;    /*0x4800 4d70 */\r
1222 \r
1223     /*DSS_CM Register */\r
1224     uint32_t cm_fclken_dss;     /*0x4800 4e00 */\r
1225     uint32_t cm_iclken_dss;     /*0x4800 4e10 */\r
1226     uint32_t cm_idlest_dss;     /*0x4800 4e20 */\r
1227     uint32_t cm_autoidle_dss;   /*0x4800 4e30 */\r
1228     uint32_t cm_clksel_dss;     /*0x4800 4e40 */\r
1229     uint32_t cm_sleepdep_dss;   /*0x4800 4e44 */\r
1230     uint32_t cm_clkstctrl_dss;  /*0x4800 4e48 */\r
1231     uint32_t cm_clkstst_dss;    /*0x4800 4e4c */\r
1232 \r
1233 \r
1234     /*CAM_CM Register */\r
1235     uint32_t cm_fclken_cam;     /*0x4800 4f00 */\r
1236     uint32_t cm_iclken_cam;     /*0x4800 4f10 */\r
1237     uint32_t cm_idlest_cam;     /*0x4800 4f20 */\r
1238     uint32_t cm_autoidle_cam;   /*0x4800 4f30 */\r
1239     uint32_t cm_clksel_cam;     /*0x4800 4f40 */\r
1240     uint32_t cm_sleepdep_cam;   /*0x4800 4f44 */\r
1241     uint32_t cm_clkstctrl_cam;  /*0x4800 4f48 */\r
1242     uint32_t cm_clkstst_cam;    /*0x4800 4f4c */\r
1243 \r
1244     /*PER_CM Register */\r
1245     uint32_t cm_fclken_per;     /*0x4800 5000 */\r
1246     uint32_t cm_iclken_per;     /*0x4800 5010 */\r
1247     uint32_t cm_idlest_per;     /*0x4800 5020 */\r
1248     uint32_t cm_autoidle_per;   /*0x4800 5030 */\r
1249     uint32_t cm_clksel_per;     /*0x4800 5040 */\r
1250     uint32_t cm_sleepdep_per;   /*0x4800 5044 */\r
1251     uint32_t cm_clkstctrl_per;  /*0x4800 5048 */\r
1252     uint32_t cm_clkstst_per;    /*0x4800 504c */\r
1253 \r
1254     /*EMU_CM Register */\r
1255     uint32_t cm_clksel1_emu;    /*0x4800 5140 */\r
1256     uint32_t cm_clkstctrl_emu;  /*0x4800 5148 */\r
1257     uint32_t cm_clkstst_emu;    /*0x4800 514c */\r
1258     uint32_t cm_clksel2_emu;    /*0x4800 5150 */\r
1259     uint32_t cm_clksel3_emu;    /*0x4800 5154 */\r
1260 \r
1261     /*Global_Reg_CM Register */\r
1262     uint32_t cm_polctrl;        /*0x4800 529c */\r
1263 \r
1264     /*NEON_CM Register */\r
1265     uint32_t cm_idlest_neon;    /*0x4800 5320 */\r
1266     uint32_t cm_clkstctrl_neon; /*0x4800 5348 */\r
1267 \r
1268     /*USBHOST_CM Register */\r
1269     uint32_t cm_fclken_usbhost; /*0x4800 5400 */\r
1270     uint32_t cm_iclken_usbhost; /*0x4800 5410 */\r
1271     uint32_t cm_idlest_usbhost; /*0x4800 5420 */\r
1272     uint32_t cm_autoidle_usbhost;       /*0x4800 5430 */\r
1273     uint32_t cm_sleepdep_usbhost;       /*0x4800 5444 */\r
1274     uint32_t cm_clkstctrl_usbhost;      /*0x4800 5448 */\r
1275     uint32_t cm_clkstst_usbhost;        /*0x4800 544c */\r
1276 \r
1277 };\r
1278 \r
1279 /*\r
1280 static inline void omap3_cm_fclken_wkup_update(struct omap3_cm_s *s,\r
1281                 uint32_t value)\r
1282 {\r
1283         \r
1284         if (value & 0x28)\r
1285         omap_clk_onoff(omap_findclk(s->mpu,"omap3_wkup_32k_fclk"), 1);\r
1286     else\r
1287         omap_clk_onoff(omap_findclk(s->mpu,"omap3_wkup_32k_fclk"), 0);\r
1288 \r
1289     if (value &0x1)\r
1290         omap_clk_onoff(omap_findclk(s->mpu,"omap3_gp1_fclk"), 1);\r
1291     else\r
1292         omap_clk_onoff(omap_findclk(s->mpu,"omap3_gp1_fclk"), 0);\r
1293 \r
1294 }\r
1295 static inline void omap3_cm_iclken_wkup_update(struct omap3_cm_s *s,\r
1296                 uint32_t value)\r
1297 {\r
1298         \r
1299         if (value & 0x3f)\r
1300         omap_clk_onoff(omap_findclk(s->mpu,"omap3_wkup_l4_iclk"), 1);\r
1301     else\r
1302         omap_clk_onoff(omap_findclk(s->mpu,"omap3_wkup_l4_iclk"), 0);\r
1303 \r
1304 }\r
1305 */\r
1306 static inline void omap3_cm_clksel_wkup_update(struct omap3_cm_s *s,\r
1307                                                uint32_t value)\r
1308 {\r
1309     omap_clk gp1_fclk = omap_findclk(s->mpu, "omap3_gp1_fclk");\r
1310 \r
1311     if (value & 0x1)\r
1312         omap_clk_reparent(gp1_fclk, omap_findclk(s->mpu, "omap3_sys_clk"));\r
1313     else\r
1314         omap_clk_reparent(gp1_fclk, omap_findclk(s->mpu, "omap3_32k_fclk"));\r
1315     /*Tell GPTIMER to generate new clk rate */\r
1316     omap_gp_timer_change_clk(s->mpu->gptimer[0]);\r
1317 \r
1318     OMAP3_DEBUG(("omap3_gp1_fclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp1_fclk"))));\r
1319 \r
1320     /*TODO:CM_USIM_CLK CLKSEL_RM */\r
1321 }\r
1322 \r
1323 static inline void omap3_cm_mpu_update(struct omap3_cm_s *s)\r
1324 {\r
1325     uint32_t m, n, divide, m2, cm_clken_pll_mpu;\r
1326     uint32_t bypass = 1;\r
1327 \r
1328     cm_clken_pll_mpu = s->cm_clken_pll_mpu;\r
1329     omap_clk mpu_clk = omap_findclk(s->mpu, "omap3_mpu_clk");\r
1330 \r
1331     if ((cm_clken_pll_mpu & 0x7) == 0x5)\r
1332     {\r
1333         bypass = 1;\r
1334     }\r
1335     else if ((cm_clken_pll_mpu & 0x7) == 0x7)\r
1336     {\r
1337         m = (s->cm_clksel1_pll_mpu & 0x7ff00) >> 8;\r
1338         if ((m == 0) || (m == 1))\r
1339             bypass = 1;\r
1340         else\r
1341             bypass = 0;\r
1342     }\r
1343     if (bypass == 1)\r
1344     {\r
1345         /*BYPASS Model */\r
1346         divide = (s->cm_clksel1_pll_mpu & 0x380000) >> 19;\r
1347         //OMAP3_DEBUG(("divide %d\n",divide));\r
1348         omap_clk_reparent(mpu_clk, omap_findclk(s->mpu, "omap3_core_clk"));\r
1349         omap_clk_setrate(mpu_clk, divide, 1);\r
1350 \r
1351     }\r
1352     else\r
1353     {\r
1354         n = (s->cm_clksel1_pll_mpu & 0x7F);\r
1355         m2 = (s->cm_clksel2_pll_mpu & 0x1F);\r
1356         //OMAP3_DEBUG(("M  %d N %d M2 %d \n",m,n,m2 ));\r
1357         omap_clk_reparent(mpu_clk, omap_findclk(s->mpu, "omap3_sys_clk"));\r
1358         omap_clk_setrate(mpu_clk, (n + 1) * m2, m);\r
1359         //OMAP3_DEBUG(("mpu %d \n",omap_clk_getrate(mpu_clk)));\r
1360 \r
1361     }\r
1362 \r
1363 }\r
1364 static inline void omap3_cm_iva2_update(struct omap3_cm_s *s)\r
1365 {\r
1366     uint32_t m, n, divide, m2, cm_clken_pll_iva2;\r
1367     uint32_t bypass = 1;\r
1368 \r
1369     cm_clken_pll_iva2 = s->cm_clken_pll_iva2;\r
1370     omap_clk iva2_clk = omap_findclk(s->mpu, "omap3_iva2_clk");\r
1371 \r
1372     if (((cm_clken_pll_iva2 & 0x7) == 0x5)\r
1373         || ((cm_clken_pll_iva2 & 0x7) == 0x1))\r
1374     {\r
1375         bypass = 1;\r
1376     }\r
1377     else if ((cm_clken_pll_iva2 & 0x7) == 0x7)\r
1378     {\r
1379         m = (s->cm_clksel1_pll_iva2 & 0x7ff00) >> 8;\r
1380         if ((m == 0) || (m == 1))\r
1381             bypass = 1;\r
1382         else\r
1383             bypass = 0;\r
1384     }\r
1385     if (bypass == 1)\r
1386     {\r
1387         /*BYPASS Model */\r
1388         divide = (s->cm_clksel1_pll_iva2 & 0x380000) >> 19;\r
1389         //OMAP3_DEBUG(("divide %d\n",divide));\r
1390         omap_clk_reparent(iva2_clk, omap_findclk(s->mpu, "omap3_core_clk"));\r
1391         omap_clk_setrate(iva2_clk, divide, 1);\r
1392 \r
1393     }\r
1394     else\r
1395     {\r
1396         n = (s->cm_clksel1_pll_iva2 & 0x7F);\r
1397         m2 = (s->cm_clksel2_pll_iva2 & 0x1F);\r
1398         //OMAP3_DEBUG(("M  %d N %d M2 %d \n",m,n,m2 ));\r
1399         omap_clk_reparent(iva2_clk, omap_findclk(s->mpu, "omap3_sys_clk"));\r
1400         omap_clk_setrate(iva2_clk, (n + 1) * m2, m);\r
1401         //OMAP3_DEBUG(("iva2_clk %d \n",omap_clk_getrate(iva2_clk)));\r
1402 \r
1403     }\r
1404 \r
1405 }\r
1406 \r
1407 static inline void omap3_cm_dpll3_update(struct omap3_cm_s *s)\r
1408 {\r
1409     uint32_t m, n, m2, m3, cm_clken_pll;\r
1410     uint32_t bypass = 1;\r
1411 \r
1412     cm_clken_pll = s->cm_clken_pll;\r
1413 \r
1414     /*dpll3 bypass mode. parent clock is always omap3_sys_clk */\r
1415     if (((cm_clken_pll & 0x7) == 0x5) || ((cm_clken_pll & 0x7) == 0x6))\r
1416     {\r
1417         bypass = 1;\r
1418     }\r
1419     else if ((cm_clken_pll & 0x7) == 0x7)\r
1420     {\r
1421         m = (s->cm_clksel1_pll & 0x7ff0000) >> 16;\r
1422         if ((m == 0) || (m == 1))\r
1423             bypass = 1;\r
1424         else\r
1425             bypass = 0;\r
1426     }\r
1427     if (bypass == 1)\r
1428     {\r
1429         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core_clk"), 1, 1);\r
1430         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core2_clk"), 1, 1);\r
1431         omap_clk_setrate(omap_findclk(s->mpu, "omap3_emu_core_alwon_clk"), 1,\r
1432                          1);\r
1433     }\r
1434     else\r
1435     {\r
1436         n = (s->cm_clksel1_pll & 0x3f00) >> 8;\r
1437         m2 = (s->cm_clksel1_pll & 0xf8000000) >> 27;\r
1438         m3 = (s->cm_clksel1_emu & 0x1f0000) >> 16;\r
1439 \r
1440         if (s->cm_clksel2_emu&0x80000)\r
1441         {\r
1442                 /*override control of DPLL3*/\r
1443                 m = (s->cm_clksel2_emu&0x7ff)>>8;\r
1444                 n =  s->cm_clksel2_emu&0x7f;\r
1445                 OMAP3_DEBUG(("DPLL3 override, m 0x%x n 0x%x \n",m,n));\r
1446         }\r
1447 \r
1448         //OMAP3_DEBUG(("dpll3 cm_clksel1_pll %x m  %d n %d m2 %d  m3 %d\n",s->cm_clksel1_pll,m,n,m2,m3 ));\r
1449         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core_clk"), (n + 1) * m2,\r
1450                          m);\r
1451         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core2_clk"), (n + 1) * m2,\r
1452                          m * 2);\r
1453         omap_clk_setrate(omap_findclk(s->mpu, "omap3_emu_core_alwon_clk"),\r
1454                          (n + 1) * m3, m * 2);\r
1455         OMAP3_DEBUG(("coreclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_core_clk"))));\r
1456     }\r
1457 \r
1458 \r
1459 }\r
1460 \r
1461 \r
1462 static inline void omap3_cm_dpll4_update(struct omap3_cm_s *s)\r
1463 {\r
1464     uint32_t m, n, m2, m3, m4, m5, m6, cm_clken_pll;\r
1465     cm_clken_pll = s->cm_clken_pll;\r
1466     uint32_t bypass = 1;\r
1467 \r
1468     /*dpll3 bypass mode. parent clock is always omap3_sys_clk */\r
1469     /*DPLL4 */\r
1470     if ((cm_clken_pll & 0x70000) == 0x10000)\r
1471     {\r
1472         bypass = 1;\r
1473     }\r
1474     else if ((cm_clken_pll & 0x70000) == 0x70000)\r
1475     {\r
1476         m = (s->cm_clksel2_pll & 0x7ff00) >> 8;\r
1477         if ((m == 0) || (m == 1))\r
1478             bypass = 1;\r
1479         else\r
1480             bypass = 0;\r
1481     }\r
1482     if (bypass == 1)\r
1483     {\r
1484         omap_clk_setrate(omap_findclk(s->mpu, "omap3_96m_fclk"), 1, 1);\r
1485         omap_clk_setrate(omap_findclk(s->mpu, "omap3_54m_fclk"), 1, 1);\r
1486         omap_clk_setrate(omap_findclk(s->mpu, "omap3_dss1_alwon_fclk"), 1, 1);\r
1487         omap_clk_setrate(omap_findclk(s->mpu, "omap3_cam_mclk"), 1, 1);\r
1488         omap_clk_setrate(omap_findclk(s->mpu, "omap3_per_alwon_clk"), 1, 1);\r
1489     }\r
1490     else\r
1491     {\r
1492         n = (s->cm_clksel2_pll & 0x7f);\r
1493         m2 = s->cm_clksel3_pll & 0x1f;\r
1494         m3 = (s->cm_clksel_dss & 0x1f00) >> 8;\r
1495         m4 = s->cm_clksel_dss & 0x1f;\r
1496         m5 = s->cm_clksel_cam & 0x1f;\r
1497         m6 = (s->cm_clksel1_emu & 0x1f000000) >> 24;\r
1498 \r
1499         if (s->cm_clksel3_emu&0x80000)\r
1500         {\r
1501                 /*override control of DPLL4*/\r
1502                 m = (s->cm_clksel3_emu&0x7ff)>>8;\r
1503                 n =  s->cm_clksel3_emu&0x7f;\r
1504                 OMAP3_DEBUG(("DPLL4 override, m 0x%x n 0x%x \n",m,n));\r
1505         }\r
1506 \r
1507 \r
1508         //OMAP3_DEBUG(("dpll4 m  %d n %d m2 %d  m3 %d m4 %d m5 %d m6 %d \n",m,n,m2,m3,m4,m5,m6 ));\r
1509         omap_clk_setrate(omap_findclk(s->mpu, "omap3_96m_fclk"), (n + 1) * m2,\r
1510                          m * 2);\r
1511         omap_clk_setrate(omap_findclk(s->mpu, "omap3_54m_fclk"), (n + 1) * m3,\r
1512                          m * 2);\r
1513         omap_clk_setrate(omap_findclk(s->mpu, "omap3_dss1_alwon_fclk"),\r
1514                          (n + 1) * m4, m * 2);\r
1515         omap_clk_setrate(omap_findclk(s->mpu, "omap3_cam_mclk"), (n + 1) * m5,\r
1516                          m * 2);\r
1517         omap_clk_setrate(omap_findclk(s->mpu, "omap3_per_alwon_clk"),\r
1518                          (n + 1) * m6, m * 2);\r
1519 \r
1520         OMAP3_DEBUG(("omap3_96m_fclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_96m_fclk"))));\r
1521         OMAP3_DEBUG(("omap3_54m_fclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_54m_fclk"))));\r
1522         OMAP3_DEBUG(("omap3_dss1_alwon_fclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_dss1_alwon_fclk"))));\r
1523         OMAP3_DEBUG(("omap3_cam_mclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_cam_mclk"))));\r
1524         OMAP3_DEBUG(("omap3_per_alwon_clk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_per_alwon_clk"))));\r
1525         OMAP3_DEBUG(("omap3_48m_fclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_48m_fclk"))));\r
1526         OMAP3_DEBUG(("omap3_12m_fclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_12m_fclk"))));\r
1527 \r
1528                         //printf("omap3_cm_dpll4_update \n");\r
1529     }\r
1530 }\r
1531 \r
1532 static inline void omap3_cm_dpll5_update(struct omap3_cm_s *s)\r
1533 {\r
1534          uint32_t m, n, m2, cm_idlest2_ckgen;\r
1535     uint32_t bypass = 1;\r
1536 \r
1537     cm_idlest2_ckgen = s->cm_idlest2_ckgen;;\r
1538 \r
1539     /*dpll5 bypass mode */\r
1540     if ((cm_idlest2_ckgen & 0x1) == 0x0) \r
1541     {\r
1542         bypass = 1;\r
1543     }\r
1544 \r
1545     if (bypass == 1)\r
1546     {\r
1547         omap_clk_setrate(omap_findclk(s->mpu, "omap3_120m_fclk"), 1, 1);\r
1548     }\r
1549     else\r
1550     {\r
1551          m = (s->cm_clksel4_pll & 0x7ff00)>>8;\r
1552         n = s->cm_clksel4_pll & 0x3f00;\r
1553         m2 = s->cm_clksel5_pll & 0x1f;\r
1554 \r
1555         OMAP3_DEBUG(("dpll5 m %d n %d m2 %d\n",m,n,m2 ));\r
1556         omap_clk_setrate(omap_findclk(s->mpu, "omap3_120m_fclk"), (n + 1) * m2,\r
1557                          m);\r
1558         OMAP3_DEBUG(("omap3_120m_fclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_120m_fclk"))));\r
1559     }\r
1560 \r
1561 \r
1562 }\r
1563 static inline void omap3_cm_48m_update(struct omap3_cm_s *s)\r
1564 {\r
1565     if (s->cm_clksel1_pll & 0x8)\r
1566     {\r
1567         /*parent is sysaltclk */\r
1568         omap_clk_reparent(omap_findclk(s->mpu, "omap3_48m_fclk"),\r
1569                           omap_findclk(s->mpu, "omap3_sys_altclk"));\r
1570         omap_clk_reparent(omap_findclk(s->mpu, "omap3_12m_fclk"),\r
1571                           omap_findclk(s->mpu, "omap3_sys_altclk"));\r
1572         /*TODO:need to set rate ? */\r
1573 \r
1574     }\r
1575     else\r
1576     {\r
1577         omap_clk_reparent(omap_findclk(s->mpu, "omap3_12m_fclk"),\r
1578                           omap_findclk(s->mpu, "omap3_96m_fclk"));\r
1579         omap_clk_reparent(omap_findclk(s->mpu, "omap3_48m_fclk"),\r
1580                           omap_findclk(s->mpu, "omap3_96m_fclk"));\r
1581         omap_clk_setrate(omap_findclk(s->mpu, "omap3_48m_fclk"), 2, 1);\r
1582         omap_clk_setrate(omap_findclk(s->mpu, "omap3_12m_fclk"), 8, 1);\r
1583 \r
1584     }\r
1585 \r
1586 }\r
1587 \r
1588 static inline void omap3_cm_gp10_update(struct omap3_cm_s *s)\r
1589 {\r
1590     omap_clk gp10_fclk = omap_findclk(s->mpu, "omap3_gp10_fclk");\r
1591 \r
1592     if (s->cm_clksel_core & 0x40)\r
1593         omap_clk_reparent(gp10_fclk, omap_findclk(s->mpu, "omap3_sys_clk"));\r
1594     else\r
1595         omap_clk_reparent(gp10_fclk, omap_findclk(s->mpu, "omap3_32k_fclk"));\r
1596 \r
1597     /*Tell GPTIMER10 to generate new clk rate */\r
1598     omap_gp_timer_change_clk(s->mpu->gptimer[9]);\r
1599     OMAP3_DEBUG(("omap3_gp10_fclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp10_fclk"))));\r
1600 }\r
1601 \r
1602 static inline void omap3_cm_gp11_update(struct omap3_cm_s *s)\r
1603 {\r
1604     omap_clk gp11_fclk = omap_findclk(s->mpu, "omap3_gp11_fclk");\r
1605 \r
1606     if (s->cm_clksel_core & 0x80)\r
1607         omap_clk_reparent(gp11_fclk, omap_findclk(s->mpu, "omap3_sys_clk"));\r
1608     else\r
1609         omap_clk_reparent(gp11_fclk, omap_findclk(s->mpu, "omap3_32k_fclk"));\r
1610     /*Tell GPTIMER10 to generate new clk rate */\r
1611     omap_gp_timer_change_clk(s->mpu->gptimer[10]);\r
1612     OMAP3_DEBUG(("omap3_gp11_fclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp11_fclk"))));\r
1613 }\r
1614 \r
1615 static inline void omap3_cm_l3clk_update(struct omap3_cm_s *s)\r
1616 {\r
1617     omap_clk l3_iclk = omap_findclk(s->mpu, "omap3_l3_iclk");\r
1618     if ((s->cm_clksel_core & 0x3) == 0x1)\r
1619         omap_clk_setrate(l3_iclk, 1, 1);\r
1620     else if ((s->cm_clksel_core & 0x3) == 0x2)\r
1621         omap_clk_setrate(l3_iclk, 2, 1);\r
1622 }\r
1623 \r
1624 static inline void omap3_cm_l4clk_update(struct omap3_cm_s *s)\r
1625 {\r
1626     omap_clk l4_iclk = omap_findclk(s->mpu, "omap3_l4_iclk");\r
1627     if ((s->cm_clksel_core & 0xc) == 0x4)\r
1628         omap_clk_setrate(l4_iclk, 1, 1);\r
1629     else if ((s->cm_clksel_core & 0xc) == 0x8)\r
1630         omap_clk_setrate(l4_iclk, 2, 1);\r
1631 }\r
1632 \r
1633 static inline void omap3_cm_per_gptimer_update(struct omap3_cm_s *s)\r
1634 {\r
1635     uint32_t cm_clksel_per = s->cm_clksel_per;\r
1636 \r
1637     if (cm_clksel_per & 0x1)\r
1638         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp2_fclk"),\r
1639                           omap_findclk(s->mpu, "omap3_sys_clk"));\r
1640     else\r
1641         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp2_fclk"),\r
1642                           omap_findclk(s->mpu, "omap3_32k_fclk"));\r
1643     omap_gp_timer_change_clk(s->mpu->gptimer[1]);\r
1644 \r
1645     if (cm_clksel_per & 0x2)\r
1646         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp3_fclk"),\r
1647                           omap_findclk(s->mpu, "omap3_sys_clk"));\r
1648     else\r
1649         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp3_fclk"),\r
1650                           omap_findclk(s->mpu, "omap3_32k_fclk"));\r
1651     omap_gp_timer_change_clk(s->mpu->gptimer[2]);\r
1652 \r
1653     if (cm_clksel_per & 0x4)\r
1654         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp4_fclk"),\r
1655                           omap_findclk(s->mpu, "omap3_sys_clk"));\r
1656     else\r
1657         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp4_fclk"),\r
1658                           omap_findclk(s->mpu, "omap3_32k_fclk"));\r
1659     omap_gp_timer_change_clk(s->mpu->gptimer[3]);\r
1660 \r
1661     if (cm_clksel_per & 0x8)\r
1662         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp5_fclk"),\r
1663                           omap_findclk(s->mpu, "omap3_sys_clk"));\r
1664     else\r
1665         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp5_fclk"),\r
1666                           omap_findclk(s->mpu, "omap3_32k_fclk"));\r
1667     omap_gp_timer_change_clk(s->mpu->gptimer[4]);\r
1668 \r
1669     if (cm_clksel_per & 0x10)\r
1670         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp6_fclk"),\r
1671                           omap_findclk(s->mpu, "omap3_sys_clk"));\r
1672     else\r
1673         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp6_fclk"),\r
1674                           omap_findclk(s->mpu, "omap3_32k_fclk"));\r
1675     omap_gp_timer_change_clk(s->mpu->gptimer[5]);\r
1676     \r
1677     if (cm_clksel_per & 0x20)\r
1678         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp7_fclk"),\r
1679                           omap_findclk(s->mpu, "omap3_sys_clk"));\r
1680     else\r
1681         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp7_fclk"),\r
1682                           omap_findclk(s->mpu, "omap3_32k_fclk"));\r
1683     omap_gp_timer_change_clk(s->mpu->gptimer[6]);\r
1684 \r
1685 \r
1686     if (cm_clksel_per & 0x40)\r
1687         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp8_fclk"),\r
1688                           omap_findclk(s->mpu, "omap3_sys_clk"));\r
1689     else\r
1690         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp8_fclk"),\r
1691                           omap_findclk(s->mpu, "omap3_32k_fclk"));\r
1692     omap_gp_timer_change_clk(s->mpu->gptimer[7]);\r
1693     \r
1694     if (cm_clksel_per & 0x80)\r
1695         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp9_fclk"),\r
1696                           omap_findclk(s->mpu, "omap3_sys_clk"));\r
1697     else\r
1698         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp9_fclk"),\r
1699                           omap_findclk(s->mpu, "omap3_32k_fclk"));\r
1700     omap_gp_timer_change_clk(s->mpu->gptimer[8]);\r
1701 \r
1702     /*TODO:Tell GPTIMER to generate new clk rate */\r
1703     OMAP3_DEBUG(("omap3_gp2_fclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp2_fclk"))));\r
1704     OMAP3_DEBUG(("omap3_gp3_fclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp3_fclk"))));\r
1705         OMAP3_DEBUG(("omap3_gp4_fclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp4_fclk"))));\r
1706     OMAP3_DEBUG(("omap3_gp5_fclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp5_fclk"))));\r
1707     OMAP3_DEBUG(("omap3_gp6_fclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp6_fclk"))));\r
1708     OMAP3_DEBUG(("omap3_gp7_fclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp7_fclk"))));\r
1709     OMAP3_DEBUG(("omap3_gp8_fclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp8_fclk"))));\r
1710     OMAP3_DEBUG(("omap3_gp9_fclk %lld \n",omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp9_fclk"))));\r
1711 }\r
1712 \r
1713 static inline void omap3_cm_clkout2_update(struct omap3_cm_s *s)\r
1714 {\r
1715         uint32 divor;\r
1716         \r
1717         if (!s->cm_clkout_ctrl&0x80)\r
1718                 return;\r
1719 \r
1720         switch (s->cm_clkout_ctrl&0x3)\r
1721         {\r
1722                 case 0x0:\r
1723                         omap_clk_reparent(omap_findclk(s->mpu, "omap3_sys_clkout2"),\r
1724                           omap_findclk(s->mpu, "omap3_core_clk"));\r
1725                         break;\r
1726                 case 0x1:\r
1727                         omap_clk_reparent(omap_findclk(s->mpu, "omap3_sys_clkout2"),\r
1728                           omap_findclk(s->mpu, "omap3_sys_clk"));\r
1729                         break;\r
1730                 case 0x2:\r
1731                         omap_clk_reparent(omap_findclk(s->mpu, "omap3_sys_clkout2"),\r
1732                           omap_findclk(s->mpu, "omap3_96m_fclk"));\r
1733                         break;\r
1734                 case 0x3:\r
1735                         omap_clk_reparent(omap_findclk(s->mpu, "omap3_sys_clkout2"),\r
1736                           omap_findclk(s->mpu, "omap3_54m_fclk"));\r
1737                         break;\r
1738         }\r
1739 \r
1740         divor = (s->cm_clkout_ctrl&0x31)>>3;\r
1741         divor = 1<<divor;\r
1742         omap_clk_setrate(omap_findclk(s->mpu, "omap3_sys_clkout2"), divor, 1);\r
1743         \r
1744 }\r
1745 \r
1746 static void omap3_cm_reset(struct omap3_cm_s *s)\r
1747 {\r
1748     s->cm_fclken_iva2 = 0x0;\r
1749     s->cm_clken_pll_iva2 = 0x11;\r
1750     s->cm_idlest_iva2 = 0x1;\r
1751     s->cm_idlest_pll_iva2 = 0x0;\r
1752     s->cm_autoidle_pll_iva2 = 0x0;\r
1753     s->cm_clksel1_pll_iva2 = 0x80000;\r
1754     s->cm_clksel2_pll_iva2 = 0x1;\r
1755     s->cm_clkstctrl_iva2 = 0x0;\r
1756     s->cm_clkstst_iva2 = 0x0;\r
1757 \r
1758     s->cm_revision = 0x10;\r
1759     s->cm_sysconfig = 0x1;\r
1760 \r
1761     s->cm_clken_pll_mpu = 0x15;\r
1762     s->cm_idlest_mpu = 0x1;\r
1763     s->cm_idlest_pll_mpu = 0x0;\r
1764     s->cm_autoidle_pll_mpu = 0x0;\r
1765     s->cm_clksel1_pll_mpu = 0x80000;\r
1766     s->cm_clksel2_pll_mpu = 0x1;\r
1767     s->cm_clkstctrl_mpu = 0x0;\r
1768     s->cm_clkstst_mpu = 0x0;\r
1769 \r
1770     s->cm_fclken1_core = 0x0;\r
1771     s->cm_fclken3_core = 0x0;\r
1772     s->cm_iclken1_core = 0x42;\r
1773     s->cm_iclken2_core = 0x0;\r
1774     s->cm_iclken3_core = 0x0;\r
1775     /*allow access to devices*/\r
1776     s->cm_idlest1_core = 0x0;\r
1777     s->cm_idlest2_core = 0x0;\r
1778     /*ide status =0 */\r
1779     s->cm_idlest3_core = 0xa; \r
1780     s->cm_autoidle1_core = 0x0;\r
1781     s->cm_autoidle2_core = 0x0;\r
1782     s->cm_autoidle3_core = 0x0;\r
1783     s->cm_clksel_core = 0x105;\r
1784     s->cm_clkstctrl_core = 0x0;\r
1785     s->cm_clkstst_core = 0x0;\r
1786 \r
1787     s->cm_fclken_sgx = 0x0;\r
1788     s->cm_iclken_sgx = 0x0;\r
1789     s->cm_idlest_sgx = 0x1;\r
1790     s->cm_clksel_sgx = 0x0;\r
1791     s->cm_sleepdep_sgx = 0x0;\r
1792     s->cm_clkstctrl_sgx = 0x0;\r
1793     s->cm_clkstst_sgx = 0x0;\r
1794 \r
1795     s->cm_fclken_wkup = 0x0;\r
1796     s->cm_iclken_wkup = 0x0;\r
1797     /*assume all clock can be accessed*/\r
1798     s->cm_idlest_wkup = 0x0;\r
1799     s->cm_autoidle_wkup = 0x0;\r
1800     s->cm_clksel_wkup = 0x12;\r
1801 \r
1802     s->cm_clken_pll = 0x110015;\r
1803     s->cm_clken2_pll = 0x11;\r
1804     s->cm_idlest_ckgen = 0x0;\r
1805     s->cm_idlest2_ckgen = 0x0;\r
1806     s->cm_autoidle_pll = 0x0;\r
1807     s->cm_autoidle2_pll = 0x0;\r
1808     s->cm_clksel1_pll = 0x8000040;\r
1809     s->cm_clksel2_pll = 0x0;\r
1810     s->cm_clksel3_pll = 0x1;\r
1811     s->cm_clksel4_pll = 0x0;\r
1812     s->cm_clksel5_pll = 0x1;\r
1813     s->cm_clkout_ctrl = 0x3;\r
1814 \r
1815 \r
1816     s->cm_fclken_dss = 0x0;\r
1817     s->cm_iclken_dss = 0x0;\r
1818     /*dss can be accessed*/\r
1819     s->cm_idlest_dss = 0x0;\r
1820     s->cm_autoidle_dss = 0x0;\r
1821     s->cm_clksel_dss = 0x1010;\r
1822     s->cm_sleepdep_dss = 0x0;\r
1823     s->cm_clkstctrl_dss = 0x0;\r
1824     s->cm_clkstst_dss = 0x0;\r
1825 \r
1826     s->cm_fclken_cam = 0x0;\r
1827     s->cm_iclken_cam = 0x0;\r
1828     s->cm_idlest_cam = 0x1;\r
1829     s->cm_autoidle_cam = 0x0;\r
1830     s->cm_clksel_cam = 0x10;\r
1831     s->cm_sleepdep_cam = 0x0;\r
1832     s->cm_clkstctrl_cam = 0x0;\r
1833     s->cm_clkstst_cam = 0x0;\r
1834 \r
1835     s->cm_fclken_per = 0x0;\r
1836     s->cm_iclken_per = 0x0;\r
1837     //s->cm_idlest_per = 0x3ffff;\r
1838     s->cm_idlest_per = 0x0; //enable GPIO access\r
1839     s->cm_autoidle_per = 0x0;\r
1840     s->cm_clksel_per = 0x0;\r
1841     s->cm_sleepdep_per = 0x0;\r
1842     s->cm_clkstctrl_per = 0x0;\r
1843     s->cm_clkstst_per = 0x0;\r
1844 \r
1845     s->cm_clksel1_emu = 0x10100a50;\r
1846     s->cm_clkstctrl_emu = 0x2;\r
1847     s->cm_clkstst_emu = 0x0;\r
1848     s->cm_clksel2_emu = 0x0;\r
1849     s->cm_clksel3_emu = 0x0;\r
1850 \r
1851     s->cm_polctrl = 0x0;\r
1852 \r
1853     s->cm_idlest_neon = 0x1;\r
1854     s->cm_clkstctrl_neon = 0x0;\r
1855 \r
1856     s->cm_fclken_usbhost = 0x0;\r
1857     s->cm_iclken_usbhost = 0x0;\r
1858     s->cm_idlest_usbhost = 0x3;\r
1859     s->cm_autoidle_usbhost = 0x0;\r
1860     s->cm_sleepdep_usbhost = 0x0;\r
1861     s->cm_clkstctrl_usbhost = 0x0;\r
1862     s->cm_clkstst_usbhost = 0x0;\r
1863 }\r
1864 \r
1865 static uint32_t omap3_cm_read(void *opaque, target_phys_addr_t addr)\r
1866 {\r
1867     struct omap3_cm_s *s = (struct omap3_cm_s *) opaque;\r
1868     uint32_t ret;\r
1869     uint32_t bypass = 0, m;\r
1870 \r
1871     switch (addr)\r
1872     {\r
1873     case 0x0:\r
1874         return s->cm_fclken_iva2;\r
1875     case 0x04:\r
1876         return s->cm_clken_pll_iva2;\r
1877     case 0x20:\r
1878         return s->cm_idlest_iva2;\r
1879     case 0x24:\r
1880         if (((s->cm_clken_pll_iva2 & 0x7) == 0x5)\r
1881             || ((s->cm_clken_pll_iva2 & 0x7) == 0x1))\r
1882         {\r
1883             bypass = 1;\r
1884         }\r
1885         else if ((s->cm_clken_pll_iva2 & 0x7) == 0x7)\r
1886         {\r
1887             m = (s->cm_clksel1_pll_iva2 & 0x7ff00) >> 8;\r
1888             if ((m == 0) || (m == 1))\r
1889                 bypass = 1;\r
1890             else\r
1891                 bypass = 0;\r
1892         }\r
1893         if (bypass)\r
1894             return 0;\r
1895         else\r
1896             return 1;\r
1897     case 0x34:\r
1898         return s->cm_autoidle_pll_iva2;\r
1899     case 0x40:\r
1900         return s->cm_clksel1_pll_iva2;\r
1901     case 0x44:\r
1902         return s->cm_clksel2_pll_iva2;\r
1903     case 0x48:\r
1904         return s->cm_clkstctrl_iva2;\r
1905     case 0x4c:\r
1906         return s->cm_clkstst_iva2;\r
1907 \r
1908    case 0x800:\r
1909                 return s->cm_revision;\r
1910         case 0x810:\r
1911                 return s->cm_sysconfig;\r
1912 \r
1913         \r
1914     case 0x904:                /*CM_CLKEN_PLL_MPU */\r
1915         return s->cm_clken_pll_mpu;\r
1916    case 0x920:\r
1917                 return s->cm_idlest_mpu & 0x0;  /*MPU is active*/\r
1918     case 0x924:\r
1919         if ((s->cm_clken_pll_mpu & 0x7) == 0x5)\r
1920         {\r
1921             bypass = 1;\r
1922         }\r
1923         else if ((s->cm_clken_pll_mpu & 0x7) == 0x7)\r
1924         {\r
1925             m = (s->cm_clksel1_pll_mpu & 0x7ff00) >> 8;\r
1926             if ((m == 0) || (m == 1))\r
1927                 bypass = 1;\r
1928             else\r
1929                 bypass = 0;\r
1930         }\r
1931         if (bypass)\r
1932             return 0;\r
1933         else\r
1934             return 1;\r
1935     case 0x934:\r
1936         return s->cm_autoidle_pll_mpu;\r
1937     case 0x940:\r
1938         return s->cm_clksel1_pll_mpu;\r
1939     case 0x944:\r
1940         return s->cm_clksel2_pll_mpu;\r
1941      case 0x948:\r
1942         return s->cm_clkstctrl_mpu;\r
1943      case 0x94c:\r
1944         return s->cm_clkstst_mpu;\r
1945 \r
1946 \r
1947         \r
1948     case 0xa00:\r
1949         return s->cm_fclken1_core;\r
1950     case 0xa08:\r
1951         return s->cm_fclken3_core;\r
1952     case 0xa10:\r
1953         return s->cm_iclken1_core;\r
1954     case 0xa14:\r
1955          return s->cm_iclken2_core;\r
1956     case 0xa20:\r
1957         return s->cm_idlest1_core;\r
1958     case 0xa24:\r
1959         return s->cm_idlest2_core;\r
1960     case 0xa28:\r
1961         return s->cm_idlest3_core;\r
1962     case 0xa30:\r
1963         return s->cm_autoidle1_core;\r
1964     case 0xa34:\r
1965         return s->cm_autoidle2_core;\r
1966     case 0xa38:\r
1967         return s->cm_autoidle3_core;\r
1968     case 0xa40:                /*CM_CLKSEL_CORE */\r
1969         return s->cm_clksel_core;\r
1970     case 0xa48:\r
1971          return s->cm_clkstctrl_core;\r
1972      case 0xa4c:\r
1973         return s->cm_clkstst_core;\r
1974 \r
1975    case 0xb00:\r
1976                 return s->cm_fclken_sgx;\r
1977         case 0xb10:\r
1978                 return s->cm_iclken_sgx;\r
1979         case 0xb20:\r
1980                 return s->cm_idlest_sgx&0x0;\r
1981    case 0xb40:                /*CM_CLKSEL_SGX */\r
1982         return s->cm_clksel_sgx;\r
1983    case 0xb48:\r
1984                 return s->cm_clkstctrl_sgx;\r
1985         case 0xb4c:\r
1986                 return s->cm_clkstst_sgx;\r
1987 \r
1988                 \r
1989     case 0xc00:                /*CM_FCLKEN_WKUP */\r
1990         return s->cm_fclken_wkup;\r
1991     case 0xc10:                /*CM_ICLKEN_WKUP */\r
1992         return s->cm_iclken_wkup;\r
1993     case 0xc20:                /*CM_IDLEST_WKUP */\r
1994         /*TODO: Check whether the timer can be accessed. */\r
1995         return 0x0;\r
1996     case 0xc30:\r
1997         return s->cm_idlest_wkup;\r
1998     case 0xc40:\r
1999         return s->cm_clksel_wkup;\r
2000     case 0xc48:\r
2001         return s->cm_c48;\r
2002 \r
2003         \r
2004     case 0xd00:                /*CM_CLKEN_PLL */\r
2005         return s->cm_clken_pll;\r
2006     case 0xd04:\r
2007         return s->cm_clken2_pll;\r
2008     case 0xd20:\r
2009          /*FIXME: all clock is active. we do not care it. */\r
2010         ret = 0x3ffff;\r
2011 \r
2012         /*DPLL3*/\r
2013         bypass = 0;\r
2014         if (((s->cm_clken_pll & 0x7) == 0x5) || ((s->cm_clken_pll & 0x7) == 0x6))\r
2015                 bypass = 1;\r
2016         else if ((s->cm_clken_pll & 0x7) == 0x7) {\r
2017             m = (s->cm_clksel1_pll & 0x7ff0000) >> 16;\r
2018             if ((m == 0) || (m == 1))\r
2019                 bypass = 1;\r
2020             else\r
2021                 bypass = 0;\r
2022         }\r
2023         if (bypass)\r
2024             ret &= 0xfffe;\r
2025         \r
2026         /*DPLL4*/\r
2027             bypass = 0;\r
2028             if ((s->cm_clken_pll & 0x70000) == 0x10000)\r
2029             bypass = 1;\r
2030         else if ((s->cm_clken_pll & 0x70000) == 0x70000) {\r
2031             m = (s->cm_clksel2_pll & 0x7ff00) >> 8;\r
2032             if ((m == 0) || (m == 1))\r
2033                 bypass = 1;\r
2034             else\r
2035                 bypass = 0;\r
2036         }\r
2037         if (bypass)\r
2038             ret &= 0xfffd;\r
2039         return ret;\r
2040         \r
2041     case 0xd24:\r
2042         return s->cm_idlest2_ckgen;\r
2043     case 0xd30:\r
2044         return s->cm_autoidle_pll;\r
2045     case 0xd34:\r
2046         return s->cm_autoidle2_pll;\r
2047     case 0xd40:                /*CM_CLKSEL1_PLL */\r
2048         return s->cm_clksel1_pll;\r
2049     case 0xd44:\r
2050         return s->cm_clksel2_pll;\r
2051     case 0xd48:                /*CM_CLKSEL3_PLL */\r
2052         return s->cm_clksel3_pll;\r
2053     case 0xd4c:\r
2054         return s->cm_clksel4_pll;\r
2055     case 0xd50:                /*CM_CLKSEL5_PLL */\r
2056         return s->cm_clksel5_pll;\r
2057     case 0xd70:\r
2058          return s->cm_clkout_ctrl;\r
2059 \r
2060          \r
2061     case 0xe00:\r
2062         return s->cm_fclken_dss;\r
2063         case 0xe10:\r
2064         return s->cm_iclken_dss;\r
2065     case 0xe20:\r
2066         return s->cm_idlest_dss;\r
2067     case 0xe30:\r
2068         return s->cm_autoidle_dss;\r
2069     case 0xe40:\r
2070         return s->cm_clksel_dss;\r
2071     case 0xe44:\r
2072         return s->cm_sleepdep_dss;\r
2073     case 0xe48:\r
2074         return s->cm_clkstctrl_dss;\r
2075     case 0xe4c:\r
2076         return s->cm_clkstst_dss;\r
2077 \r
2078         \r
2079     case 0xf00:\r
2080         return s->cm_fclken_cam;\r
2081     case 0xf10:\r
2082         return s->cm_iclken_cam;\r
2083     case 0xf20:\r
2084         return s->cm_idlest_cam&0x0;\r
2085     case 0xf30:\r
2086         return s->cm_autoidle_cam;\r
2087     case 0xf40:\r
2088         return s->cm_clksel_cam;\r
2089     case 0xf44:\r
2090         return s->cm_sleepdep_cam;\r
2091     case 0xf48:\r
2092         return s->cm_clkstctrl_cam;\r
2093     case 0xf4c:\r
2094         return s->cm_clkstst_cam;\r
2095 \r
2096         \r
2097     case 0x1000:\r
2098         return s->cm_fclken_per;\r
2099     case 0x1010:\r
2100         return s->cm_iclken_per;\r
2101     case 0x1020:\r
2102         return s->cm_idlest_per ;\r
2103     case 0x1030:\r
2104         return s->cm_autoidle_per;\r
2105     case 0x1040:\r
2106         return s->cm_clksel_per;\r
2107     case 0x1044:\r
2108         return s->cm_sleepdep_per;\r
2109     case 0x1048:\r
2110         return s->cm_clkstctrl_per;\r
2111     case 0x104c:\r
2112                 return s->cm_clkstst_per;\r
2113 \r
2114         \r
2115     case 0x1140:               /*CM_CLKSEL1_EMU */\r
2116         return s->cm_clksel1_emu;\r
2117     case 0x1148:\r
2118          return s->cm_clkstctrl_emu;\r
2119     case 0x114c:\r
2120         return s->cm_clkstst_emu&0x0;\r
2121     case 0x1150:\r
2122         return s->cm_clksel2_emu;\r
2123     case 0x1154:\r
2124         return s->cm_clksel3_emu;\r
2125 \r
2126    case 0x129c:\r
2127                 return s->cm_polctrl;\r
2128 \r
2129         case 0x1320:\r
2130                 return s->cm_idlest_neon&0x0;\r
2131         case 0x1348:\r
2132                 return s->cm_clkstctrl_neon;\r
2133 \r
2134         case 0x1400:\r
2135                 return s->cm_fclken_usbhost;\r
2136         case 0x1410:\r
2137                 return s->cm_iclken_usbhost;\r
2138         case 0x1420:\r
2139                 return s->cm_idlest_usbhost&0x0;\r
2140     case 0x1430:\r
2141         return s->cm_autoidle_usbhost;\r
2142     case 0x1444:\r
2143         return s->cm_sleepdep_usbhost;\r
2144     case 0x1448:\r
2145         return s->cm_clkstctrl_usbhost;\r
2146     case 0x144c:\r
2147         return s->cm_clkstst_usbhost;\r
2148 \r
2149     default:\r
2150         printf("omap3_cm_read addr %x pc %x \n", addr, cpu_single_env->regs[15] );\r
2151         exit(-1);\r
2152     }\r
2153 }\r
2154 \r
2155 \r
2156 static void omap3_cm_write(void *opaque, target_phys_addr_t addr,\r
2157                            uint32_t value)\r
2158 {\r
2159     struct omap3_cm_s *s = (struct omap3_cm_s *) opaque;\r
2160 \r
2161     switch (addr)\r
2162     {\r
2163     case 0x20:\r
2164     case 0x24:\r
2165     case 0x4c:\r
2166     case 0x800:\r
2167     case 0x920:\r
2168     case 0x924:\r
2169     case 0x94c:\r
2170     case 0xa20:\r
2171     case 0xa24:\r
2172     case 0xa28:\r
2173     case 0xa4c:\r
2174     case 0xb20:\r
2175     case 0xb4c:\r
2176     case 0xc20:                /*CM_IDLEST_WKUP */\r
2177     case 0xd20:\r
2178     case 0xd24:\r
2179     case 0xe20:\r
2180     case 0xe4c:\r
2181     case 0xf20:\r
2182     case 0xf4c:\r
2183     case 0x1020:\r
2184     case 0x104c:\r
2185     case 0x114c:\r
2186     case 0x1320:\r
2187     case 0x1420:\r
2188     case 0x144c:\r
2189         OMAP_RO_REG(addr);\r
2190         exit(-1);\r
2191         break;\r
2192         \r
2193     case 0x0:\r
2194         s->cm_fclken_iva2 = value & 0x1;\r
2195         break;\r
2196     case 0x4:                  /*CM_CLKEN_PLL_IVA2 */\r
2197         s->cm_clken_pll_iva2 = value & 0x7ff;\r
2198         omap3_cm_iva2_update(s);\r
2199         break;\r
2200     case 0x34:\r
2201         s->cm_autoidle_pll_iva2 = value & 0x7;\r
2202         break;\r
2203     case 0x40:\r
2204         s->cm_clksel1_pll_iva2 = value & 0x3fff7f;\r
2205         //printf("value %x s->cm_clksel1_pll_iva2 %x \n",value,s->cm_clksel1_pll_iva2);\r
2206         omap3_cm_iva2_update(s);\r
2207         break;\r
2208     case 0x44:\r
2209         s->cm_clksel2_pll_iva2 = value & 0x1f;\r
2210         omap3_cm_iva2_update(s);\r
2211         break;\r
2212     case 0x48:\r
2213         s->cm_clkstctrl_iva2 = value& 0x3;\r
2214         break;\r
2215 \r
2216     case 0x810:\r
2217         s->cm_sysconfig = value & 0x1;\r
2218         break;\r
2219 \r
2220         \r
2221     case 0x904:                /*CM_CLKEN_PLL_MPU */\r
2222         s->cm_clken_pll_mpu = value & 0x7ff;\r
2223         omap3_cm_mpu_update(s);\r
2224         break;\r
2225     case 0x934:\r
2226         s->cm_autoidle_pll_mpu = value & 0x7;\r
2227         break;\r
2228     case 0x940:\r
2229         //printf("s->cm_clksel1_pll_mpu  %x\n",s->cm_clksel1_pll_mpu );\r
2230         s->cm_clksel1_pll_mpu = value & 0x3fff7f;\r
2231         omap3_cm_mpu_update(s);\r
2232         break;\r
2233     case 0x944:\r
2234         s->cm_clksel2_pll_mpu = value & 0x1f;\r
2235         omap3_cm_mpu_update(s);\r
2236         break;\r
2237     case 0x948:\r
2238         s->cm_clkstctrl_mpu = value & 0x3;\r
2239         break;\r
2240 \r
2241         \r
2242     case 0xa00:\r
2243         s->cm_fclken1_core = value & 0x43fffe00;\r
2244          break;\r
2245     case 0xa08:\r
2246          s->cm_fclken3_core = value & 0x7;\r
2247          break;\r
2248     case 0xa10:\r
2249         s->cm_iclken1_core = value & 0x7ffffed2;\r
2250          break;\r
2251     case 0xa14:\r
2252          s->cm_iclken2_core = value & 0x1f;\r
2253          break;\r
2254     case 0xa18:\r
2255         s->cm_iclken3_core = value & 0x2;\r
2256         break;\r
2257     case 0xa30:\r
2258         s->cm_autoidle1_core = value & 0x7ffffed0;\r
2259         break;\r
2260     case 0xa34:\r
2261         s->cm_autoidle2_core = value & 0x1f;\r
2262         break;\r
2263     case 0xa38:\r
2264         s->cm_autoidle3_core = value & 0x2;\r
2265         break;\r
2266     case 0xa40:                /*CM_CLKSEL_CORE */\r
2267         s->cm_clksel_core = (value & 0xff);\r
2268         s->cm_clksel_core |= 0x100;\r
2269         omap3_cm_gp10_update(s);\r
2270         omap3_cm_gp11_update(s);\r
2271         omap3_cm_l3clk_update(s);\r
2272         omap3_cm_l4clk_update(s);\r
2273         break;\r
2274     case 0xa48:\r
2275         s->cm_clkstctrl_core = value & 0xf;\r
2276         break;\r
2277 \r
2278     case 0xb00:\r
2279         s->cm_fclken_sgx = value &0x2;\r
2280         break;\r
2281     case 0xb10:\r
2282         s->cm_iclken_sgx = value & 0x1;\r
2283         break;\r
2284     case 0xb40:                /*CM_CLKSEL_SGX */\r
2285         /*TODO: SGX Clock!! */\r
2286         s->cm_clksel_sgx = value;\r
2287         break;\r
2288     case 0xb44:\r
2289         s->cm_sleepdep_sgx = value &0x2;\r
2290         break;\r
2291     case 0xb48:\r
2292         s->cm_clkstctrl_sgx = value & 0x3;\r
2293         break;\r
2294 \r
2295     \r
2296     case 0xc00:                /*CM_FCLKEN_WKUP */\r
2297         s->cm_fclken_wkup = value & 0x2e9;\r
2298         break;\r
2299     case 0xc10:                /*CM_ICLKEN_WKUP */\r
2300         s->cm_iclken_wkup = value & 0x2ff;\r
2301         break;\r
2302     case 0xc30:\r
2303         s->cm_autoidle_wkup = value & 0x23f;\r
2304         break;\r
2305     case 0xc40:                /*CM_CLKSEL_WKUP */\r
2306         s->cm_clksel_wkup = value & 0x7f;\r
2307         omap3_cm_clksel_wkup_update(s, s->cm_clksel_wkup);\r
2308         break;\r
2309 \r
2310         \r
2311     case 0xd00:                /*CM_CLKEN_PLL */\r
2312         s->cm_clken_pll = value & 0xffff17ff;\r
2313         omap3_cm_dpll3_update(s);\r
2314         omap3_cm_dpll4_update(s);\r
2315         break;\r
2316     case 0xd04:\r
2317         s->cm_clken2_pll = value & 0x7ff;\r
2318         break;\r
2319     case 0xd30:\r
2320         s->cm_autoidle_pll = value & 0x3f;\r
2321         break;\r
2322     case 0xd34:\r
2323         s->cm_autoidle2_pll = value & 0x7;\r
2324         break;\r
2325     case 0xd40:                /*CM_CLKSEL1_PLL */\r
2326         //OMAP3_DEBUG(("WD40 value %x \n",value));\r
2327         s->cm_clksel1_pll = value & 0xffffbffc;\r
2328         //OMAP3_DEBUG(("WD40 value %x \n",value));\r
2329         omap3_cm_dpll3_update(s);\r
2330         omap3_cm_48m_update(s);\r
2331         break;\r
2332     case 0xd44:\r
2333         s->cm_clksel2_pll = value & 0x7ff7f;\r
2334         omap3_cm_dpll4_update(s);\r
2335         break;\r
2336     case 0xd48:                /*CM_CLKSEL3_PLL */\r
2337         s->cm_clksel3_pll = value & 0x1f;\r
2338         omap3_cm_dpll4_update(s);\r
2339         break;\r
2340     case 0xd4c:                /*CM_CLKSEL4_PLL */  \r
2341         s->cm_clksel4_pll = value & 0x7ff7f;\r
2342         omap3_cm_dpll5_update(s);\r
2343         break;\r
2344      case 0xd50:                /*CM_CLKSEL5_PLL */\r
2345         s->cm_clksel5_pll = value & 0x1f;\r
2346         omap3_cm_dpll5_update(s);\r
2347         break;\r
2348     case 0xd70:\r
2349         s->cm_clkout_ctrl = value & 0xbb;\r
2350         omap3_cm_clkout2_update(s);\r
2351         break;\r
2352         \r
2353     case 0xe00:\r
2354         s->cm_fclken_dss = value & 0x7;\r
2355         break;\r
2356         case 0xe10:\r
2357         s->cm_iclken_dss = value & 0x1;\r
2358         break;\r
2359     case 0xe30:\r
2360         s->cm_autoidle_dss = value & 0x1;\r
2361         break;\r
2362     case 0xe40:\r
2363         s->cm_clksel_dss = value & 0x1f1f;\r
2364         omap3_cm_dpll4_update(s);\r
2365         break;\r
2366    case 0xe44:\r
2367                 s->cm_sleepdep_dss = value & 0x7;\r
2368        break;\r
2369    case 0xe48:\r
2370                 s->cm_clkstctrl_dss = value & 0x3;\r
2371        break;\r
2372         \r
2373     case 0xf00:\r
2374         s->cm_fclken_cam = value & 0x3;\r
2375         break;\r
2376     case 0xf10:\r
2377         s->cm_iclken_cam = value & 0x1;\r
2378         break;\r
2379     case 0xf30:\r
2380         s->cm_autoidle_cam = value & 0x1;\r
2381         break;\r
2382     case 0xf40:\r
2383         s->cm_clksel_cam = value & 0x1f;\r
2384         omap3_cm_dpll4_update(s);\r
2385         break;\r
2386     case 0xf44:\r
2387         s->cm_sleepdep_cam = value & 0x2;\r
2388         break;\r
2389     case 0xf48:\r
2390         s->cm_clkstctrl_cam = value & 0x3;\r
2391         break;\r
2392    \r
2393     case 0x1000:\r
2394         s->cm_fclken_per = value & 0x3ffff;\r
2395         break;\r
2396     case 0x1010:\r
2397         s->cm_iclken_per = value & 0x3ffff;\r
2398         break;\r
2399     \r
2400     case 0x1030:\r
2401         s->cm_autoidle_per = value &0x3ffff;\r
2402         break;\r
2403     case 0x1040:\r
2404         s->cm_clksel_per = value & 0xff;\r
2405         omap3_cm_per_gptimer_update(s);\r
2406         break;\r
2407     case 0x1044:\r
2408         s->cm_sleepdep_per = value & 0x6;\r
2409         break;\r
2410     case 0x1048:\r
2411          s->cm_clkstctrl_per = value &0x7;\r
2412          break;\r
2413          \r
2414     case 0x1140:               /*CM_CLKSEL1_EMU */\r
2415         s->cm_clksel1_emu = value & 0x1f1f3fff;\r
2416         //printf("cm_clksel1_emu %x\n",s->cm_clksel1_emu);\r
2417         omap3_cm_dpll3_update(s);\r
2418         omap3_cm_dpll4_update(s);\r
2419         break;\r
2420     case 0x1148:\r
2421         s->cm_clkstctrl_emu = value & 0x3;\r
2422         break;\r
2423          case 0x1150:\r
2424                  s->cm_clksel2_emu = value & 0xfff7f;\r
2425                  omap3_cm_dpll3_update(s);\r
2426         break;\r
2427     case 0x1154:\r
2428          s->cm_clksel3_emu = value & 0xfff7f;\r
2429                  omap3_cm_dpll4_update(s);\r
2430         break;\r
2431 \r
2432     case 0x129c:\r
2433          s->cm_polctrl = value & 0x1;\r
2434          break;\r
2435 \r
2436    case 0x1348:\r
2437                 s->cm_clkstctrl_neon = value & 0x3;\r
2438                 break;\r
2439 \r
2440         case 0x1400:\r
2441                 s->cm_fclken_usbhost = value & 0x3;\r
2442                 break;\r
2443         case 0x1410:\r
2444                 s->cm_iclken_usbhost = value & 0x1;\r
2445                 break;\r
2446     case 0x1430:\r
2447         s->cm_autoidle_usbhost = value & 0x1;\r
2448         break;\r
2449     case 0x1444:\r
2450         s->cm_sleepdep_usbhost = value & 0x6;\r
2451         break;\r
2452     case 0x1448:\r
2453         s->cm_clkstctrl_usbhost = value & 0x3;\r
2454         break;\r
2455    \r
2456     default:\r
2457         printf("omap3_cm_write addr %x value %x pc %x\n", addr, value,cpu_single_env->regs[15] );\r
2458         exit(-1);\r
2459     }\r
2460 }\r
2461 \r
2462 \r
2463 \r
2464 static CPUReadMemoryFunc *omap3_cm_readfn[] = {\r
2465     omap_badwidth_read32,\r
2466     omap_badwidth_read32,\r
2467     omap3_cm_read,\r
2468 };\r
2469 \r
2470 static CPUWriteMemoryFunc *omap3_cm_writefn[] = {\r
2471     omap_badwidth_write32,\r
2472     omap_badwidth_write32,\r
2473     omap3_cm_write,\r
2474 };\r
2475 \r
2476 struct omap3_cm_s *omap3_cm_init(struct omap_target_agent_s *ta,\r
2477                                  qemu_irq mpu_int, qemu_irq dsp_int,\r
2478                                  qemu_irq iva_int, struct omap_mpu_state_s *mpu)\r
2479 {\r
2480     int iomemtype;\r
2481     struct omap3_cm_s *s = (struct omap3_cm_s *) qemu_mallocz(sizeof(*s));\r
2482 \r
2483     s->irq[0] = mpu_int;\r
2484     s->irq[1] = dsp_int;\r
2485     s->irq[2] = iva_int;\r
2486     s->mpu = mpu;\r
2487     omap3_cm_reset(s);\r
2488 \r
2489     iomemtype = l4_register_io_memory(0, omap3_cm_readfn, omap3_cm_writefn, s);\r
2490     omap_l4_attach(ta, 0, iomemtype);\r
2491     omap_l4_attach(ta, 1, iomemtype);\r
2492 \r
2493     return s;\r
2494 }\r
2495 \r
2496 #define OMAP3_SEC_WDT          1\r
2497 #define OMAP3_MPU_WDT         2\r
2498 #define OMAP3_IVA2_WDT        3\r
2499 /*omap3 watchdog timer*/\r
2500 struct omap3_wdt_s\r
2501 {\r
2502     qemu_irq irq;               /*IVA2 IRQ */\r
2503     struct omap_mpu_state_s *mpu;\r
2504     omap_clk clk;\r
2505     QEMUTimer *timer;\r
2506 \r
2507     int active;\r
2508     int64_t rate;\r
2509     int64_t time;\r
2510     //int64_t ticks_per_sec;\r
2511 \r
2512     uint32_t wd_sysconfig;\r
2513     uint32_t wd_sysstatus;\r
2514     uint32_t wisr;\r
2515     uint32_t wier;\r
2516     uint32_t wclr;\r
2517     uint32_t wcrr;\r
2518     uint32_t wldr;\r
2519     uint32_t wtgr;\r
2520     uint32_t wwps;\r
2521     uint32_t wspr;\r
2522 \r
2523     /*pre and ptv in wclr */\r
2524     uint32_t pre;\r
2525     uint32_t ptv;\r
2526     //uint32_t val;\r
2527 \r
2528     uint16_t writeh;            /* LSB */\r
2529     uint16_t readh;             /* MSB */\r
2530 \r
2531 };\r
2532 \r
2533 \r
2534 \r
2535 \r
2536 \r
2537 static inline void omap3_wdt_timer_update(struct omap3_wdt_s *wdt_timer)\r
2538 {\r
2539     int64_t expires;\r
2540     if (wdt_timer->active)\r
2541     {\r
2542         expires = muldiv64(0xffffffffll - wdt_timer->wcrr,\r
2543                            ticks_per_sec, wdt_timer->rate);\r
2544         qemu_mod_timer(wdt_timer->timer, wdt_timer->time + expires);\r
2545     }\r
2546     else\r
2547         qemu_del_timer(wdt_timer->timer);\r
2548 }\r
2549 static void omap3_wdt_clk_setup(struct omap3_wdt_s *timer)\r
2550 {\r
2551     /*TODO: Add irq as user to clk */\r
2552 }\r
2553 \r
2554 static inline uint32_t omap3_wdt_timer_read(struct omap3_wdt_s *timer)\r
2555 {\r
2556     uint64_t distance;\r
2557 \r
2558     if (timer->active)\r
2559     {\r
2560         distance = qemu_get_clock(vm_clock) - timer->time;\r
2561         distance = muldiv64(distance, timer->rate, ticks_per_sec);\r
2562 \r
2563         if (distance >= 0xffffffff - timer->wcrr)\r
2564             return 0xffffffff;\r
2565         else\r
2566             return timer->wcrr + distance;\r
2567     }\r
2568     else\r
2569         return timer->wcrr;\r
2570 }\r
2571 \r
2572 /*\r
2573 static inline void omap3_wdt_timer_sync(struct omap3_wdt_s *timer)\r
2574 {\r
2575     if (timer->active) {\r
2576         timer->val = omap3_wdt_timer_read(timer);\r
2577         timer->time = qemu_get_clock(vm_clock);\r
2578     }\r
2579 }*/\r
2580 \r
2581 static void omap3_wdt_reset(struct omap3_wdt_s *s, int wdt_index)\r
2582 {\r
2583     s->wd_sysconfig = 0x0;\r
2584     s->wd_sysstatus = 0x0;\r
2585     s->wisr = 0x0;\r
2586     s->wier = 0x0;\r
2587     s->wclr = 0x20;\r
2588     s->wcrr = 0x0;\r
2589     switch (wdt_index)\r
2590     {\r
2591     case OMAP3_MPU_WDT:\r
2592     case OMAP3_IVA2_WDT:\r
2593         s->wldr = 0xfffb0000;\r
2594         break;\r
2595     case OMAP3_SEC_WDT:\r
2596         s->wldr = 0xffa60000;\r
2597         break;\r
2598     }\r
2599     s->wtgr = 0x0;\r
2600     s->wwps = 0x0;\r
2601     s->wspr = 0x0;\r
2602 \r
2603     switch (wdt_index)\r
2604     {\r
2605     case OMAP3_SEC_WDT:\r
2606     case OMAP3_MPU_WDT:\r
2607         s->active = 1;\r
2608         break;\r
2609     case OMAP3_IVA2_WDT:\r
2610         s->active = 0;\r
2611         break;\r
2612     }\r
2613     s->pre = s->wclr & (1 << 5);\r
2614     s->ptv = (s->wclr & 0x1c) >> 2;\r
2615     s->rate = omap_clk_getrate(s->clk) >> (s->pre ? s->ptv : 0);\r
2616 \r
2617     s->active = 1;\r
2618     s->time = qemu_get_clock(vm_clock);\r
2619     omap3_wdt_timer_update(s);\r
2620 }\r
2621 \r
2622 static uint32_t omap3_wdt_read32(void *opaque, target_phys_addr_t addr,\r
2623                                  int wdt_index)\r
2624 {\r
2625     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;\r
2626 \r
2627     //uint32_t ret;\r
2628     //printf("omap3_wdt_read32 addr %x \n",addr);\r
2629     switch (addr)\r
2630     {\r
2631     case 0x10:                 /*WD_SYSCONFIG */\r
2632         return s->wd_sysconfig;\r
2633     case 0x14:                 /*WD_SYSSTATUS */\r
2634         return s->wd_sysstatus;\r
2635     case 0x18:\r
2636          /*WISR*/ return s->wisr & 0x1;\r
2637     case 0x1c:\r
2638          /*WIER*/ return s->wier & 0x1;\r
2639     case 0x24:\r
2640          /*WCLR*/ return s->wclr & 0x3c;\r
2641     case 0x28:\r
2642          /*WCRR*/ s->wcrr = omap3_wdt_timer_read(s);\r
2643         s->time = qemu_get_clock(vm_clock);\r
2644         return s->wcrr;\r
2645     case 0x2c:\r
2646          /*WLDR*/ return s->wldr;\r
2647     case 0x30:\r
2648          /*WTGR*/ return s->wtgr;\r
2649     case 0x34:\r
2650          /*WWPS*/ return s->wwps;\r
2651     case 0x48:\r
2652          /*WSPR*/ return s->wspr;\r
2653     default:\r
2654         printf("omap3_wdt_read32 addr %x \n", addr);\r
2655         exit(-1);\r
2656     }\r
2657 }\r
2658 static uint32_t omap3_mpu_wdt_read16(void *opaque, target_phys_addr_t addr)\r
2659 {\r
2660     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;\r
2661     uint32_t ret;\r
2662 \r
2663     if (addr & 2)\r
2664         return s->readh;\r
2665     else\r
2666     {\r
2667         ret = omap3_wdt_read32(opaque, addr, OMAP3_MPU_WDT);\r
2668         s->readh = ret >> 16;\r
2669         return ret & 0xffff;\r
2670     }\r
2671 }\r
2672 static uint32_t omap3_mpu_wdt_read32(void *opaque, target_phys_addr_t addr)\r
2673 {\r
2674     return omap3_wdt_read32(opaque, addr, OMAP3_MPU_WDT);\r
2675 }\r
2676 \r
2677 static void omap3_wdt_write32(void *opaque, target_phys_addr_t addr,\r
2678                               uint32_t value, int wdt_index)\r
2679 {\r
2680     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;\r
2681 \r
2682     //printf("omap3_wdt_write32 addr %x value %x \n",addr,value);\r
2683     switch (addr)\r
2684     {\r
2685     case 0x14:                 /*WD_SYSSTATUS */\r
2686     case 0x34:\r
2687          /*WWPS*/ OMAP_RO_REG(addr);\r
2688         exit(-1);\r
2689         break;\r
2690     case 0x10:                 /*WD_SYSCONFIG */\r
2691         s->wd_sysconfig = value & 0x33f;\r
2692         break;\r
2693     case 0x18:\r
2694          /*WISR*/ s->wisr = value & 0x1;\r
2695         break;\r
2696     case 0x1c:\r
2697          /*WIER*/ s->wier = value & 0x1;\r
2698         break;\r
2699     case 0x24:\r
2700          /*WCLR*/ s->wclr = value & 0x3c;\r
2701         break;\r
2702     case 0x28:\r
2703          /*WCRR*/ s->wcrr = value;\r
2704         s->time = qemu_get_clock(vm_clock);\r
2705         omap3_wdt_timer_update(s);\r
2706         break;\r
2707     case 0x2c:\r
2708          /*WLDR*/ s->wldr = value;      /*It will take effect after next overflow */\r
2709         break;\r
2710     case 0x30:\r
2711          /*WTGR*/ if (value != s->wtgr)\r
2712         {\r
2713             s->wcrr = s->wldr;\r
2714             s->pre = s->wclr & (1 << 5);\r
2715             s->ptv = (s->wclr & 0x1c) >> 2;\r
2716             s->rate = omap_clk_getrate(s->clk) >> (s->pre ? s->ptv : 0);\r
2717             s->time = qemu_get_clock(vm_clock);\r
2718             omap3_wdt_timer_update(s);\r
2719         }\r
2720         s->wtgr = value;\r
2721         break;\r
2722     case 0x48:\r
2723          /*WSPR*/\r
2724             if (((value & 0xffff) == 0x5555) && ((s->wspr & 0xffff) == 0xaaaa))\r
2725         {\r
2726             s->active = 0;\r
2727             s->wcrr = omap3_wdt_timer_read(s);\r
2728             omap3_wdt_timer_update(s);\r
2729         }\r
2730         if (((value & 0xffff) == 0x4444) && ((s->wspr & 0xffff) == 0xbbbb))\r
2731         {\r
2732             s->active = 1;\r
2733             s->time = qemu_get_clock(vm_clock);\r
2734             omap3_wdt_timer_update(s);\r
2735         }\r
2736         s->wspr = value;\r
2737         break;\r
2738     default:\r
2739         printf("omap3_wdt_write32 addr %x \n", addr);\r
2740         exit(-1);\r
2741     }\r
2742 }\r
2743 \r
2744 static void omap3_mpu_wdt_write16(void *opaque, target_phys_addr_t addr,\r
2745                                   uint32_t value)\r
2746 {\r
2747     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;\r
2748 \r
2749     if (addr & 2)\r
2750         return omap3_wdt_write32(opaque, addr, (value << 16) | s->writeh,\r
2751                                  OMAP3_MPU_WDT);\r
2752     else\r
2753         s->writeh = (uint16_t) value;\r
2754 }\r
2755 static void omap3_mpu_wdt_write32(void *opaque, target_phys_addr_t addr,\r
2756                                   uint32_t value)\r
2757 {\r
2758     omap3_wdt_write32(opaque, addr, value, OMAP3_MPU_WDT);\r
2759 }\r
2760 \r
2761 \r
2762 static CPUReadMemoryFunc *omap3_mpu_wdt_readfn[] = {\r
2763     omap_badwidth_read32,\r
2764     omap3_mpu_wdt_read16,\r
2765     omap3_mpu_wdt_read32,\r
2766 };\r
2767 \r
2768 static CPUWriteMemoryFunc *omap3_mpu_wdt_writefn[] = {\r
2769     omap_badwidth_write32,\r
2770     omap3_mpu_wdt_write16,\r
2771     omap3_mpu_wdt_write32,\r
2772 };\r
2773 \r
2774 \r
2775 \r
2776 static void omap3_mpu_wdt_timer_tick(void *opaque)\r
2777 {\r
2778     struct omap3_wdt_s *wdt_timer = (struct omap3_wdt_s *) opaque;\r
2779 \r
2780     /*TODO:Sent reset pulse to PRCM */\r
2781     wdt_timer->wcrr = wdt_timer->wldr;\r
2782 \r
2783     /*after overflow, generate the new wdt_timer->rate */\r
2784     wdt_timer->pre = wdt_timer->wclr & (1 << 5);\r
2785     wdt_timer->ptv = (wdt_timer->wclr & 0x1c) >> 2;\r
2786     wdt_timer->rate =\r
2787         omap_clk_getrate(wdt_timer->clk) >> (wdt_timer->pre ? wdt_timer->\r
2788                                              ptv : 0);\r
2789 \r
2790     wdt_timer->time = qemu_get_clock(vm_clock);\r
2791     omap3_wdt_timer_update(wdt_timer);\r
2792 }\r
2793 \r
2794 static struct omap3_wdt_s *omap3_mpu_wdt_init(struct omap_target_agent_s *ta,\r
2795                                               qemu_irq irq, omap_clk fclk,\r
2796                                               omap_clk iclk,\r
2797                                               struct omap_mpu_state_s *mpu)\r
2798 {\r
2799     int iomemtype;\r
2800     struct omap3_wdt_s *s = (struct omap3_wdt_s *) qemu_mallocz(sizeof(*s));\r
2801 \r
2802     s->irq = irq;\r
2803     s->clk = fclk;\r
2804     s->timer = qemu_new_timer(vm_clock, omap3_mpu_wdt_timer_tick, s);\r
2805 \r
2806     omap3_wdt_reset(s, OMAP3_MPU_WDT);\r
2807     if (irq != NULL)\r
2808         omap3_wdt_clk_setup(s);\r
2809 \r
2810     iomemtype = l4_register_io_memory(0, omap3_mpu_wdt_readfn,\r
2811                                       omap3_mpu_wdt_writefn, s);\r
2812     omap_l4_attach(ta, 0, iomemtype);\r
2813 \r
2814     return s;\r
2815 \r
2816 }\r
2817 \r
2818 \r
2819 /*dummy system control module*/\r
2820 struct omap3_scm_s\r
2821 {\r
2822     struct omap_mpu_state_s *mpu;\r
2823 \r
2824         uint8 interface[48];           /*0x4800 2000*/\r
2825         uint8 padconfs[576];         /*0x4800 2030*/\r
2826         uint32 general[228];            /*0x4800 2270*/\r
2827         uint8 mem_wkup[1024];     /*0x4800 2600*/\r
2828         uint8 padconfs_wkup[84]; /*0x4800 2a00*/\r
2829         uint32 general_wkup[8];    /*0x4800 2a60*/\r
2830 };\r
2831 \r
2832 #define PADCONFS_VALUE(wakeup0,wakeup1,offmode0,offmode1, \\r
2833                                                 inputenable0,inputenable1,pupd0,pupd1,muxmode0,muxmode1,offset) \\r
2834         do { \\r
2835                  *(padconfs+offset/4) = (wakeup0 <<14)|(offmode0<<9)|(inputenable0<<8)|(pupd0<<3)|(muxmode0); \\r
2836                  *(padconfs+offset/4) |= (wakeup1 <<30)|(offmode1<<25)|(inputenable1<<24)|(pupd1<<19)|(muxmode1<<16); \\r
2837 } while (0)\r
2838 \r
2839 \r
2840 static void omap3_scm_reset(struct omap3_scm_s *s)\r
2841 {\r
2842          uint32 * padconfs;\r
2843     padconfs = (uint32 *)(s->padconfs);\r
2844     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x0);\r
2845     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x4);\r
2846     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x8);\r
2847     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0xc);\r
2848     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x10);\r
2849     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x14);\r
2850     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x18);\r
2851     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x1c);\r
2852     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x20);\r
2853     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x24);\r
2854     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x28);\r
2855     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x2c);\r
2856     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x30);\r
2857     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x34);\r
2858     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x38);\r
2859     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x3c);\r
2860     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x40);\r
2861     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x44);\r
2862     PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,7,0x48);\r
2863     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x4c);\r
2864     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x50);\r
2865     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x54);\r
2866     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x58);\r
2867     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,0,0x5c);\r
2868     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x60);\r
2869     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x64);\r
2870     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x68);\r
2871     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x6c);\r
2872     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x70);\r
2873     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x74);\r
2874     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x78);\r
2875     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x7c);\r
2876     PADCONFS_VALUE(0,0,0,0,1,1,0,3,0,7,0x80);\r
2877     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x84);\r
2878     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x88);\r
2879     PADCONFS_VALUE(0,0,0,0,1,1,3,0,7,0,0x8c);\r
2880     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x90);\r
2881     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x94);\r
2882     PADCONFS_VALUE(0,0,0,0,1,1,1,0,7,0,0x98);\r
2883     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,7,0x9c);\r
2884     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0xa0);\r
2885     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0xa4);\r
2886     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0xa8);\r
2887     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xac);\r
2888     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb0);\r
2889     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb4);\r
2890     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb8);\r
2891     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xbc);\r
2892     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc0);\r
2893     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc4);\r
2894     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc8);\r
2895     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xcc);\r
2896     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd0);\r
2897     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd4);\r
2898     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd8);\r
2899     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xdc);\r
2900     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe0);\r
2901     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe4);\r
2902     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe8);\r
2903     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xec);\r
2904     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf0);\r
2905     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf4);\r
2906     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf8);\r
2907     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xfc);\r
2908     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x100);\r
2909     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x104);\r
2910     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x108);\r
2911     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x10c);\r
2912     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x110);\r
2913     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x114);\r
2914     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x118);\r
2915     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x11c);\r
2916     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x120);\r
2917     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x124);\r
2918     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x128);\r
2919     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x12c);\r
2920     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x130);\r
2921     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x134);\r
2922     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x138);\r
2923     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x13c);\r
2924     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x140);\r
2925     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x144);\r
2926     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x148);\r
2927     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x14c);\r
2928     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x150);\r
2929     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x154);\r
2930     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x158);\r
2931     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x15c);\r
2932     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x160);\r
2933     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x164);\r
2934     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x168);\r
2935     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x16c);\r
2936     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x170);\r
2937     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x174);\r
2938     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x178);\r
2939     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x17c);\r
2940     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x180);\r
2941     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x184);\r
2942     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x188);\r
2943     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x18c);\r
2944     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x190);\r
2945     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x194);\r
2946     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x198);\r
2947     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x19c);\r
2948     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x1a0);\r
2949     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1a4);\r
2950     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x1a8);\r
2951     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1ac);\r
2952     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1b0);\r
2953     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1b4);\r
2954     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1b8);\r
2955     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1bc);\r
2956     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c0);\r
2957     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c4);\r
2958     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c8);\r
2959     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1cc);\r
2960     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d0);\r
2961     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d4);\r
2962     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d8);\r
2963     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1dc);\r
2964     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e0);\r
2965     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e4);\r
2966     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e8);\r
2967     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1ec);\r
2968     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f0);\r
2969     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f4);\r
2970     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f8);\r
2971     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1fc);\r
2972     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x200);\r
2973     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x204);\r
2974     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x208);\r
2975     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x20c);\r
2976     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x210);\r
2977     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x214);\r
2978     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x218);\r
2979     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x21c);\r
2980     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x220);\r
2981     PADCONFS_VALUE(0,0,0,0,1,1,3,1,0,0,0x224);\r
2982     PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,0,0x228);\r
2983     PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,0,0x22c);\r
2984     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x230);\r
2985     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x234);\r
2986 \r
2987 \r
2988         padconfs = (uint32 *)(s->general);\r
2989         s->general[1] = 0x4000000;  /*0x4800 2274*/\r
2990         s->general[0x1c] = 0x1;  /*0x4800 22e0*/\r
2991         s->general[0x75] = 0x7fc0;  /*0x4800 2444*/\r
2992         s->general[0x76] = 0xaa;  /*0x4800 2448*/\r
2993         s->general[0x7c] = 0x2700;  /*0x4800 2460*/\r
2994         s->general[0x7d] = 0x300000;  /*0x4800 2464*/\r
2995         s->general[0x7e] = 0x300000;  /*0x4800 2468*/\r
2996         s->general[0x81] = 0xffff;  /*0x4800 2474*/\r
2997         s->general[0x82] = 0xffff;  /*0x4800 2478*/\r
2998         s->general[0x83] = 0xffff;  /*0x4800 247c*/\r
2999         s->general[0x84] = 0x6;  /*0x4800 2480*/\r
3000         s->general[0x85] = 0xffffffff;  /*0x4800 2484*/\r
3001         s->general[0x86] = 0xffff;  /*0x4800 2488*/\r
3002         s->general[0x87] = 0xffff;  /*0x4800 248c*/\r
3003         s->general[0x88] = 0x1;  /*0x4800 2490*/\r
3004         s->general[0x8b] = 0xffffffff;  /*0x4800 249c*/\r
3005         s->general[0x8c] = 0xffff;  /*0x4800 24a0*/\r
3006         s->general[0x8e] = 0xffff;  /*0x4800 24a8*/\r
3007         s->general[0x8f] = 0xffff;  /*0x4800 24ac*/\r
3008         s->general[0x91] = 0xffff;  /*0x4800 24b4*/\r
3009         s->general[0x92] = 0xffff;  /*0x4800 24b8*/\r
3010         s->general[0xac] = 0x109;  /*0x4800 2520*/\r
3011         s->general[0xb2] = 0xffff;  /*0x4800 2538*/\r
3012         s->general[0xb3] = 0xffff;  /*0x4800 253c*/\r
3013         s->general[0xb4] = 0xffff;  /*0x4800 2540*/\r
3014         PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x368);\r
3015     PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x36c);\r
3016     PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x370);\r
3017     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x374);\r
3018     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x378);\r
3019     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x37c);\r
3020     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x380);\r
3021     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x384);\r
3022     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x388);\r
3023 \r
3024     \r
3025 \r
3026         padconfs = (uint32 *)(s->padconfs_wkup);\r
3027         PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x0);\r
3028         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x4);\r
3029         PADCONFS_VALUE(0,0,0,0,1,1,3,0,0,0,0x8);\r
3030         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0xc);\r
3031         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x10);\r
3032         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x14);\r
3033         PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x18);\r
3034         PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c);\r
3035         PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x20);\r
3036         PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x24);\r
3037         PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x2c);\r
3038 \r
3039 \r
3040         s->general_wkup[0] = 0x66ff; /*0x4800 2A60*/\r
3041             \r
3042 }\r
3043 \r
3044 static uint32_t omap3_scm_read8(void *opaque, target_phys_addr_t addr)\r
3045 {\r
3046     struct omap3_scm_s *s = (struct omap3_scm_s *) opaque;\r
3047     uint8_t* temp;\r
3048         \r
3049     switch (addr) {\r
3050     case 0x00 ... 0x2f:\r
3051         return s->interface[addr];\r
3052     case 0x30 ... 0x26f:\r
3053         return s->padconfs[addr-0x30];\r
3054     case 0x270 ... 0x5ff:\r
3055         temp = (uint8_t *)s->general;\r
3056         return temp[addr-0x270];\r
3057     case 0x600 ... 0x9ff:\r
3058         return s->mem_wkup[addr-0x600];\r
3059     case 0xa00 ... 0xa5f:\r
3060         return s->padconfs_wkup[addr-0xa00];\r
3061     case 0xa60 ... 0xa7f:\r
3062         temp = (uint8_t *)s->general_wkup;\r
3063         return temp[addr-0xa60];\r
3064     /* case 0x2f0:\r
3065         return s->control_status & 0xff;\r
3066     case 0x2f1:\r
3067         return (s->control_status & 0xff00) >> 8;\r
3068     case 0x2f2:\r
3069         return (s->control_status & 0xff0000) >> 16;\r
3070     case 0x2f3:\r
3071         return (s->control_status & 0xff000000) >> 24;    */\r
3072         \r
3073     default:\r
3074         break;\r
3075     }\r
3076     printf("omap3_scm_read8 addr %x pc %x  \n", addr,cpu_single_env->regs[15] );\r
3077     return 0;\r
3078 }\r
3079 \r
3080 static uint32_t omap3_scm_read16(void *opaque, target_phys_addr_t addr)\r
3081 {\r
3082     uint32_t v;\r
3083     v = omap3_scm_read8(opaque, addr);\r
3084     v |= omap3_scm_read8(opaque, addr + 1) << 8;\r
3085     return v;\r
3086 }\r
3087 \r
3088 static uint32_t omap3_scm_read32(void *opaque, target_phys_addr_t addr)\r
3089 {\r
3090     uint32_t v;\r
3091     v = omap3_scm_read8(opaque, addr);\r
3092     v |= omap3_scm_read8(opaque, addr + 1) << 8;\r
3093     v |= omap3_scm_read8(opaque, addr + 2) << 16;\r
3094     v |= omap3_scm_read8(opaque, addr + 3) << 24;\r
3095     return v;\r
3096 }\r
3097 \r
3098 static void omap3_scm_write8(void *opaque, target_phys_addr_t addr,\r
3099                              uint32_t value)\r
3100 {\r
3101     struct omap3_scm_s *s = (struct omap3_scm_s *) opaque;\r
3102     uint8_t* temp;\r
3103 \r
3104     switch (addr)\r
3105     {\r
3106     case 0x00 ... 0x2f:\r
3107         s->interface[addr] = value;\r
3108         break;\r
3109     case 0x30 ... 0x26f:\r
3110         s->padconfs[addr-0x30] = value;\r
3111         break;\r
3112     case 0x270 ... 0x5ff:\r
3113         temp = (uint8_t *)s->general;\r
3114         temp[addr-0x270] = value;\r
3115         break;\r
3116     case 0x600 ... 0x9ff:\r
3117         s->mem_wkup[addr-0x600] = value;\r
3118         break;\r
3119     case 0xa00 ... 0xa5f:\r
3120         s->padconfs_wkup[addr-0xa00] = value;\r
3121         break;\r
3122     case 0xa60 ... 0xa7f:\r
3123         temp = (uint8_t *)s->general_wkup;\r
3124         temp[addr-0xa60] = value;\r
3125         break;\r
3126     default:\r
3127         /*we do not care scm write*/\r
3128         printf("omap3_scm_write8 addr %x pc %x \n \n", addr,\r
3129                cpu_single_env->regs[15] - 0x80008000 + 0x80e80000);\r
3130         exit(1);\r
3131         //break;\r
3132     }\r
3133 }\r
3134 \r
3135 static void omap3_scm_write16(void *opaque, target_phys_addr_t addr,\r
3136                               uint32_t value)\r
3137 {\r
3138     omap3_scm_write8(opaque, addr + 0, (value) & 0xff);\r
3139     omap3_scm_write8(opaque, addr + 1, (value >> 8) & 0xff);\r
3140 }\r
3141 \r
3142 static void omap3_scm_write32(void *opaque, target_phys_addr_t addr,\r
3143                               uint32_t value)\r
3144 {\r
3145     omap3_scm_write8(opaque, addr + 0, (value) & 0xff);\r
3146     omap3_scm_write8(opaque, addr + 1, (value >> 8) & 0xff);\r
3147     omap3_scm_write8(opaque, addr + 2, (value >> 16) & 0xff);\r
3148     omap3_scm_write8(opaque, addr + 3, (value >> 24) & 0xff);\r
3149 }\r
3150 \r
3151 static CPUReadMemoryFunc *omap3_scm_readfn[] = {\r
3152     omap3_scm_read8,\r
3153     omap3_scm_read16,\r
3154     omap3_scm_read32,\r
3155 };\r
3156 \r
3157 static CPUWriteMemoryFunc *omap3_scm_writefn[] = {\r
3158     omap3_scm_write8,\r
3159     omap3_scm_write16,\r
3160     omap3_scm_write32,\r
3161 };\r
3162 \r
3163 static struct omap3_scm_s *omap3_scm_init(struct omap_target_agent_s *ta,\r
3164                                           struct omap_mpu_state_s *mpu)\r
3165 {\r
3166     int iomemtype;\r
3167     struct omap3_scm_s *s = (struct omap3_scm_s *) qemu_mallocz(sizeof(*s));\r
3168 \r
3169     s->mpu = mpu;\r
3170 \r
3171     omap3_scm_reset(s);\r
3172 \r
3173     iomemtype = l4_register_io_memory(0, omap3_scm_readfn,\r
3174                                       omap3_scm_writefn, s);\r
3175     omap_l4_attach(ta, 0, iomemtype);\r
3176     \r
3177     return s;\r
3178 }\r
3179 \r
3180 \r
3181 /*dummy port protection*/\r
3182 struct omap3_pm_s\r
3183 {\r
3184     struct omap_mpu_state_s *mpu;\r
3185 \r
3186     uint32_t l3_pm_rt_error_log;        /*0x6801 0020 */\r
3187     uint32_t l3_pm_rt_control;  /*0x6801 0028 */\r
3188     uint32_t l3_pm_rt_error_clear_single;       /*0x6801 0030 */\r
3189     uint32_t l3_pm_rt_error_clear_multi;        /*0x6801 0038 */\r
3190     uint32_t l3_pm_rt_req_info_permission[2];   /*0x6801 0048 + (0x20*i) */\r
3191     uint32_t l3_pm_rt_read_permission[2];       /*0x6801 0050 + (0x20*i) */\r
3192     uint32_t l3_pm_rt_write_permission[2];      /*0x6801 0058 + (0x20*i) */\r
3193     uint32_t l3_pm_rt_addr_match[1];    /*0x6801 0060 + (0x20*k) */\r
3194 \r
3195     uint32_t l3_pm_gpmc_error_log;      /*0x6801 2420 */\r
3196     uint32_t l3_pm_gpmc_control;        /*0x6801 2428 */\r
3197     uint32_t l3_pm_gpmc_error_clear_single;     /*0x6801 2430 */\r
3198     uint32_t l3_pm_gpmc_error_clear_multi;      /*0x6801 2438 */\r
3199     uint32_t l3_pm_gpmc_req_info_permission[8]; /*0x6801 2448 + (0x20*i) */\r
3200     uint32_t l3_pm_gpmc_read_permission[8];     /*0x6801 2450 + (0x20*i) */\r
3201     uint32_t l3_pm_gpmc_write_permission[8];    /*0x6801 2458 + (0x20*i) */\r
3202     uint32_t l3_pm_gpmc_addr_match[7];  /*0x6801 2460 + (0x20*k) */\r
3203 \r
3204     uint32_t l3_pm_ocmram_error_log;    /*0x6801 2820 */\r
3205     uint32_t l3_pm_ocmram_control;      /*0x6801 2828 */\r
3206     uint32_t l3_pm_ocmram_error_clear_single;   /*0x6801 2830 */\r
3207     uint32_t l3_pm_ocmram_error_clear_multi;    /*0x6801 2838 */\r
3208     uint32_t l3_pm_ocmram_req_info_permission[8];       /*0x6801 2848 + (0x20*i) */\r
3209     uint32_t l3_pm_ocmram_read_permission[8];   /*0x6801 2850 + (0x20*i) */\r
3210     uint32_t l3_pm_ocmram_write_permission[8];  /*0x6801 2858 + (0x20*i) */\r
3211     uint32_t l3_pm_ocmram_addr_match[7];        /*0x6801 2860 + (0x20*k) */\r
3212 \r
3213     uint32_t l3_pm_ocmrom_error_log;    /*0x6801 2c20 */\r
3214     uint32_t l3_pm_ocmrom_control;      /*0x6801 2c28 */\r
3215     uint32_t l3_pm_ocmrom_error_clear_single;   /*0x6801 2c30 */\r
3216     uint32_t l3_pm_ocmrom_error_clear_multi;    /*0x6801 2c38 */\r
3217     uint32_t l3_pm_ocmrom_req_info_permission[2];       /*0x6801 2c48 + (0x20*i) */\r
3218     uint32_t l3_pm_ocmrom_read_permission[2];   /*0x6801 2c50 + (0x20*i) */\r
3219     uint32_t l3_pm_ocmrom_write_permission[2];  /*0x6801 2c58 + (0x20*i) */\r
3220     uint32_t l3_pm_ocmrom_addr_match[1];        /*0x6801 2c60 + (0x20*k) */\r
3221 \r
3222     uint32_t l3_pm_mad2d_error_log;     /*0x6801 3020 */\r
3223     uint32_t l3_pm_mad2d_control;       /*0x6801 3028 */\r
3224     uint32_t l3_pm_mad2d_error_clear_single;    /*0x6801 3030 */\r
3225     uint32_t l3_pm_mad2d_error_clear_multi;     /*0x6801 3038 */\r
3226     uint32_t l3_pm_mad2d_req_info_permission[8];        /*0x6801 3048 + (0x20*i) */\r
3227     uint32_t l3_pm_mad2d_read_permission[8];    /*0x6801 3050 + (0x20*i) */\r
3228     uint32_t l3_pm_mad2d_write_permission[8];   /*0x6801 3058 + (0x20*i) */\r
3229     uint32_t l3_pm_mad2d_addr_match[7]; /*0x6801 3060 + (0x20*k) */\r
3230 \r
3231     uint32_t l3_pm_iva_error_log;       /*0x6801 4020 */\r
3232     uint32_t l3_pm_iva_control; /*0x6801 4028 */\r
3233     uint32_t l3_pm_iva_error_clear_single;      /*0x6801 4030 */\r
3234     uint32_t l3_pm_iva_error_clear_multi;       /*0x6801 4038 */\r
3235     uint32_t l3_pm_iva_req_info_permission[4];  /*0x6801 4048 + (0x20*i) */\r
3236     uint32_t l3_pm_iva_read_permission[4];      /*0x6801 4050 + (0x20*i) */\r
3237     uint32_t l3_pm_iva_write_permission[4];     /*0x6801 4058 + (0x20*i) */\r
3238     uint32_t l3_pm_iva_addr_match[3];   /*0x6801 4060 + (0x20*k) */\r
3239 };\r
3240 \r
3241 static void omap3_pm_reset(struct omap3_pm_s *s)\r
3242 {\r
3243     int i;\r
3244 \r
3245     s->l3_pm_rt_control = 0x3000000;\r
3246     s->l3_pm_gpmc_control = 0x3000000;\r
3247     s->l3_pm_ocmram_control = 0x3000000;\r
3248     s->l3_pm_ocmrom_control = 0x3000000;\r
3249     s->l3_pm_mad2d_control = 0x3000000;\r
3250     s->l3_pm_iva_control = 0x3000000;\r
3251 \r
3252     s->l3_pm_rt_req_info_permission[0] = 0xffff;\r
3253     s->l3_pm_rt_req_info_permission[1] = 0x0;\r
3254     for (i = 3; i < 8; i++)\r
3255         s->l3_pm_gpmc_req_info_permission[i] = 0xffff;\r
3256     for (i = 1; i < 8; i++)\r
3257         s->l3_pm_ocmram_req_info_permission[i] = 0xffff;\r
3258     s->l3_pm_ocmrom_req_info_permission[1] = 0xffff;\r
3259     for (i = 1; i < 8; i++)\r
3260         s->l3_pm_mad2d_req_info_permission[i] = 0xffff;\r
3261     for (i = 1; i < 4; i++)\r
3262         s->l3_pm_iva_req_info_permission[i] = 0xffff;\r
3263 \r
3264     s->l3_pm_rt_read_permission[0] = 0x1406;\r
3265     s->l3_pm_rt_read_permission[1] = 0x1406;\r
3266     s->l3_pm_rt_write_permission[0] = 0x1406;\r
3267     s->l3_pm_rt_write_permission[1] = 0x1406;\r
3268     for (i = 0; i < 8; i++)\r
3269     {\r
3270         s->l3_pm_gpmc_read_permission[i] = 0x563e;\r
3271         s->l3_pm_gpmc_write_permission[i] = 0x563e;\r
3272     }\r
3273     for (i = 0; i < 8; i++)\r
3274     {\r
3275         s->l3_pm_ocmram_read_permission[i] = 0x5f3e;\r
3276         s->l3_pm_ocmram_write_permission[i] = 0x5f3e;\r
3277     }\r
3278     for (i = 0; i < 2; i++)\r
3279     {\r
3280         s->l3_pm_ocmrom_read_permission[i] = 0x1002;\r
3281         s->l3_pm_ocmrom_write_permission[i] = 0x1002;\r
3282     }\r
3283 \r
3284     for (i = 0; i < 8; i++)\r
3285     {\r
3286         s->l3_pm_mad2d_read_permission[i] = 0x5f1e;\r
3287         s->l3_pm_mad2d_write_permission[i] = 0x5f1e;\r
3288     }\r
3289 \r
3290     for (i = 0; i < 4; i++)\r
3291     {\r
3292         s->l3_pm_iva_read_permission[i] = 0x140e;\r
3293         s->l3_pm_iva_write_permission[i] = 0x140e;\r
3294     }\r
3295 \r
3296 \r
3297     s->l3_pm_rt_addr_match[0] = 0x10230;\r
3298 \r
3299     s->l3_pm_gpmc_addr_match[0] = 0x10230;\r
3300 }\r
3301 \r
3302 static uint32_t omap3_pm_read8(void *opaque, target_phys_addr_t addr)\r
3303 {\r
3304     //struct omap3_pm_s *s = (struct omap3_pm_s *) opaque;\r
3305 \r
3306     switch (addr)\r
3307     {\r
3308     default:\r
3309         printf("omap3_pm_read8 addr %x \n", addr);\r
3310         exit(-1);\r
3311     }\r
3312 }\r
3313 \r
3314 static uint32_t omap3_pm_read16(void *opaque, target_phys_addr_t addr)\r
3315 {\r
3316     uint32_t v;\r
3317     v = omap3_pm_read8(opaque, addr);\r
3318     v |= omap3_pm_read8(opaque, addr + 1) << 8;\r
3319     return v;\r
3320 }\r
3321 \r
3322 static uint32_t omap3_pm_read32(void *opaque, target_phys_addr_t addr)\r
3323 {\r
3324     uint32_t v;\r
3325     v = omap3_pm_read8(opaque, addr);\r
3326     v |= omap3_pm_read8(opaque, addr + 1) << 8;\r
3327     v |= omap3_pm_read8(opaque, addr + 2) << 16;\r
3328     v |= omap3_pm_read8(opaque, addr + 3) << 24;\r
3329     return v;\r
3330 }\r
3331 \r
3332 static void omap3_pm_write8(void *opaque, target_phys_addr_t addr,\r
3333                             uint32_t value)\r
3334 {\r
3335     struct omap3_pm_s *s = (struct omap3_pm_s *) opaque;\r
3336     int i;\r
3337 \r
3338     switch (addr)\r
3339     {\r
3340     case 0x48 ... 0x4b:\r
3341     case 0x68 ... 0x6b:\r
3342         i = (addr - 0x48) / 0x20;\r
3343         s->l3_pm_rt_req_info_permission[i] &=\r
3344             (~(0xff << ((addr - 0x48 - i * 0x20) * 8)));\r
3345         s->l3_pm_rt_req_info_permission[i] |=\r
3346             (value << (addr - 0x48 - i * 0x20) * 8);\r
3347         break;\r
3348     case 0x50 ... 0x53:\r
3349     case 0x70 ... 0x73:\r
3350         i = (addr - 0x50) / 0x20;\r
3351         s->l3_pm_rt_read_permission[i] &=\r
3352             (~(0xff << ((addr - 0x50 - i * 0x20) * 8)));\r
3353         s->l3_pm_rt_read_permission[i] |=\r
3354             (value << (addr - 0x50 - i * 0x20) * 8);\r
3355         break;\r
3356     case 0x58 ... 0x5b:\r
3357     case 0x78 ... 0x7b:\r
3358         i = (addr - 0x58) / 0x20;\r
3359         s->l3_pm_rt_write_permission[i] &=\r
3360             (~(0xff << ((addr - 0x58 - i * 0x20) * 8)));\r
3361         s->l3_pm_rt_write_permission[i] |=\r
3362             (value << (addr - 0x58 - i * 0x20) * 8);\r
3363         break;\r
3364     case 0x60 ... 0x63:\r
3365         s->l3_pm_rt_addr_match[0] &= (~(0xff << ((addr - 0x60) * 8)));\r
3366         s->l3_pm_rt_addr_match[0] |= (value << (addr - 0x60) * 8);\r
3367         break;\r
3368     case 0x2448 ... 0x244b:\r
3369     case 0x2468 ... 0x246b:\r
3370     case 0x2488 ... 0x248b:\r
3371     case 0x24a8 ... 0x24ab:\r
3372     case 0x24c8 ... 0x24cb:\r
3373     case 0x24e8 ... 0x24eb:\r
3374     case 0x2508 ... 0x250b:\r
3375     case 0x2528 ... 0x252b:\r
3376         i = (addr - 0x2448) / 0x20;\r
3377         s->l3_pm_gpmc_req_info_permission[i] &=\r
3378             (~(0xff << ((addr - 0x2448 - i * 0x20) * 8)));\r
3379         s->l3_pm_gpmc_req_info_permission[i] |=\r
3380             (value << (addr - 0x2448 - i * 0x20) * 8);\r
3381         break;\r
3382     case 0x2450 ... 0x2453:\r
3383     case 0x2470 ... 0x2473:\r
3384     case 0x2490 ... 0x2493:\r
3385     case 0x24b0 ... 0x24b3:\r
3386     case 0x24d0 ... 0x24d3:\r
3387     case 0x24f0 ... 0x24f3:\r
3388     case 0x2510 ... 0x2513:\r
3389     case 0x2530 ... 0x2533:\r
3390         i = (addr - 0x2450) / 0x20;\r
3391         s->l3_pm_gpmc_read_permission[i] &=\r
3392             (~(0xff << ((addr - 0x2450 - i * 0x20) * 8)));\r
3393         s->l3_pm_gpmc_read_permission[i] |=\r
3394             (value << (addr - 0x2450 - i * 0x20) * 8);\r
3395         break;\r
3396     case 0x2458 ... 0x245b:\r
3397     case 0x2478 ... 0x247b:\r
3398     case 0x2498 ... 0x249b:\r
3399     case 0x24b8 ... 0x24bb:\r
3400     case 0x24d8 ... 0x24db:\r
3401     case 0x24f8 ... 0x24fb:\r
3402     case 0x2518 ... 0x251b:\r
3403     case 0x2538 ... 0x253b:\r
3404         i = (addr - 0x2458) / 0x20;\r
3405         s->l3_pm_gpmc_write_permission[i] &=\r
3406             (~(0xff << ((addr - 0x2458 - i * 0x20) * 8)));\r
3407         s->l3_pm_gpmc_write_permission[i] |=\r
3408             (value << (addr - 0x2458 - i * 0x20) * 8);\r
3409         break;\r
3410     case 0x2848 ... 0x284b:\r
3411     case 0x2868 ... 0x286b:\r
3412     case 0x2888 ... 0x288b:\r
3413     case 0x28a8 ... 0x28ab:\r
3414     case 0x28c8 ... 0x28cb:\r
3415     case 0x28e8 ... 0x28eb:\r
3416     case 0x2908 ... 0x290b:\r
3417     case 0x2928 ... 0x292b:\r
3418         i = (addr - 0x2848) / 0x20;\r
3419         s->l3_pm_ocmram_req_info_permission[i] &=\r
3420             (~(0xff << ((addr - 0x2848 - i * 0x20) * 8)));\r
3421         s->l3_pm_ocmram_req_info_permission[i] |=\r
3422             (value << (addr - 0x2848 - i * 0x20) * 8);\r
3423         break;\r
3424     case 0x2850 ... 0x2853:\r
3425     case 0x2870 ... 0x2873:\r
3426     case 0x2890 ... 0x2893:\r
3427     case 0x28b0 ... 0x28b3:\r
3428     case 0x28d0 ... 0x28d3:\r
3429     case 0x28f0 ... 0x28f3:\r
3430     case 0x2910 ... 0x2913:\r
3431     case 0x2930 ... 0x2933:\r
3432         i = (addr - 0x2850) / 0x20;\r
3433         s->l3_pm_ocmram_read_permission[i] &=\r
3434             (~(0xff << ((addr - 0x2850 - i * 0x20) * 8)));\r
3435         s->l3_pm_ocmram_read_permission[i] |=\r
3436             (value << (addr - 0x2850 - i * 0x20) * 8);\r
3437         break;\r
3438     case 0x2858 ... 0x285b:\r
3439     case 0x2878 ... 0x287b:\r
3440     case 0x2898 ... 0x289b:\r
3441     case 0x28b8 ... 0x28bb:\r
3442     case 0x28d8 ... 0x28db:\r
3443     case 0x28f8 ... 0x28fb:\r
3444     case 0x2918 ... 0x291b:\r
3445     case 0x2938 ... 0x293b:\r
3446         i = (addr - 0x2858) / 0x20;\r
3447         s->l3_pm_ocmram_write_permission[i] &=\r
3448             (~(0xff << ((addr - 0x2858 - i * 0x20) * 8)));\r
3449         s->l3_pm_ocmram_write_permission[i] |=\r
3450             (value << (addr - 0x2858 - i * 0x20) * 8);\r
3451         break;\r
3452 \r
3453     case 0x2860 ... 0x2863:\r
3454     case 0x2880 ... 0x2883:\r
3455     case 0x28a0 ... 0x28a3:\r
3456     case 0x28c0 ... 0x28c3:\r
3457     case 0x28e0 ... 0x28e3:\r
3458     case 0x2900 ... 0x2903:\r
3459     case 0x2920 ... 0x2923:\r
3460         i = (addr - 0x2860) / 0x20;\r
3461         s->l3_pm_ocmram_addr_match[i] &=\r
3462             (~(0xff << ((addr - 0x2860 - i * 0x20) * 8)));\r
3463         s->l3_pm_ocmram_addr_match[i] |=\r
3464             (value << (addr - 0x2860 - i * 0x20) * 8);\r
3465         break;\r
3466 \r
3467     case 0x4048 ... 0x404b:\r
3468     case 0x4068 ... 0x406b:\r
3469     case 0x4088 ... 0x408b:\r
3470     case 0x40a8 ... 0x40ab:\r
3471         i = (addr - 0x4048) / 0x20;\r
3472         s->l3_pm_iva_req_info_permission[i] &=\r
3473             (~(0xff << ((addr - 0x4048 - i * 0x20) * 8)));\r
3474         s->l3_pm_iva_req_info_permission[i] |=\r
3475             (value << (addr - 0x4048 - i * 0x20) * 8);\r
3476         break;\r
3477     case 0x4050 ... 0x4053:\r
3478     case 0x4070 ... 0x4073:\r
3479     case 0x4090 ... 0x4093:\r
3480     case 0x40b0 ... 0x40b3:\r
3481         i = (addr - 0x4050) / 0x20;\r
3482         s->l3_pm_iva_read_permission[i] &=\r
3483             (~(0xff << ((addr - 0x4050 - i * 0x20) * 8)));\r
3484         s->l3_pm_iva_read_permission[i] |=\r
3485             (value << (addr - 0x4050 - i * 0x20) * 8);\r
3486         break;\r
3487     case 0x4058 ... 0x405b:\r
3488     case 0x4078 ... 0x407b:\r
3489     case 0x4098 ... 0x409b:\r
3490     case 0x40b8 ... 0x40bb:\r
3491         i = (addr - 0x4058) / 0x20;\r
3492         s->l3_pm_iva_write_permission[i] &=\r
3493             (~(0xff << ((addr - 0x4058 - i * 0x20) * 8)));\r
3494         s->l3_pm_iva_write_permission[i] |=\r
3495             (value << (addr - 0x4058 - i * 0x20) * 8);\r
3496         break;\r
3497     default:\r
3498         printf("omap3_pm_write8 addr %x \n", addr);\r
3499         exit(-1);\r
3500     }\r
3501 }\r
3502 \r
3503 static void omap3_pm_write16(void *opaque, target_phys_addr_t addr,\r
3504                              uint32_t value)\r
3505 {\r
3506     omap3_pm_write8(opaque, addr + 0, (value) & 0xff);\r
3507     omap3_pm_write8(opaque, addr + 1, (value >> 8) & 0xff);\r
3508 }\r
3509 \r
3510 static void omap3_pm_write32(void *opaque, target_phys_addr_t addr,\r
3511                              uint32_t value)\r
3512 {\r
3513     omap3_pm_write8(opaque, addr + 0, (value) & 0xff);\r
3514     omap3_pm_write8(opaque, addr + 1, (value >> 8) & 0xff);\r
3515     omap3_pm_write8(opaque, addr + 2, (value >> 16) & 0xff);\r
3516     omap3_pm_write8(opaque, addr + 3, (value >> 24) & 0xff);\r
3517 }\r
3518 \r
3519 static CPUReadMemoryFunc *omap3_pm_readfn[] = {\r
3520     omap3_pm_read8,\r
3521     omap3_pm_read16,\r
3522     omap3_pm_read32,\r
3523 };\r
3524 \r
3525 static CPUWriteMemoryFunc *omap3_pm_writefn[] = {\r
3526     omap3_pm_write8,\r
3527     omap3_pm_write16,\r
3528     omap3_pm_write32,\r
3529 };\r
3530 \r
3531 static struct omap3_pm_s *omap3_pm_init(struct omap_mpu_state_s *mpu)\r
3532 {\r
3533     int iomemtype;\r
3534     struct omap3_pm_s *s = (struct omap3_pm_s *) qemu_mallocz(sizeof(*s));\r
3535 \r
3536     s->mpu = mpu;\r
3537     //s->base = 0x68010000;\r
3538     //s->size = 0x4400;\r
3539 \r
3540     omap3_pm_reset(s);\r
3541 \r
3542     iomemtype = cpu_register_io_memory(0, omap3_pm_readfn, omap3_pm_writefn, s);\r
3543     cpu_register_physical_memory(0x68010000, 0x4400, iomemtype);\r
3544 \r
3545     return s;\r
3546 }\r
3547 \r
3548 /*dummy SDRAM Memory Scheduler emulation*/\r
3549 struct omap3_sms_s\r
3550 {\r
3551     struct omap_mpu_state_s *mpu;\r
3552 \r
3553     uint32 sms_sysconfig;\r
3554     uint32 sms_sysstatus;\r
3555     uint32 sms_rg_att[8];\r
3556     uint32 sms_rg_rdperm[8];\r
3557     uint32 sms_rg_wrperm[8];\r
3558     uint32 sms_rg_start[7];\r
3559     uint32 sms_rg_end[7];\r
3560     uint32 sms_security_control;\r
3561     uint32 sms_class_arbiter0;\r
3562     uint32 sms_class_arbiter1;\r
3563     uint32 sms_class_arbiter2;\r
3564     uint32 sms_interclass_arbiter;\r
3565     uint32 sms_class_rotation[3];\r
3566     uint32 sms_err_addr;\r
3567     uint32 sms_err_type;\r
3568     uint32 sms_pow_ctrl;\r
3569     uint32 sms_rot_control[12];\r
3570     uint32 sms_rot_size[12];\r
3571     uint32 sms_rot_physical_ba[12];\r
3572 \r
3573 \r
3574 };\r
3575 \r
3576 static uint32_t omap3_sms_read32(void *opaque, target_phys_addr_t addr)\r
3577 {\r
3578     struct omap3_sms_s *s = (struct omap3_sms_s *) opaque;\r
3579 \r
3580     switch (addr)\r
3581     {\r
3582     case 0x10:\r
3583         return s->sms_sysconfig;\r
3584     case 0x14:\r
3585         return s->sms_sysstatus;\r
3586     case 0x48:\r
3587     case 0x68:\r
3588     case 0x88:\r
3589     case 0xa8:\r
3590     case 0xc8:\r
3591     case 0xe8:\r
3592     case 0x108:\r
3593     case 0x128:\r
3594         return s->sms_rg_att[(addr-0x48)/0x20];\r
3595     case 0x50:\r
3596     case 0x70:\r
3597     case 0x90:\r
3598     case 0xb0:\r
3599     case 0xd0:\r
3600     case 0xf0:\r
3601     case 0x110:\r
3602     case 0x130:\r
3603         return s->sms_rg_rdperm[(addr-0x50)/0x20];\r
3604     case 0x58:\r
3605     case 0x78:\r
3606     case 0x98:\r
3607     case 0xb8:\r
3608     case 0xd8:\r
3609     case 0xf8:\r
3610     case 0x118:\r
3611         return s->sms_rg_wrperm[(addr-0x58)/0x20];\r
3612     case 0x60:\r
3613     case 0x80:\r
3614     case 0xa0:\r
3615     case 0xc0:\r
3616     case 0xe0:\r
3617     case 0x100:\r
3618     case 0x120:\r
3619         return s->sms_rg_start[(addr-0x60)/0x20];\r
3620 \r
3621     case 0x64:\r
3622     case 0x84:\r
3623     case 0xa4:\r
3624     case 0xc4:\r
3625     case 0xe4:\r
3626     case 0x104:\r
3627     case 0x124:\r
3628         return s->sms_rg_end[(addr-0x64)/0x20];\r
3629     case 0x140:\r
3630         return s->sms_security_control;\r
3631     case 0x150:\r
3632         return s->sms_class_arbiter0;\r
3633         case 0x154:\r
3634                 return s->sms_class_arbiter1;\r
3635         case 0x158:\r
3636                 return s->sms_class_arbiter2;\r
3637         case 0x160:\r
3638                 return s->sms_interclass_arbiter;\r
3639         case 0x164:\r
3640         case 0x168:\r
3641         case 0x16c:\r
3642                 return s->sms_class_rotation[(addr-0x164)/4];\r
3643         case 0x170:\r
3644                 return s->sms_err_addr;\r
3645         case 0x174:\r
3646                 return s->sms_err_type;\r
3647         case 0x178:\r
3648                 return s->sms_pow_ctrl;\r
3649         case 0x180:\r
3650         case 0x190:\r
3651         case 0x1a0:\r
3652         case 0x1b0:\r
3653         case 0x1c0:\r
3654         case 0x1d0:\r
3655         case 0x1e0:\r
3656         case 0x1f0:\r
3657         case 0x200:\r
3658         case 0x210:\r
3659         case 0x220:\r
3660         case 0x230:\r
3661                 return s->sms_rot_control[(addr-0x180)/0x10];\r
3662         case 0x184:\r
3663         case 0x194:\r
3664         case 0x1a4:\r
3665         case 0x1b4:\r
3666         case 0x1c4:\r
3667         case 0x1d4:\r
3668         case 0x1e4:\r
3669         case 0x1f4:\r
3670         case 0x204:\r
3671         case 0x214:\r
3672         case 0x224:\r
3673         case 0x234:\r
3674                 return s->sms_rot_size[(addr-0x184)/0x10];\r
3675 \r
3676         case 0x188:\r
3677         case 0x198:\r
3678         case 0x1a8:\r
3679         case 0x1b8:\r
3680         case 0x1c8:\r
3681         case 0x1d8:\r
3682         case 0x1e8:\r
3683         case 0x1f8:\r
3684         case 0x208:\r
3685         case 0x218:\r
3686         case 0x228:\r
3687         case 0x238:\r
3688                 return s->sms_rot_size[(addr-0x188)/0x10];\r
3689 \r
3690     default:\r
3691         printf("omap3_sms_read32 addr %x \n", addr);\r
3692         exit(-1);\r
3693     }\r
3694 }\r
3695 \r
3696 static void omap3_sms_write32(void *opaque, target_phys_addr_t addr,\r
3697                               uint32_t value)\r
3698 {\r
3699     struct omap3_sms_s *s = (struct omap3_sms_s *) opaque;\r
3700     //int i;\r
3701 \r
3702     switch (addr)\r
3703     {\r
3704     case 0x14:\r
3705         OMAP_RO_REG(addr);\r
3706         return;\r
3707     case 0x10:\r
3708         s->sms_sysconfig = value & 0x1f;\r
3709         break;\r
3710     \r
3711     case 0x48:\r
3712     case 0x68:\r
3713     case 0x88:\r
3714     case 0xa8:\r
3715     case 0xc8:\r
3716     case 0xe8:\r
3717     case 0x108:\r
3718     case 0x128:\r
3719         s->sms_rg_att[(addr-0x48)/0x20] = value;\r
3720         break;\r
3721     case 0x50:\r
3722     case 0x70:\r
3723     case 0x90:\r
3724     case 0xb0:\r
3725     case 0xd0:\r
3726     case 0xf0:\r
3727     case 0x110:\r
3728     case 0x130:\r
3729         s->sms_rg_rdperm[(addr-0x50)/0x20] = value&0xffff;\r
3730         break;\r
3731     case 0x58:\r
3732     case 0x78:\r
3733     case 0x98:\r
3734     case 0xb8:\r
3735     case 0xd8:\r
3736     case 0xf8:\r
3737     case 0x118:\r
3738         s->sms_rg_wrperm[(addr-0x58)/0x20] = value&0xffff;\r
3739         break;          \r
3740     case 0x60:\r
3741     case 0x80:\r
3742     case 0xa0:\r
3743     case 0xc0:\r
3744     case 0xe0:\r
3745     case 0x100:\r
3746     case 0x120:\r
3747         s->sms_rg_start[(addr-0x60)/0x20] = value;\r
3748         break;\r
3749     case 0x64:\r
3750     case 0x84:\r
3751     case 0xa4:\r
3752     case 0xc4:\r
3753     case 0xe4:\r
3754     case 0x104:\r
3755     case 0x124:\r
3756         s->sms_rg_end[(addr-0x64)/0x20] = value;\r
3757         break;\r
3758     case 0x140:\r
3759         s->sms_security_control = value &0xfffffff;\r
3760         break;\r
3761     case 0x150:\r
3762         s->sms_class_arbiter0 = value;\r
3763         break;\r
3764         case 0x154:\r
3765                 s->sms_class_arbiter1 = value;\r
3766                 break;\r
3767         case 0x158:\r
3768                 s->sms_class_arbiter2 = value;\r
3769                 break;\r
3770         case 0x160:\r
3771                 s->sms_interclass_arbiter = value;\r
3772                 break;\r
3773         case 0x164:\r
3774         case 0x168:\r
3775         case 0x16c:\r
3776                 s->sms_class_rotation[(addr-0x164)/4] = value;\r
3777                 break;\r
3778         case 0x170:\r
3779                 s->sms_err_addr = value;\r
3780                 break;\r
3781         case 0x174:\r
3782                 s->sms_err_type = value;\r
3783                 break;\r
3784         case 0x178:\r
3785                 s->sms_pow_ctrl = value;\r
3786                 break;\r
3787         case 0x180:\r
3788         case 0x190:\r
3789         case 0x1a0:\r
3790         case 0x1b0:\r
3791         case 0x1c0:\r
3792         case 0x1d0:\r
3793         case 0x1e0:\r
3794         case 0x1f0:\r
3795         case 0x200:\r
3796         case 0x210:\r
3797         case 0x220:\r
3798         case 0x230:\r
3799                 s->sms_rot_control[(addr-0x180)/0x10] = value;\r
3800                 break;\r
3801         case 0x184:\r
3802         case 0x194:\r
3803         case 0x1a4:\r
3804         case 0x1b4:\r
3805         case 0x1c4:\r
3806         case 0x1d4:\r
3807         case 0x1e4:\r
3808         case 0x1f4:\r
3809         case 0x204:\r
3810         case 0x214:\r
3811         case 0x224:\r
3812         case 0x234:\r
3813                 s->sms_rot_size[(addr-0x184)/0x10] = value;\r
3814                 break;\r
3815 \r
3816         case 0x188:\r
3817         case 0x198:\r
3818         case 0x1a8:\r
3819         case 0x1b8:\r
3820         case 0x1c8:\r
3821         case 0x1d8:\r
3822         case 0x1e8:\r
3823         case 0x1f8:\r
3824         case 0x208:\r
3825         case 0x218:\r
3826         case 0x228:\r
3827         case 0x238:\r
3828                 s->sms_rot_size[(addr-0x188)/0x10] = value;   \r
3829                 break;\r
3830         default:\r
3831         printf("omap3_sms_write32 addr %x\n", addr);\r
3832         exit(-1);\r
3833     }\r
3834 }\r
3835 \r
3836 static CPUReadMemoryFunc *omap3_sms_readfn[] = {\r
3837     omap_badwidth_read32,\r
3838     omap_badwidth_read32,\r
3839     omap3_sms_read32,\r
3840 };\r
3841 \r
3842 static CPUWriteMemoryFunc *omap3_sms_writefn[] = {\r
3843     omap_badwidth_write32,\r
3844     omap_badwidth_write32,\r
3845     omap3_sms_write32,\r
3846 };\r
3847 \r
3848 static void omap3_sms_reset(struct omap3_sms_s *s)\r
3849 {\r
3850         s->sms_sysconfig = 0x1;\r
3851         s->sms_class_arbiter0 = 0x500000;\r
3852         s->sms_class_arbiter1 = 0x500;\r
3853         s->sms_class_arbiter2 = 0x55000;\r
3854         s->sms_interclass_arbiter = 0x400040;\r
3855         s->sms_class_rotation[0] = 0x1;\r
3856         s->sms_class_rotation[1] = 0x1;\r
3857         s->sms_class_rotation[2] = 0x1;\r
3858         s->sms_pow_ctrl = 0x80;\r
3859 }\r
3860 \r
3861 static struct omap3_sms_s *omap3_sms_init(struct omap_mpu_state_s *mpu)\r
3862 {\r
3863     int iomemtype;\r
3864     struct omap3_sms_s *s = (struct omap3_sms_s *) qemu_mallocz(sizeof(*s));\r
3865 \r
3866     s->mpu = mpu;\r
3867 \r
3868     omap3_sms_reset(s);\r
3869     \r
3870     iomemtype = cpu_register_io_memory(0, omap3_sms_readfn,\r
3871                                        omap3_sms_writefn, s);\r
3872     cpu_register_physical_memory(0x6c000000, 0x10000, iomemtype);\r
3873 \r
3874     return s;\r
3875 }\r
3876 \r
3877 static const struct dma_irq_map omap3_dma_irq_map[] = {\r
3878     {0, OMAP_INT_35XX_SDMA_IRQ0},\r
3879     {0, OMAP_INT_35XX_SDMA_IRQ1},\r
3880     {0, OMAP_INT_35XX_SDMA_IRQ2},\r
3881     {0, OMAP_INT_35XX_SDMA_IRQ3},\r
3882 };\r
3883 \r
3884 static int omap3_validate_addr(struct omap_mpu_state_s *s,\r
3885                                target_phys_addr_t addr)\r
3886 {\r
3887     return 1;\r
3888 }\r
3889 \r
3890 /*\r
3891   set the kind of memory connected to GPMC that we are trying to boot form.\r
3892   Uses SYS BOOT settings.\r
3893 */\r
3894 void omap3_set_mem_type(struct omap_mpu_state_s *s,int bootfrom)\r
3895 {\r
3896         switch (bootfrom)\r
3897         {\r
3898                 case 0x0: /*GPMC_NOR*/\r
3899                         s->omap3_scm->general[32] |= 7;\r
3900                         break;\r
3901                 case 0x1: /*GPMC_NAND*/\r
3902                         s->omap3_scm->general[32] |= 1;\r
3903                         break;\r
3904                 case 0x2:\r
3905                         s->omap3_scm->general[32] |= 8;\r
3906                         break;\r
3907                 case 0x3:\r
3908                         s->omap3_scm->general[32] |= 0;\r
3909                         break;\r
3910                 case 0x4:\r
3911                         s->omap3_scm->general[32] |= 17;\r
3912                         break;\r
3913                 case 0x5:\r
3914                         s->omap3_scm->general[32] |= 3;\r
3915                         break;\r
3916         }\r
3917 }\r
3918 \r
3919 void omap3_set_device_type(struct omap_mpu_state_s *s,int device_type)\r
3920 {\r
3921         s->omap3_scm->general[32] |= (device_type & 0x7) << 8;\r
3922 }\r
3923 \r
3924 struct omap_mpu_state_s *omap3530_mpu_init(unsigned long sdram_size,\r
3925                                            DisplayState * ds, const char *core)\r
3926 {\r
3927     struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)\r
3928         qemu_mallocz(sizeof(struct omap_mpu_state_s));\r
3929     ram_addr_t sram_base, q2_base;\r
3930     qemu_irq *cpu_irq;\r
3931     qemu_irq dma_irqs[4];\r
3932     int i;\r
3933     int sdindex;\r
3934     //omap_clk gpio_clks[4];\r
3935 \r
3936 \r
3937     s->mpu_model = omap3530;\r
3938     s->env = cpu_init("cortex-a8");\r
3939     if (!s->env)\r
3940     {\r
3941         fprintf(stderr, "Unable to find CPU definition\n");\r
3942         exit(1);\r
3943     }\r
3944     s->sdram_size = sdram_size;\r
3945     s->sram_size = OMAP3530_SRAM_SIZE;\r
3946 \r
3947     sdindex = drive_get_index(IF_SD, 0, 0);\r
3948     if (sdindex == -1) {\r
3949         fprintf(stderr, "qemu: missing SecureDigital device\n");\r
3950         exit(1);\r
3951     }\r
3952 \r
3953     /* Clocks */\r
3954     omap_clk_init(s);\r
3955 \r
3956     /* Memory-mapped stuff */\r
3957 \r
3958     q2_base = qemu_ram_alloc(s->sdram_size);\r
3959     cpu_register_physical_memory(OMAP3_Q2_BASE, s->sdram_size,\r
3960                                  (q2_base | IO_MEM_RAM));\r
3961     sram_base = qemu_ram_alloc(s->sram_size);\r
3962     cpu_register_physical_memory(OMAP3_SRAM_BASE, s->sram_size,\r
3963                                  (sram_base | IO_MEM_RAM));\r
3964 \r
3965 \r
3966     \r
3967 \r
3968     s->l4 = omap_l4_init(OMAP3_L4_BASE, sizeof(omap3_l4_agent_info));\r
3969 \r
3970     cpu_irq = arm_pic_init_cpu(s->env);\r
3971     s->ih[0] = omap2_inth_init(s,\r
3972                                0x48200000, 0x1000, 3, &s->irq[0],\r
3973                                cpu_irq[ARM_PIC_CPU_IRQ],\r
3974                                cpu_irq[ARM_PIC_CPU_FIQ], omap_findclk(s,\r
3975                                                                       "omap3_mpu_intc_fclk"),\r
3976                                omap_findclk(s, "omap3_mpu_intc_iclk"));\r
3977 \r
3978     for (i = 0; i < 4; i++)\r
3979         dma_irqs[i] =\r
3980             s->irq[omap3_dma_irq_map[i].ih][omap3_dma_irq_map[i].intr];\r
3981     s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,\r
3982                             omap_findclk(s, "omap3_sdma_fclk"),\r
3983                             omap_findclk(s, "omap3_sdma_iclk"));\r
3984     s->port->addr_valid = omap3_validate_addr;\r
3985 \r
3986 \r
3987     /* Register SDRAM and SRAM ports for fast DMA transfers.  */\r
3988     soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);\r
3989     soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);\r
3990 \r
3991 \r
3992     s->omap3_cm = omap3_cm_init(omap3_l4ta_get(s->l4, 1), NULL, NULL, NULL, s);\r
3993 \r
3994     s->omap3_prm = omap3_prm_init(omap3_l4ta_get(s->l4, 2),\r
3995                                   NULL, NULL, NULL, s);\r
3996 \r
3997     s->omap3_mpu_wdt = omap3_mpu_wdt_init(omap3_l4ta_get(s->l4, 3),\r
3998                                           NULL,\r
3999                                           omap_findclk(s,\r
4000                                                        "omap3_wkup_32k_fclk"),\r
4001                                           omap_findclk(s, "omap3_wkup_l4_iclk"),\r
4002                                           s);\r
4003 \r
4004     s->omap3_scm = omap3_scm_init(omap3_l4ta_get(s->l4, 4), s);\r
4005 \r
4006     s->omap3_pm = omap3_pm_init(s);\r
4007     s->omap3_sms = omap3_sms_init(s);\r
4008 \r
4009     s->gptimer[0] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 5),\r
4010                                        s->irq[0][OMAP_INT_35XX_GPTIMER1],\r
4011                                        omap_findclk(s, "omap3_gp1_fclk"),\r
4012                                        omap_findclk(s, "omap3_wkup_l4_iclk"));\r
4013     s->gptimer[1] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 6),\r
4014                                        s->irq[0][OMAP_INT_35XX_GPTIMER2],\r
4015                                        omap_findclk(s, "omap3_gp2_fclk"),\r
4016                                        omap_findclk(s, "omap3_per_l4_iclk"));\r
4017     s->gptimer[2] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 7),\r
4018                                        s->irq[0][OMAP_INT_35XX_GPTIMER3],\r
4019                                        omap_findclk(s, "omap3_gp3_fclk"),\r
4020                                        omap_findclk(s, "omap3_per_l4_iclk"));\r
4021     s->gptimer[3] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 8),\r
4022                                        s->irq[0][OMAP_INT_35XX_GPTIMER4],\r
4023                                        omap_findclk(s, "omap3_gp4_fclk"),\r
4024                                        omap_findclk(s, "omap3_per_l4_iclk"));\r
4025     s->gptimer[4] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 9),\r
4026                                        s->irq[0][OMAP_INT_35XX_GPTIMER5],\r
4027                                        omap_findclk(s, "omap3_gp5_fclk"),\r
4028                                        omap_findclk(s, "omap3_per_l4_iclk"));\r
4029     s->gptimer[5] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 10),\r
4030                                        s->irq[0][OMAP_INT_35XX_GPTIMER6],\r
4031                                        omap_findclk(s, "omap3_gp6_fclk"),\r
4032                                        omap_findclk(s, "omap3_per_l4_iclk"));\r
4033     s->gptimer[6] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 11),\r
4034                                        s->irq[0][OMAP_INT_35XX_GPTIMER7],\r
4035                                        omap_findclk(s, "omap3_gp7_fclk"),\r
4036                                        omap_findclk(s, "omap3_per_l4_iclk"));\r
4037     s->gptimer[7] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 12),\r
4038                                        s->irq[0][OMAP_INT_35XX_GPTIMER8],\r
4039                                        omap_findclk(s, "omap3_gp8_fclk"),\r
4040                                        omap_findclk(s, "omap3_per_l4_iclk"));\r
4041     s->gptimer[8] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 13),\r
4042                                        s->irq[0][OMAP_INT_35XX_GPTIMER9],\r
4043                                        omap_findclk(s, "omap3_gp9_fclk"),\r
4044                                        omap_findclk(s, "omap3_per_l4_iclk"));\r
4045     s->gptimer[9] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 14),\r
4046                                        s->irq[0][OMAP_INT_35XX_GPTIMER10],\r
4047                                        omap_findclk(s, "omap3_gp10_fclk"),\r
4048                                        omap_findclk(s, "omap3_core_l4_iclk"));\r
4049     s->gptimer[10] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 15),\r
4050                                        s->irq[0][OMAP_INT_35XX_GPTIMER11],\r
4051                                        omap_findclk(s, "omap3_gp12_fclk"),\r
4052                                        omap_findclk(s, "omap3_core_l4_iclk"));\r
4053     s->gptimer[11] = omap_gp_timer_init(omap3_l4ta_get(s->l4, 16),\r
4054                                        s->irq[0][OMAP_INT_35XX_GPTIMER12],\r
4055                                        omap_findclk(s, "omap3_gp12_fclk"),\r
4056                                        omap_findclk(s, "omap3_wkup_l4_iclk"));\r
4057 \r
4058     \r
4059         \r
4060     omap_synctimer_init(omap3_l4ta_get(s->l4, 17), s,\r
4061                         omap_findclk(s, "omap3_sys_32k"), NULL);\r
4062 \r
4063     s->sdrc = omap_sdrc_init(0x6d000000);\r
4064     \r
4065     s->gpmc = omap_gpmc_init(s, 0x6e000000, s->irq[0][OMAP_INT_35XX_GPMC_IRQ]);\r
4066     \r
4067 \r
4068     s->uart[0] = omap2_uart_init(omap3_l4ta_get(s->l4, 18),\r
4069                                  s->irq[0][OMAP_INT_35XX_UART1_IRQ],\r
4070                                  omap_findclk(s, "omap3_uart1_fclk"),\r
4071                                  omap_findclk(s, "omap3_uart1_iclk"),\r
4072                                  s->drq[OMAP35XX_DMA_UART1_TX],\r
4073                                  s->drq[OMAP35XX_DMA_UART1_RX], serial_hds[0]);\r
4074     s->uart[1] = omap2_uart_init(omap3_l4ta_get(s->l4, 19),\r
4075                                  s->irq[0][OMAP_INT_35XX_UART2_IRQ],\r
4076                                  omap_findclk(s, "omap3_uart2_fclk"),\r
4077                                  omap_findclk(s, "omap3_uart2_iclk"),\r
4078                                  s->drq[OMAP35XX_DMA_UART2_TX],\r
4079                                  s->drq[OMAP35XX_DMA_UART2_RX],\r
4080                                  serial_hds[0] ? serial_hds[1] : 0);\r
4081     s->uart[2] = omap2_uart_init(omap3_l4ta_get(s->l4, 20),\r
4082                                  s->irq[0][OMAP_INT_35XX_UART3_IRQ],\r
4083                                  omap_findclk(s, "omap3_uart2_fclk"),\r
4084                                  omap_findclk(s, "omap3_uart3_iclk"),\r
4085                                  s->drq[OMAP35XX_DMA_UART3_TX],\r
4086                                  s->drq[OMAP35XX_DMA_UART3_RX],\r
4087                                  serial_hds[0]\r
4088                                  && serial_hds[1] ? serial_hds[2] : 0);\r
4089     \r
4090     /*attach serial[0] to uart 2 for beagle board */\r
4091     omap_uart_attach(s->uart[2], serial_hds[0]);\r
4092 \r
4093     s->dss = omap_dss_init(omap3_l4ta_get(s->l4, 21), 0x68005400, ds,\r
4094                     s->irq[0][OMAP_INT_35XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],\r
4095                    NULL,NULL,NULL,NULL,NULL);\r
4096 \r
4097     //gpio_clks[0] = NULL;\r
4098     //gpio_clks[1] = NULL;\r
4099     //gpio_clks[2] = NULL;\r
4100     //gpio_clks[3] = NULL;\r
4101 \r
4102     s->gpif = omap3_gpif_init();\r
4103     /*gpio 1*/\r
4104     omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 22),\r
4105                     &s->irq[0][OMAP_INT_35XX_GPIO_BANK1], \r
4106                     NULL,NULL,0);\r
4107     /*gpio 2*/\r
4108     omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 23),\r
4109                     &s->irq[0][OMAP_INT_35XX_GPIO_BANK2], \r
4110                     NULL,NULL,1);\r
4111     /*gpio 3*/\r
4112     omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 24),\r
4113                     &s->irq[0][OMAP_INT_35XX_GPIO_BANK3], \r
4114                     NULL,NULL,2);\r
4115     /*gpio 4*/\r
4116     omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 25),\r
4117                     &s->irq[0][OMAP_INT_35XX_GPIO_BANK4], \r
4118                     NULL,NULL,3);\r
4119 \r
4120     /*gpio 5*/\r
4121     omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 26),\r
4122                     &s->irq[0][OMAP_INT_35XX_GPIO_BANK5], \r
4123                     NULL,NULL,4);\r
4124      /*gpio 6*/\r
4125     omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, 27),\r
4126                     &s->irq[0][OMAP_INT_35XX_GPIO_BANK6], \r
4127                     NULL,NULL,5);\r
4128 \r
4129      omap_tap_init(omap3_l4ta_get(s->l4, 28), s);\r
4130 \r
4131     s->omap3_mmc = omap3_mmc_init(omap3_l4ta_get(s->l4, 29), drives_table[sdindex].bdrv,\r
4132                     s->irq[0][OMAP_INT_35XX_MMC1_IRQ],\r
4133                     &s->drq[OMAP35XX_DMA_MMC1_TX],\r
4134                     omap_findclk(s, "omap3_mmc1_fclk"), omap_findclk(s, "omap3_mmc1_iclk"));\r
4135 \r
4136     s->i2c[0] = omap3_i2c_init(omap3_l4ta_get(s->l4, 32),\r
4137                                s->irq[0][OMAP_INT_35XX_I2C1_IRQ],\r
4138                                &s->drq[OMAP35XX_DMA_I2C1_TX],\r
4139                                omap_findclk(s, "omap3_i2c1_fclk"),\r
4140                                omap_findclk(s, "omap3_i2c1_iclk"),\r
4141                                8);\r
4142     s->i2c[1] = omap3_i2c_init(omap3_l4ta_get(s->l4, 33),\r
4143                                s->irq[0][OMAP_INT_35XX_I2C2_IRQ],\r
4144                                &s->drq[OMAP35XX_DMA_I2C2_TX],\r
4145                                omap_findclk(s, "omap3_i2c2_fclk"),\r
4146                                omap_findclk(s, "omap3_i2c2_iclk"),\r
4147                                8);\r
4148     s->i2c[2] = omap3_i2c_init(omap3_l4ta_get(s->l4, 34),\r
4149                                s->irq[0][OMAP_INT_35XX_I2C3_IRQ],\r
4150                                &s->drq[OMAP35XX_DMA_I2C3_TX],\r
4151                                omap_findclk(s, "omap3_i2c3_fclk"),\r
4152                                omap_findclk(s, "omap3_i2c3_iclk"),\r
4153                                64);\r
4154 \r
4155     return s;\r
4156 }\r