git.maemo.org Git - qemu/blob - hw/omap3.c

   1 /*
   2  * TI OMAP3 processors emulation.
   3  *
   4  * Copyright (C) 2008 yajin <yajin@vm-kernel.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 or
   9  * (at your option) version 3 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include "hw.h"
  23 #include "arm-misc.h"
  24 #include "omap.h"
  25 #include "sysemu.h"
  26 #include "qemu-timer.h"
  27 #include "qemu-char.h"
  28 #include "flash.h"
  29 #include "soc_dma.h"
  30 #include "audio/audio.h"
  31 #include "block.h"
  32
  33 //#define OMAP3_DEBUG_
  34
  35 #ifdef OMAP3_DEBUG_
  36 #define TRACE(fmt, ...) fprintf(stderr, "%s " fmt "\n", __FUNCTION__, ##__VA_ARGS__)
  37 #else
  38 #define TRACE(...)
  39 #endif
  40
  41 static uint32_t omap3_l4ta_read(void *opaque, target_phys_addr_t addr)
  42 {
  43     struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
  44
  45     switch (addr) {
  46         case 0x00: /* COMPONENT_L */
  47             return s->component;
  48         case 0x04: /* COMPONENT_H */
  49             return 0;
  50         case 0x18: /* CORE_L */
  51             return s->component;
  52         case 0x1c: /* CORE_H */
  53             return (s->component >> 16);
  54         case 0x20: /* AGENT_CONTROL_L */
  55             return s->control;
  56         case 0x24: /* AGENT_CONTROL_H */
  57             return s->control_h;
  58         case 0x28: /* AGENT_STATUS_L */
  59             return s->status;
  60         case 0x2c: /* AGENT_STATUS_H */
  61             return 0;
  62         default:
  63             break;
  64     }
  65
  66     OMAP_BAD_REG(s->base + addr);
  67     return 0;
  68 }
  69
  70 static void omap3_l4ta_write(void *opaque, target_phys_addr_t addr,
  71                              uint32_t value)
  72 {
  73     struct omap_target_agent_s *s = (struct omap_target_agent_s *)opaque;
  74
  75     switch (addr) {
  76         case 0x00: /* COMPONENT_L */
  77         case 0x04: /* COMPONENT_H */
  78         case 0x18: /* CORE_L */
  79         case 0x1c: /* CORE_H */
  80             OMAP_RO_REG(s->base + addr);
  81             break;
  82         case 0x20: /* AGENT_CONTROL_L */
  83             s->control = value & 0x00000701;
  84             break;
  85         case 0x24: /* AGENT_CONTROL_H */
  86             s->control_h = value & 0x100; /* TODO: shouldn't this be read-only? */
  87             break;
  88         case 0x28: /* AGENT_STATUS_L */
  89             if (value & 0x100)
  90                 s->status &= ~0x100; /* REQ_TIMEOUT */
  91             break;
  92         case 0x2c: /* AGENT_STATUS_H */
  93             /* no writable bits although the register is listed as RW */
  94             break;
  95         default:
  96             OMAP_BAD_REG(s->base + addr);
  97             break;
  98     }
  99 }
 100
 101 static CPUReadMemoryFunc *omap3_l4ta_readfn[] = {
 102     omap_badwidth_read16,
 103     omap3_l4ta_read,
 104     omap_badwidth_read16,
 105 };
 106
 107 static CPUWriteMemoryFunc *omap3_l4ta_writefn[] = {
 108     omap_badwidth_write32,
 109     omap_badwidth_write32,
 110     omap3_l4ta_write,
 111 };
 112
 113 enum omap3_l4_region_id_t {
 114     /* 48000000-48001FFF */
 115     /* 48002000-48002FFF */ L4ID_SCM = 0,
 116     /* 48003000-48003FFF */ L4ID_SCM_TA,
 117     /* 48004000-48005FFF */ L4ID_CM_A,
 118     /* 48006000-480067FF */ L4ID_CM_B,
 119     /* 48006800-48006FFF */
 120     /* 48007000-48007FFF */ L4ID_CM_TA,
 121     /* 48008000-48023FFF */
 122     /* 48024000-48024FFF */
 123     /* 48025000-48025FFF */
 124     /* 48026000-4803FFFF */
 125     /* 48040000-480407FF */ L4ID_CORE_AP,
 126     /* 48040800-48040FFF */ L4ID_CORE_IP,
 127     /* 48041000-48041FFF */ L4ID_CORE_LA,
 128     /* 48042000-4804FBFF */
 129     /* 4804FC00-4804FFFF */ L4ID_DSI,
 130     /* 48050000-480503FF */ L4ID_DSS,
 131     /* 48050400-480507FF */ L4ID_DISPC,
 132     /* 48050800-48050BFF */ L4ID_RFBI,
 133     /* 48050C00-48050FFF */ L4ID_VENC,
 134     /* 48051000-48051FFF */ L4ID_DSS_TA,
 135     /* 48052000-48055FFF */
 136     /* 48056000-48056FFF */ L4ID_SDMA,
 137     /* 48057000-48057FFF */ L4ID_SDMA_TA,
 138     /* 48058000-4805FFFF */
 139     /* 48060000-48060FFF */ L4ID_I2C3,
 140     /* 48061000-48061FFF */ L4ID_I2C3_TA,
 141     /* 48062000-48062FFF */ L4ID_USBTLL,
 142     /* 48063000-48063FFF */ L4ID_USBTLL_TA,
 143     /* 48064000-48064FFF */ L4ID_HSUSBHOST,
 144     /* 48065000-48065FFF */ L4ID_HSUSBHOST_TA,
 145     /* 48066000-48069FFF */
 146     /* 4806A000-4806AFFF */ L4ID_UART1,
 147     /* 4806B000-4806BFFF */ L4ID_UART1_TA,
 148     /* 4806C000-4806CFFF */ L4ID_UART2,
 149     /* 4806D000-4806DFFF */ L4ID_UART2_TA,
 150     /* 4806E000-4806FFFF */
 151     /* 48070000-48070FFF */ L4ID_I2C1,
 152     /* 48071000-48071FFF */ L4ID_I2C1_TA,
 153     /* 48072000-48072FFF */ L4ID_I2C2,
 154     /* 48073000-48073FFF */ L4ID_I2C2_TA,
 155     /* 48074000-48074FFF */ L4ID_MCBSP1,
 156     /* 48075000-48075FFF */ L4ID_MCBSP1_TA,
 157     /* 48076000-48085FFF */
 158     /* 48086000-48086FFF */ L4ID_GPTIMER10,
 159     /* 48087000-48087FFF */ L4ID_GPTIMER10_TA,
 160     /* 48088000-48088FFF */ L4ID_GPTIMER11,
 161     /* 48089000-48089FFF */ L4ID_GPTIMER11_TA,
 162     /* 4808A000-4808AFFF */
 163     /* 4808B000-4808BFFF */
 164     /* 4808C000-48093FFF */
 165     /* 48094000-48094FFF */ L4ID_MAILBOX,
 166     /* 48095000-48095FFF */ L4ID_MAILBOX_TA,
 167     /* 48096000-48096FFF */ L4ID_MCBSP5,
 168     /* 48097000-48097FFF */ L4ID_MCBSP5_TA,
 169     /* 48098000-48098FFF */ L4ID_MCSPI1,
 170     /* 48099000-48099FFF */ L4ID_MCSPI1_TA,
 171     /* 4809A000-4809AFFF */ L4ID_MCSPI2,
 172     /* 4809B000-4809BFFF */ L4ID_MCSPI2_TA,
 173     /* 4809C000-4809CFFF */ L4ID_MMCSDIO1,
 174     /* 4809D000-4809DFFF */ L4ID_MMCSDIO1_TA,
 175     /* 4809E000-4809EFFF */ L4ID_MSPRO,
 176     /* 4809F000-4809FFFF */ L4ID_MSPRO_TA,
 177     /* 480A0000-480AAFFF */
 178     /* 480AB000-480ABFFF */ L4ID_HSUSBOTG,
 179     /* 480AC000-480ACFFF */ L4ID_HSUSBOTG_TA,
 180     /* 480AD000-480ADFFF */ L4ID_MMCSDIO3,
 181     /* 480AE000-480AEFFF */ L4ID_MMCSDIO3_TA,
 182     /* 480AF000-480AFFFF */
 183     /* 480B0000-480B0FFF */
 184     /* 480B1000-480B1FFF */
 185     /* 480B2000-480B2FFF */ L4ID_HDQ1WIRE,
 186     /* 480B3000-480B2FFF */ L4ID_HDQ1WIRE_TA,
 187     /* 480B4000-480B4FFF */ L4ID_MMCSDIO2,
 188     /* 480B5000-480B5FFF */ L4ID_MMCSDIO2_TA,
 189     /* 480B6000-480B6FFF */ L4ID_ICRMPU,
 190     /* 480B7000-480B7FFF */ L4ID_ICRMPU_TA,
 191     /* 480B8000-480B8FFF */ L4ID_MCSPI3,
 192     /* 480B9000-480B9FFF */ L4ID_MCSPI3_TA,
 193     /* 480BA000-480BAFFF */ L4ID_MCSPI4,
 194     /* 480BB000-480BBFFF */ L4ID_MCSPI4_TA,
 195     /* 480BC000-480BFFFF */ L4ID_CAMERAISP,
 196     /* 480C0000-480C0FFF */ L4ID_CAMERAISP_TA,
 197     /* 480C1000-480CCFFF */
 198     /* 480CD000-480CDFFF */ L4ID_ICRMODEM,
 199     /* 480CE000-480CEFFF */ L4ID_ICRMODEM_TA,
 200     /* 480CF000-482FFFFF */
 201     /* 48300000-48303FFF */
 202     /* 48304000-48304FFF */ L4ID_GPTIMER12,
 203     /* 48305000-48305FFF */ L4ID_GPTIMER12_TA,
 204     /* 48306000-48307FFF */ L4ID_PRM_A,
 205     /* 48308000-483087FF */ L4ID_PRM_B,
 206     /* 48308800-48308FFF */
 207     /* 48309000-48309FFF */ L4ID_PRM_TA,
 208     /* 4830A000-4830AFFF */ L4ID_TAP,
 209     /* 4830B000-4830BFFF */ L4ID_TAP_TA,
 210     /* 4830C000-4830FFFF */
 211     /* 48310000-48310FFF */ L4ID_GPIO1,
 212     /* 48311000-48311FFF */ L4ID_GPIO1_TA,
 213     /* 48312000-48313FFF */
 214     /* 48314000-48314FFF */ L4ID_WDTIMER2,
 215     /* 48315000-48315FFF */ L4ID_WDTIMER2_TA,
 216     /* 48316000-48317FFF */
 217     /* 48318000-48318FFF */ L4ID_GPTIMER1,
 218     /* 48319000-48319FFF */ L4ID_GPTIMER1_TA,
 219     /* 4831A000-4831FFFF */
 220     /* 48320000-48320FFF */ L4ID_32KTIMER,
 221     /* 48321000-48321FFF */ L4ID_32KTIMER_TA,
 222     /* 48322000-48327FFF */
 223     /* 48328000-483287FF */ L4ID_WAKEUP_AP,
 224     /* 48328800-48328FFF */ L4ID_WAKEUP_C_IP,
 225     /* 48329000-48329FFF */ L4ID_WAKEUP_LA,
 226     /* 4832A000-4832A7FF */ L4ID_WAKEUP_E_IP,
 227     /* 4832A800-4833FFFF */
 228     /* 48340000-48340FFF */
 229     /* 48341000-48FFFFFF */
 230     /* 49000000-490007FF */ L4ID_PER_AP,
 231     /* 49000800-49000FFF */ L4ID_PER_IP,
 232     /* 49001000-49001FFF */ L4ID_PER_LA,
 233     /* 49002000-4901FFFF */
 234     /* 49020000-49020FFF */ L4ID_UART3,
 235     /* 49021000-49021FFF */ L4ID_UART3_TA,
 236     /* 49022000-49022FFF */ L4ID_MCBSP2,
 237     /* 49023000-49023FFF */ L4ID_MCBSP2_TA,
 238     /* 49024000-49024FFF */ L4ID_MCBSP3,
 239     /* 49025000-49025FFF */ L4ID_MCBSP3_TA,
 240     /* 49026000-49026FFF */ L4ID_MCBSP4,
 241     /* 49027000-49027FFF */ L4ID_MCBSP4_TA,
 242     /* 49028000-49028FFF */ L4ID_MCBSP2S,
 243     /* 49029000-49029FFF */ L4ID_MCBSP2S_TA,
 244     /* 4902A000-4902AFFF */ L4ID_MCBSP3S,
 245     /* 4902B000-4902BFFF */ L4ID_MCBSP3S_TA,
 246     /* 4902C000-4902FFFF */
 247     /* 49030000-49030FFF */ L4ID_WDTIMER3,
 248     /* 49031000-49031FFF */ L4ID_WDTIMER3_TA,
 249     /* 49032000-49032FFF */ L4ID_GPTIMER2,
 250     /* 49033000-49033FFF */ L4ID_GPTIMER2_TA,
 251     /* 49034000-49034FFF */ L4ID_GPTIMER3,
 252     /* 49035000-49035FFF */ L4ID_GPTIMER3_TA,
 253     /* 49036000-49036FFF */ L4ID_GPTIMER4,
 254     /* 49037000-49037FFF */ L4ID_GPTIMER4_TA,
 255     /* 49038000-49038FFF */ L4ID_GPTIMER5,
 256     /* 49039000-49039FFF */ L4ID_GPTIMER5_TA,
 257     /* 4903A000-4903AFFF */ L4ID_GPTIMER6,
 258     /* 4903B000-4903BFFF */ L4ID_GPTIMER6_TA,
 259     /* 4903C000-4903CFFF */ L4ID_GPTIMER7,
 260     /* 4903D000-4903DFFF */ L4ID_GPTIMER7_TA,
 261     /* 4903E000-4903EFFF */ L4ID_GPTIMER8,
 262     /* 4903F000-4903FFFF */ L4ID_GPTIMER8_TA,
 263     /* 49040000-49040FFF */ L4ID_GPTIMER9,
 264     /* 49041000-49041FFF */ L4ID_GPTIMER9_TA,
 265     /* 49042000-4904FFFF */
 266     /* 49050000-49050FFF */ L4ID_GPIO2,
 267     /* 49051000-49051FFF */ L4ID_GPIO2_TA,
 268     /* 49052000-49052FFF */ L4ID_GPIO3,
 269     /* 49053000-49053FFF */ L4ID_GPIO3_TA,
 270     /* 49054000-49054FFF */ L4ID_GPIO4,
 271     /* 49055000-49055FFF */ L4ID_GPIO4_TA,
 272     /* 49056000-49056FFF */ L4ID_GPIO5,
 273     /* 49057000-49057FFF */ L4ID_GPIO5_TA,
 274     /* 49058000-49058FFF */ L4ID_GPIO6,
 275     /* 49059000-49059FFF */ L4ID_GPIO6_TA,
 276     /* 4905A000-490FFFFF */
 277     /* 54000000-54003FFF */
 278     /* 54004000-54005FFF */
 279     /* 54006000-540067FF */ L4ID_EMU_AP,
 280     /* 54006800-54006FFF */ L4ID_EMU_IP_C,
 281     /* 54007000-54007FFF */ L4ID_EMU_LA,
 282     /* 54008000-540087FF */ L4ID_EMU_IP_DAP,
 283     /* 54008800-5400FFFF */
 284     /* 54010000-54017FFF */ L4ID_MPUEMU,
 285     /* 54018000-54018FFF */ L4ID_MPUEMU_TA,
 286     /* 54019000-54019FFF */ L4ID_TPIU,
 287     /* 5401A000-5401AFFF */ L4ID_TPIU_TA,
 288     /* 5401B000-5401BFFF */ L4ID_ETB,
 289     /* 5401C000-5401CFFF */ L4ID_ETB_TA,
 290     /* 5401D000-5401DFFF */ L4ID_DAPCTL,
 291     /* 5401E000-5401EFFF */ L4ID_DAPCTL_TA,
 292     /* 5401F000-5401FFFF */ L4ID_SDTI_TA,
 293     /* 54020000-544FFFFF */
 294     /* 54500000-5450FFFF */ L4ID_SDTI_CFG,
 295     /* 54510000-545FFFFF */
 296     /* 54600000-546FFFFF */ L4ID_SDTI,
 297     /* 54700000-54705FFF */
 298     /* 54706000-54707FFF */ L4ID_EMU_PRM_A,
 299     /* 54708000-547087FF */ L4ID_EMU_PRM_B,
 300     /* 54708800-54708FFF */
 301     /* 54709000-54709FFF */ L4ID_EMU_PRM_TA,
 302     /* 5470A000-5470FFFF */
 303     /* 54710000-54710FFF */ L4ID_EMU_GPIO1,
 304     /* 54711000-54711FFF */ L4ID_EMU_GPIO1_TA,
 305     /* 54712000-54713FFF */
 306     /* 54714000-54714FFF */ L4ID_EMU_WDTM2,
 307     /* 54715000-54715FFF */ L4ID_EMU_WDTM2_TA,
 308     /* 54716000-54717FFF */
 309     /* 54718000-54718FFF */ L4ID_EMU_GPTM1,
 310     /* 54719000-54719FFF */ L4ID_EMU_GPTM1_TA,
 311     /* 5471A000-5471FFFF */
 312     /* 54720000-54720FFF */ L4ID_EMU_32KTM,
 313     /* 54721000-54721FFF */ L4ID_EMU_32KTM_TA,
 314     /* 54722000-54727FFF */
 315     /* 54728000-547287FF */ L4ID_EMU_WKUP_AP,
 316     /* 54728800-54728FFF */ L4ID_EMU_WKUP_IPC,
 317     /* 54729000-54729FFF */ L4ID_EMU_WKUP_LA,
 318     /* 5472A000-5472A7FF */ L4ID_EMU_WKUP_IPE,
 319     /* 5472A800-547FFFFF */
 320 };
 321
 322 static struct omap_l4_region_s omap3_l4_region[] = {
 323     /* L4-Core */
 324     [L4ID_SCM         ] = {0x00002000, 0x1000, 32 | 16 | 8},
 325     [L4ID_SCM_TA      ] = {0x00003000, 0x1000, 32 | 16 | 8},
 326     [L4ID_CM_A        ] = {0x00004000, 0x2000, 32         },
 327     [L4ID_CM_B        ] = {0x00006000, 0x0800, 32         },
 328     [L4ID_CM_TA       ] = {0x00007000, 0x1000, 32 | 16 | 8},
 329     [L4ID_CORE_AP     ] = {0x00040000, 0x0800, 32         },
 330     [L4ID_CORE_IP     ] = {0x00040800, 0x0800, 32         },
 331     [L4ID_CORE_LA     ] = {0x00041000, 0x1000, 32         },
 332     [L4ID_DSI         ] = {0x0004fc00, 0x0400, 32 | 16 | 8},
 333     [L4ID_DSS         ] = {0x00050000, 0x0400, 32 | 16 | 8},
 334     [L4ID_DISPC       ] = {0x00050400, 0x0400, 32 | 16 | 8},
 335     [L4ID_RFBI        ] = {0x00050800, 0x0400, 32 | 16 | 8},
 336     [L4ID_VENC        ] = {0x00050c00, 0x0400, 32 | 16 | 8},
 337     [L4ID_DSS_TA      ] = {0x00051000, 0x1000, 32 | 16 | 8},
 338     [L4ID_SDMA        ] = {0x00056000, 0x1000, 32         },
 339     [L4ID_SDMA_TA     ] = {0x00057000, 0x1000, 32 | 16 | 8},
 340     [L4ID_I2C3        ] = {0x00060000, 0x1000,      16 | 8},
 341     [L4ID_I2C3_TA     ] = {0x00061000, 0x1000, 32 | 16 | 8},
 342     [L4ID_USBTLL      ] = {0x00062000, 0x1000, 32         },
 343     [L4ID_USBTLL_TA   ] = {0x00063000, 0x1000, 32 | 16 | 8},
 344     [L4ID_HSUSBHOST   ] = {0x00064000, 0x1000, 32         },
 345     [L4ID_HSUSBHOST_TA] = {0x00065000, 0x1000, 32 | 16 | 8},
 346     [L4ID_UART1       ] = {0x0006a000, 0x1000, 32 | 16 | 8},
 347     [L4ID_UART1_TA    ] = {0x0006b000, 0x1000, 32 | 16 | 8},
 348     [L4ID_UART2       ] = {0x0006c000, 0x1000, 32 | 16 | 8},
 349     [L4ID_UART2_TA    ] = {0x0006d000, 0x1000, 32 | 16 | 8},
 350     [L4ID_I2C1        ] = {0x00070000, 0x1000,      16 | 8},
 351     [L4ID_I2C1_TA     ] = {0x00071000, 0x1000, 32 | 16 | 8},
 352     [L4ID_I2C2        ] = {0x00072000, 0x1000,      16 | 8},
 353     [L4ID_I2C2_TA     ] = {0x00073000, 0x1000, 32 | 16 | 8},
 354     [L4ID_MCBSP1      ] = {0x00074000, 0x1000, 32         },
 355     [L4ID_MCBSP1_TA   ] = {0x00075000, 0x1000, 32 | 16 | 8},
 356     [L4ID_GPTIMER10   ] = {0x00086000, 0x1000, 32 | 16    },
 357     [L4ID_GPTIMER10_TA] = {0x00087000, 0x1000, 32 | 16 | 8},
 358     [L4ID_GPTIMER11   ] = {0x00088000, 0x1000, 32 | 16    },
 359     [L4ID_GPTIMER11_TA] = {0x00089000, 0x1000, 32 | 16 | 8},
 360     [L4ID_MAILBOX     ] = {0x00094000, 0x1000, 32 | 16 | 8},
 361     [L4ID_MAILBOX_TA  ] = {0x00095000, 0x1000, 32 | 16 | 8},
 362     [L4ID_MCBSP5      ] = {0x00096000, 0x1000, 32         },
 363     [L4ID_MCBSP5_TA   ] = {0x00097000, 0x1000, 32 | 16 | 8},
 364     [L4ID_MCSPI1      ] = {0x00098000, 0x1000, 32 | 16 | 8},
 365     [L4ID_MCSPI1_TA   ] = {0x00099000, 0x1000, 32 | 16 | 8},
 366     [L4ID_MCSPI2      ] = {0x0009a000, 0x1000, 32 | 16 | 8},
 367     [L4ID_MCSPI2_TA   ] = {0x0009b000, 0x1000, 32 | 16 | 8},
 368     [L4ID_MMCSDIO1    ] = {0x0009c000, 0x1000, 32         },
 369     [L4ID_MMCSDIO1_TA ] = {0x0009d000, 0x1000, 32 | 16 | 8},
 370     [L4ID_MSPRO       ] = {0x0009e000, 0x1000, 32         },
 371     [L4ID_MSPRO_TA    ] = {0x0009f000, 0x1000, 32 | 16 | 8},
 372     [L4ID_HSUSBOTG    ] = {0x000ab000, 0x1000, 32         },
 373     [L4ID_HSUSBOTG_TA ] = {0x000ac000, 0x1000, 32 | 16 | 8},
 374     [L4ID_MMCSDIO3    ] = {0x000ad000, 0x1000, 32         },
 375     [L4ID_MMCSDIO3_TA ] = {0x000ae000, 0x1000, 32 | 16 | 8},
 376     [L4ID_HDQ1WIRE    ] = {0x000b2000, 0x1000, 32         },
 377     [L4ID_HDQ1WIRE_TA ] = {0x000b3000, 0x1000, 32 | 16 | 8},
 378     [L4ID_MMCSDIO2    ] = {0x000b4000, 0x1000, 32         },
 379     [L4ID_MMCSDIO2_TA ] = {0x000b5000, 0x1000, 32 | 16 | 8},
 380     [L4ID_ICRMPU      ] = {0x000b6000, 0x1000, 32         },
 381     [L4ID_ICRMPU_TA   ] = {0x000b7000, 0x1000, 32 | 16 | 8},
 382     [L4ID_MCSPI3      ] = {0x000b8000, 0x1000, 32 | 16 | 8},
 383     [L4ID_MCSPI3_TA   ] = {0x000b9000, 0x1000, 32 | 16 | 8},
 384     [L4ID_MCSPI4      ] = {0x000ba000, 0x1000, 32 | 16 | 8},
 385     [L4ID_MCSPI4_TA   ] = {0x000bb000, 0x1000, 32 | 16 | 8},
 386     [L4ID_CAMERAISP   ] = {0x000bc000, 0x4000, 32 | 16 | 8},
 387     [L4ID_CAMERAISP_TA] = {0x000c0000, 0x1000, 32 | 16 | 8},
 388     [L4ID_ICRMODEM    ] = {0x000cd000, 0x1000, 32         },
 389     [L4ID_ICRMODEM_TA ] = {0x000ce000, 0x1000, 32 | 16 | 8},
 390     /* L4-Wakeup interconnect region A */
 391     [L4ID_GPTIMER12   ] = {0x00304000, 0x1000, 32 | 16    },
 392     [L4ID_GPTIMER12_TA] = {0x00305000, 0x1000, 32 | 16 | 8},
 393     [L4ID_PRM_A       ] = {0x00306000, 0x2000, 32         },
 394     [L4ID_PRM_B       ] = {0x00308000, 0x0800, 32         },
 395     [L4ID_PRM_TA      ] = {0x00309000, 0x1000, 32 | 16 | 8},
 396     /* L4-Core */
 397     [L4ID_TAP         ] = {0x0030a000, 0x1000, 32 | 16 | 8},
 398     [L4ID_TAP_TA      ] = {0x0030b000, 0x1000, 32 | 16 | 8},
 399     /* L4-Wakeup interconnect region B */
 400     [L4ID_GPIO1       ] = {0x00310000, 0x1000, 32 | 16 | 8},
 401     [L4ID_GPIO1_TA    ] = {0x00311000, 0x1000, 32 | 16 | 8},
 402     [L4ID_WDTIMER2    ] = {0x00314000, 0x1000, 32 | 16    },
 403     [L4ID_WDTIMER2_TA ] = {0x00315000, 0x1000, 32 | 16 | 8},
 404     [L4ID_GPTIMER1    ] = {0x00318000, 0x1000, 32 | 16    },
 405     [L4ID_GPTIMER1_TA ] = {0x00319000, 0x1000, 32 | 16 | 8},
 406     [L4ID_32KTIMER    ] = {0x00320000, 0x1000, 32 | 16    },
 407     [L4ID_32KTIMER_TA ] = {0x00321000, 0x1000, 32 | 16 | 8},
 408     [L4ID_WAKEUP_AP   ] = {0x00328000, 0x0800, 32 | 16 | 8},
 409     [L4ID_WAKEUP_C_IP ] = {0x00328800, 0x0800, 32 | 16 | 8},
 410     [L4ID_WAKEUP_LA   ] = {0x00329000, 0x1000, 32 | 16 | 8},
 411     [L4ID_WAKEUP_E_IP ] = {0x0032a000, 0x0800, 32 | 16 | 8},
 412     /* L4-Per */
 413     [L4ID_PER_AP      ] = {0x01000000, 0x0800, 32 | 16 | 8},
 414     [L4ID_PER_IP      ] = {0x01000800, 0x0800, 32 | 16 | 8},
 415     [L4ID_PER_LA      ] = {0x01001000, 0x1000, 32 | 16 | 8},
 416     [L4ID_UART3       ] = {0x01020000, 0x1000, 32 | 16 | 8},
 417     [L4ID_UART3_TA    ] = {0x01021000, 0x1000, 32 | 16 | 8},
 418     [L4ID_MCBSP2      ] = {0x01022000, 0x1000, 32         },
 419     [L4ID_MCBSP2_TA   ] = {0x01023000, 0x1000, 32 | 16 | 8},
 420     [L4ID_MCBSP3      ] = {0x01024000, 0x1000, 32         },
 421     [L4ID_MCBSP3_TA   ] = {0x01025000, 0x1000, 32 | 16 | 8},
 422     [L4ID_MCBSP4      ] = {0x01026000, 0x1000, 32         },
 423     [L4ID_MCBSP4_TA   ] = {0x01027000, 0x1000, 32 | 16 | 8},
 424     [L4ID_MCBSP2S     ] = {0x01028000, 0x1000, 32         },
 425     [L4ID_MCBSP2S_TA  ] = {0x01029000, 0x1000, 32 | 16 | 8},
 426     [L4ID_MCBSP3S     ] = {0x0102a000, 0x1000, 32         },
 427     [L4ID_MCBSP3S_TA  ] = {0x0102b000, 0x1000, 32 | 16 | 8},
 428     [L4ID_WDTIMER3    ] = {0x01030000, 0x1000, 32 | 16    },
 429     [L4ID_WDTIMER3_TA ] = {0x01031000, 0x1000, 32 | 16 | 8},
 430     [L4ID_GPTIMER2    ] = {0x01032000, 0x1000, 32 | 16    },
 431     [L4ID_GPTIMER2_TA ] = {0x01033000, 0x1000, 32 | 16 | 8},
 432     [L4ID_GPTIMER3    ] = {0x01034000, 0x1000, 32 | 16    },
 433     [L4ID_GPTIMER3_TA ] = {0x01035000, 0x1000, 32 | 16 | 8},
 434     [L4ID_GPTIMER4    ] = {0x01036000, 0x1000, 32 | 16    },
 435     [L4ID_GPTIMER4_TA ] = {0x01037000, 0x1000, 32 | 16 | 8},
 436     [L4ID_GPTIMER5    ] = {0x01038000, 0x1000, 32 | 16    },
 437     [L4ID_GPTIMER5_TA ] = {0x01039000, 0x1000, 32 | 16 | 8},
 438     [L4ID_GPTIMER6    ] = {0x0103a000, 0x1000, 32 | 16    },
 439     [L4ID_GPTIMER6_TA ] = {0x0103b000, 0x1000, 32 | 16 | 8},
 440     [L4ID_GPTIMER7    ] = {0x0103c000, 0x1000, 32 | 16    },
 441     [L4ID_GPTIMER7_TA ] = {0x0103d000, 0x1000, 32 | 16 | 8},
 442     [L4ID_GPTIMER8    ] = {0x0103e000, 0x1000, 32 | 16    },
 443     [L4ID_GPTIMER8_TA ] = {0x0103f000, 0x1000, 32 | 16 | 8},
 444     [L4ID_GPTIMER9    ] = {0x01040000, 0x1000, 32 | 16    },
 445     [L4ID_GPTIMER9_TA ] = {0x01041000, 0x1000, 32 | 16 | 8},
 446     [L4ID_GPIO2       ] = {0x01050000, 0x1000, 32 | 16 | 8},
 447     [L4ID_GPIO2_TA    ] = {0x01051000, 0x1000, 32 | 16 | 8},
 448     [L4ID_GPIO3       ] = {0x01052000, 0x1000, 32 | 16 | 8},
 449     [L4ID_GPIO3_TA    ] = {0x01053000, 0x1000, 32 | 16 | 8},
 450     [L4ID_GPIO4       ] = {0x01054000, 0x1000, 32 | 16 | 8},
 451     [L4ID_GPIO4_TA    ] = {0x01055000, 0x1000, 32 | 16 | 8},
 452     [L4ID_GPIO5       ] = {0x01056000, 0x1000, 32 | 16 | 8},
 453     [L4ID_GPIO5_TA    ] = {0x01057000, 0x1000, 32 | 16 | 8},
 454     [L4ID_GPIO6       ] = {0x01058000, 0x1000, 32 | 16 | 8},
 455     [L4ID_GPIO6_TA    ] = {0x01059000, 0x1000, 32 | 16 | 8},
 456     /* L4-Emu */
 457     [L4ID_EMU_AP      ] = {0x0c006000, 0x0800, 32 | 16 | 8},
 458     [L4ID_EMU_IP_C    ] = {0x0c006800, 0x0800, 32 | 16 | 8},
 459     [L4ID_EMU_LA      ] = {0x0c007000, 0x1000, 32 | 16 | 8},
 460     [L4ID_EMU_IP_DAP  ] = {0x0c008000, 0x0800, 32 | 16 | 8},
 461     [L4ID_MPUEMU      ] = {0x0c010000, 0x8000, 32 | 16 | 8},
 462     [L4ID_MPUEMU_TA   ] = {0x0c018000, 0x1000, 32 | 16 | 8},
 463     [L4ID_TPIU        ] = {0x0c019000, 0x1000, 32         },
 464     [L4ID_TPIU_TA     ] = {0x0c01a000, 0x1000, 32 | 16 | 8},
 465     [L4ID_ETB         ] = {0x0c01b000, 0x1000, 32         },
 466     [L4ID_ETB_TA      ] = {0x0c01c000, 0x1000, 32 | 16 | 8},
 467     [L4ID_DAPCTL      ] = {0x0c01d000, 0x1000, 32         },
 468     [L4ID_DAPCTL_TA   ] = {0x0c01e000, 0x1000, 32 | 16 | 8},
 469     [L4ID_EMU_PRM_A   ] = {0x0c706000, 0x2000, 32         },
 470     [L4ID_EMU_PRM_B   ] = {0x0c706800, 0x0800, 32         },
 471     [L4ID_EMU_PRM_TA  ] = {0x0c709000, 0x1000, 32 | 16 | 8},
 472     [L4ID_EMU_GPIO1   ] = {0x0c710000, 0x1000, 32 | 16 | 8},
 473     [L4ID_EMU_GPIO1_TA] = {0x0c711000, 0x1000, 32 | 16 | 8},
 474     [L4ID_EMU_WDTM2   ] = {0x0c714000, 0x1000, 32 | 16    },
 475     [L4ID_EMU_WDTM2_TA] = {0x0c715000, 0x1000, 32 | 16 | 8},
 476     [L4ID_EMU_GPTM1   ] = {0x0c718000, 0x1000, 32 | 16 | 8},
 477     [L4ID_EMU_GPTM1_TA] = {0x0c719000, 0x1000, 32 | 16 | 8},
 478     [L4ID_EMU_32KTM   ] = {0x0c720000, 0x1000, 32 | 16    },
 479     [L4ID_EMU_32KTM_TA] = {0x0c721000, 0x1000, 32 | 16 | 8},
 480     [L4ID_EMU_WKUP_AP ] = {0x0c728000, 0x0800, 32 | 16 | 8},
 481     [L4ID_EMU_WKUP_IPC] = {0x0c728800, 0x0800, 32 | 16 | 8},
 482     [L4ID_EMU_WKUP_LA ] = {0x0c729000, 0x1000, 32 | 16 | 8},
 483     [L4ID_EMU_WKUP_IPE] = {0x0c72a000, 0x0800, 32 | 16 | 8},
 484 };
 485
 486 enum omap3_agent_info_id_t {
 487     L4A_SCM = 0,
 488     L4A_CM,
 489     L4A_PRM,
 490     L4A_GPTIMER1,
 491     L4A_GPTIMER2,
 492     L4A_GPTIMER3,
 493     L4A_GPTIMER4,
 494     L4A_GPTIMER5,
 495     L4A_GPTIMER6,
 496     L4A_GPTIMER7,
 497     L4A_GPTIMER8,
 498     L4A_GPTIMER9,
 499     L4A_GPTIMER10,
 500     L4A_GPTIMER11,
 501     L4A_GPTIMER12,
 502     L4A_WDTIMER2,
 503     L4A_32KTIMER,
 504     L4A_UART1,
 505     L4A_UART2,
 506     L4A_UART3,
 507     L4A_DSS,
 508     L4A_GPIO1,
 509     L4A_GPIO2,
 510     L4A_GPIO3,
 511     L4A_GPIO4,
 512     L4A_GPIO5,
 513     L4A_GPIO6,
 514     L4A_MMC1,
 515     L4A_MMC2,
 516     L4A_MMC3,
 517     L4A_I2C1,
 518     L4A_I2C2,
 519     L4A_I2C3,
 520     L4A_TAP
 521 };
 522
 523 static struct omap_l4_agent_info_s omap3_l4_agent_info[] = {
 524     /* L4-Core Target Agents */
 525     {L4A_DSS,       L4ID_DSI,       6, 4},
 526     /* TODO: camera */
 527     /* TODO: USBHS OTG */
 528     /* TODO: USBHS host */
 529     /* TODO: USBTLL */
 530     {L4A_UART1,     L4ID_UART1,     2, 1},
 531     {L4A_UART2,     L4ID_UART2,     2, 1},
 532     {L4A_I2C1,      L4ID_I2C1,      2, 1},
 533     {L4A_I2C2,      L4ID_I2C2,      2, 1},
 534     {L4A_I2C3,      L4ID_I2C3,      2, 1},
 535     /* TODO: McBSP1 */
 536     /* TODO: McBSP5 */
 537     {L4A_GPTIMER10, L4ID_GPTIMER10, 2, 1},
 538     {L4A_GPTIMER11, L4ID_GPTIMER11, 2, 1},
 539     /* TODO: SPI1 */
 540     /* TODO: SPI2 */
 541     {L4A_MMC1,      L4ID_MMCSDIO1,  2, 1},
 542     {L4A_MMC2,      L4ID_MMCSDIO2,  2, 1},
 543     {L4A_MMC3,      L4ID_MMCSDIO3,  2, 1},
 544     /* TODO: HDQ/1-Wire */
 545     /* TODO: Mailbox */
 546     /* TODO: SPI3 */
 547     /* TODO: SPI4 */
 548     /* TODO: SDMA */
 549     {L4A_CM,        L4ID_CM_A,      3, 2},
 550     {L4A_SCM,       L4ID_SCM,       2, 1},
 551     {L4A_TAP,       L4ID_TAP,       2, 1},
 552     /* L4-Wakeup Target Agents */
 553     {L4A_GPTIMER12, L4ID_GPTIMER12, 2, 1},
 554     {L4A_PRM,       L4ID_PRM_A,     3, 2},
 555     {L4A_GPIO1,     L4ID_GPIO1,     2, 1},
 556     {L4A_WDTIMER2,  L4ID_WDTIMER2,  2, 1},
 557     {L4A_GPTIMER1,  L4ID_GPTIMER1,  2, 1},
 558     {L4A_32KTIMER,  L4ID_32KTIMER,  2, 1},
 559     /* L4-Per Target Agents */
 560     {L4A_UART3,     L4ID_UART3,     2, 1},
 561     /* TODO: McBSP2 */
 562     /* TODO: McBSP3 */
 563     {L4A_GPTIMER2,  L4ID_GPTIMER2,  2, 1},
 564     {L4A_GPTIMER3,  L4ID_GPTIMER3,  2, 1},
 565     {L4A_GPTIMER4,  L4ID_GPTIMER4,  2, 1},
 566     {L4A_GPTIMER5,  L4ID_GPTIMER5,  2, 1},
 567     {L4A_GPTIMER6,  L4ID_GPTIMER6,  2, 1},
 568     {L4A_GPTIMER7,  L4ID_GPTIMER7,  2, 1},
 569     {L4A_GPTIMER8,  L4ID_GPTIMER8,  2, 1},
 570     {L4A_GPTIMER9,  L4ID_GPTIMER9,  2, 1},
 571     {L4A_GPIO2,     L4ID_GPIO2,     2, 1},
 572     {L4A_GPIO3,     L4ID_GPIO3,     2, 1},
 573     {L4A_GPIO4,     L4ID_GPIO4,     2, 1},
 574     {L4A_GPIO5,     L4ID_GPIO5,     2, 1},
 575     {L4A_GPIO6,     L4ID_GPIO6,     2, 1},
 576 };
 577
 578 static struct omap_target_agent_s *omap3_l4ta_get(struct omap_l4_s *bus, int cs)
 579 {
 580     int i, iomemtype;
 581     struct omap_target_agent_s *ta = 0;
 582     struct omap_l4_agent_info_s *info = 0;
 583
 584     for (i = 0; i < bus->ta_num; i++)
 585         if (omap3_l4_agent_info[i].ta == cs)
 586         {
 587             ta = &bus->ta[i];
 588             info = &omap3_l4_agent_info[i];
 589             break;
 590         }
 591     if (!ta)
 592     {
 593         fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs);
 594         exit(-1);
 595     }
 596
 597     ta->bus = bus;
 598     ta->start = &omap3_l4_region[info->region];
 599     ta->regions = info->regions;
 600
 601     ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
 602     ta->status = 0x00000000;
 603     ta->control = 0x00000200;   /* XXX 01000200 for L4TAO */
 604
 605     iomemtype = l4_register_io_memory(0, omap3_l4ta_readfn,
 606                                       omap3_l4ta_writefn, ta);
 607     ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);
 608
 609     return ta;
 610 }
 611
 612
 613 struct omap3_prm_s
 614 {
 615     qemu_irq mpu_irq;
 616     qemu_irq iva_irq;
 617     struct omap_mpu_state_s *mpu;
 618
 619     /*IVA2_PRM Register */
 620     uint32_t rm_rstctrl_iva2;    /*0x4830 6050 */
 621     uint32_t rm_rstst_iva2;      /*0x4830 6058 */
 622     uint32_t pm_wkdep_iva2;      /*0x4830 60C8 */
 623     uint32_t pm_pwstctrl_iva2;   /*0x4830 60E0 */
 624     uint32_t pm_pwstst_iva2;     /*0x4830 60E4 */
 625     uint32_t pm_prepwstst_iva2;  /*0x4830 60E8 */
 626     uint32_t prm_irqstatus_iva2; /*0x4830 60F8 */
 627     uint32_t prm_irqenable_iva2; /*0x4830 60FC */
 628
 629     /*OCP_System_Reg_PRM Register */
 630     uint32_t prm_revision;      /*0x4830 6804 */
 631     uint32_t prm_sysconfig;     /*0x4830 6814 */
 632     uint32_t prm_irqstatus_mpu; /*0x4830 6818 */
 633     uint32_t prm_irqenable_mpu; /*0x4830 681c */
 634
 635     /*MPU_PRM Register */
 636     uint32_t rm_rstst_mpu;      /*0x4830 6958 */
 637     uint32_t pm_wkdep_mpu;      /*0x4830 69c8 */
 638     uint32_t pm_evgenctrl_mpu;  /*0x4830 69d4 */
 639     uint32_t pm_evgenontim_mpu; /*0x4830 69d8 */
 640     uint32_t pm_evgenofftim_mpu;        /*0x4830 69dc */
 641     uint32_t pm_pwstctrl_mpu;   /*0x4830 69e0 */
 642     uint32_t pm_pwstst_mpu;     /*0x4830 69e4 */
 643     uint32_t pm_perpwstst_mpu;  /*0x4830 69e8 */
 644
 645     /*CORE_PRM Register */
 646     uint32_t rm_rstst_core;     /*0x4830 6a58 */
 647     uint32_t pm_wken1_core;     /*0x4830 6aa0 */
 648     uint32_t pm_mpugrpsel1_core;        /*0x4830 6aa4 */
 649     uint32_t pm_iva2grpsel1_core;       /*0x4830 6aa8 */
 650     uint32_t pm_wkst1_core;     /*0x4830 6ab0 */
 651     uint32_t pm_wkst3_core;     /*0x4830 6ab8 */
 652     uint32_t pm_pwstctrl_core;  /*0x4830 6ae0 */
 653     uint32_t pm_pwstst_core;    /*0x4830 6ae4 */
 654     uint32_t pm_prepwstst_core; /*0x4830 6ae8 */
 655     uint32_t pm_wken3_core;     /*0x4830 6af0 */
 656     uint32_t pm_iva2grpsel3_core;       /*0x4830 6af4 */
 657     uint32_t pm_mpugrpsel3_core;        /*0x4830 6af8 */
 658
 659     /*SGX_PRM Register */
 660     uint32_t rm_rstst_sgx;      /*0x4830 6b58 */
 661     uint32_t pm_wkdep_sgx;      /*0x4830 6bc8 */
 662     uint32_t pm_pwstctrl_sgx;   /*0x4830 6be0 */
 663     uint32_t pm_pwstst_sgx;     /*0x4830 6be4 */
 664     uint32_t pm_prepwstst_sgx;  /*0x4830 6be8 */
 665
 666     /*WKUP_PRM Register */
 667     uint32_t pm_wken_wkup;      /*0x4830 6ca0 */
 668     uint32_t pm_mpugrpsel_wkup; /*0x4830 6ca4 */
 669     uint32_t pm_iva2grpsel_wkup;        /*0x4830 6ca8 */
 670     uint32_t pm_wkst_wkup;      /*0x4830 6cb0 */
 671
 672     /*Clock_Control_Reg_PRM Register */
 673     uint32_t prm_clksel;        /*0x4830 6D40 */
 674     uint32_t prm_clkout_ctrl;   /*0x4830 6D70 */
 675
 676     /*DSS_PRM Register */
 677     uint32_t rm_rstst_dss;      /*0x4830 6e58 */
 678     uint32_t pm_wken_dss;       /*0x4830 6ea0 */
 679     uint32_t pm_wkdep_dss;      /*0x4830 6ec8 */
 680     uint32_t pm_pwstctrl_dss;   /*0x4830 6ee0 */
 681     uint32_t pm_pwstst_dss;     /*0x4830 6ee4 */
 682     uint32_t pm_prepwstst_dss;  /*0x4830 6ee8 */
 683
 684     /*CAM_PRM Register */
 685     uint32_t rm_rstst_cam;      /*0x4830 6f58 */
 686     uint32_t pm_wkdep_cam;      /*0x4830 6fc8 */
 687     uint32_t pm_pwstctrl_cam;   /*0x4830 6fe0 */
 688     uint32_t pm_pwstst_cam;     /*0x4830 6fe4 */
 689     uint32_t pm_prepwstst_cam;  /*0x4830 6fe8 */
 690
 691     /*PER_PRM Register */
 692     uint32_t rm_rstst_per;      /*0x4830 7058 */
 693     uint32_t pm_wken_per;       /*0x4830 70a0 */
 694     uint32_t pm_mpugrpsel_per;  /*0x4830 70a4 */
 695     uint32_t pm_iva2grpsel_per; /*0x4830 70a8 */
 696     uint32_t pm_wkst_per;       /*0x4830 70b0 */
 697     uint32_t pm_wkdep_per;      /*0x4830 70c8 */
 698     uint32_t pm_pwstctrl_per;   /*0x4830 70e0 */
 699     uint32_t pm_pwstst_per;     /*0x4830 70e4 */
 700     uint32_t pm_perpwstst_per;  /*0x4830 70e8 */
 701
 702     /*EMU_PRM Register */
 703     uint32_t rm_rstst_emu;      /*0x4830 7158 */
 704     uint32_t pm_pwstst_emu;     /*0x4830 71e4 */
 705
 706     /*Global_Reg_PRM Register */
 707     uint32_t prm_vc_smps_sa;    /*0x4830 7220 */
 708     uint32_t prm_vc_smps_vol_ra;        /*0x4830 7224 */
 709     uint32_t prm_vc_smps_cmd_ra;        /*0x4830 7228 */
 710     uint32_t prm_vc_cmd_val_0;  /*0x4830 722c */
 711     uint32_t prm_vc_cmd_val_1;  /*0x4830 7230 */
 712     uint32_t prm_vc_hc_conf;    /*0x4830 7234 */
 713     uint32_t prm_vc_i2c_cfg;    /*0x4830 7238 */
 714     uint32_t prm_vc_bypass_val; /*0x4830 723c */
 715     uint32_t prm_rstctrl;       /*0x4830 7250 */
 716     uint32_t prm_rsttimer;      /*0x4830 7254 */
 717     uint32_t prm_rstst;         /*0x4830 7258 */
 718     uint32_t prm_voltctrl;      /*0x4830 7260 */
 719     uint32_t prm_sram_pcharge;  /*0x4830 7264 */
 720     uint32_t prm_clksrc_ctrl;   /*0x4830 7270 */
 721     uint32_t prm_obs;           /*0x4830 7280 */
 722     uint32_t prm_voltsetup1;    /*0x4830 7290 */
 723     uint32_t prm_voltoffset;    /*0x4830 7294 */
 724     uint32_t prm_clksetup;      /*0x4830 7298 */
 725     uint32_t prm_polctrl;       /*0x4830 729c */
 726     uint32_t prm_voltsetup2;    /*0x4830 72a0 */
 727
 728     /*NEON_PRM Register */
 729     uint32_t rm_rstst_neon;     /*0x4830 7358 */
 730     uint32_t pm_wkdep_neon;     /*0x4830 73c8 */
 731     uint32_t pm_pwstctrl_neon;  /*0x4830 73e0 */
 732     uint32_t pm_pwstst_neon;    /*0x4830 73e4 */
 733     uint32_t pm_prepwstst_neon; /*0x4830 73e8 */
 734
 735     /*USBHOST_PRM Register */
 736     uint32_t rm_rstst_usbhost;  /*0x4830 7458 */
 737     uint32_t pm_wken_usbhost;   /*0x4830 74a0 */
 738     uint32_t pm_mpugrpsel_usbhost;      /*0x4830 74a4 */
 739     uint32_t pm_iva2grpsel_usbhost;     /*0x4830 74a8 */
 740     uint32_t pm_wkst_usbhost;   /*0x4830 74b0 */
 741     uint32_t pm_wkdep_usbhost;  /*0x4830 74c8 */
 742     uint32_t pm_pwstctrl_usbhost;       /*0x4830 74e0 */
 743     uint32_t pm_pwstst_usbhost; /*0x4830 74e4 */
 744     uint32_t pm_prepwstst_usbhost;      /*0x4830 74e8 */
 745
 746 };
 747
 748 static void omap3_prm_int_update(struct omap3_prm_s *s)
 749 {
 750     qemu_set_irq(s->mpu_irq, s->prm_irqstatus_mpu & s->prm_irqenable_mpu);
 751     qemu_set_irq(s->iva_irq, s->prm_irqstatus_iva2 & s->prm_irqenable_iva2);
 752 }
 753
 754 static void omap3_prm_reset(struct omap3_prm_s *s)
 755 {
 756     s->rm_rstctrl_iva2 = 0x7;
 757     s->rm_rstst_iva2 = 0x1;
 758     s->pm_wkdep_iva2 = 0xb3;
 759     s->pm_pwstctrl_iva2 = 0xff0f07;
 760     s->pm_pwstst_iva2 = 0xff7;
 761     s->pm_prepwstst_iva2 = 0x0;
 762     s->prm_irqstatus_iva2 = 0x0;
 763     s->prm_irqenable_iva2 = 0x0;
 764
 765     s->prm_revision = 0x10;
 766     s->prm_sysconfig = 0x1;
 767     s->prm_irqstatus_mpu = 0x0;
 768     s->prm_irqenable_mpu = 0x0;
 769
 770     s->rm_rstst_mpu = 0x1;
 771     s->pm_wkdep_mpu = 0xa5;
 772     s->pm_evgenctrl_mpu = 0x12;
 773     s->pm_evgenontim_mpu = 0x0;
 774     s->pm_evgenofftim_mpu = 0x0;
 775     s->pm_pwstctrl_mpu = 0x30107;
 776     s->pm_pwstst_mpu = 0xc7;
 777     s->pm_pwstst_mpu = 0x0;
 778
 779     s->rm_rstst_core = 0x1;
 780     s->pm_wken1_core = 0xc33ffe18;
 781     s->pm_mpugrpsel1_core = 0xc33ffe18;
 782     s->pm_iva2grpsel1_core = 0xc33ffe18;
 783     s->pm_wkst1_core = 0x0;
 784     s->pm_wkst3_core = 0x0;
 785     s->pm_pwstctrl_core = 0xf0307;
 786     s->pm_pwstst_core = 0xf7;
 787     s->pm_prepwstst_core = 0x0;
 788     s->pm_wken3_core = 0x4;
 789     s->pm_iva2grpsel3_core = 0x4;
 790     s->pm_mpugrpsel3_core = 0x4;
 791
 792     s->rm_rstst_sgx = 0x1;
 793     s->pm_wkdep_sgx = 0x16;
 794     s->pm_pwstctrl_sgx = 0x30107;
 795     s->pm_pwstst_sgx = 0x3;
 796     s->pm_prepwstst_sgx = 0x0;
 797
 798     s->pm_wken_wkup = 0x3cb;
 799     s->pm_mpugrpsel_wkup = 0x3cb;
 800     s->pm_iva2grpsel_wkup = 0x0;
 801     s->pm_wkst_wkup = 0x0;
 802
 803     s->prm_clksel = 0x4;
 804     s->prm_clkout_ctrl = 0x80;
 805
 806     s->rm_rstst_dss = 0x1;
 807     s->pm_wken_dss = 0x1;
 808     s->pm_wkdep_dss = 0x16;
 809     s->pm_pwstctrl_dss = 0x30107;
 810     s->pm_pwstst_dss = 0x3;
 811     s->pm_prepwstst_dss = 0x0;
 812
 813     s->rm_rstst_cam = 0x1;
 814     s->pm_wkdep_cam = 0x16;
 815     s->pm_pwstctrl_cam = 0x30107;
 816     s->pm_pwstst_cam = 0x3;
 817     s->pm_prepwstst_cam = 0x0;
 818
 819     s->rm_rstst_per = 0x1;
 820     s->pm_wken_per = 0x3efff;
 821     s->pm_mpugrpsel_per = 0x3efff;
 822     s->pm_iva2grpsel_per = 0x3efff;
 823     s->pm_wkst_per = 0x0;
 824     s->pm_wkdep_per = 0x17;
 825     s->pm_pwstctrl_per = 0x30107;
 826     s->pm_pwstst_per = 0x7;
 827     s->pm_perpwstst_per = 0x0;
 828
 829     s->rm_rstst_emu = 0x1;
 830     s->pm_pwstst_emu = 0x13;
 831
 832     s->prm_vc_smps_sa = 0x0;
 833     s->prm_vc_smps_vol_ra = 0x0;
 834     s->prm_vc_smps_cmd_ra = 0x0;
 835     s->prm_vc_cmd_val_0 = 0x0;
 836     s->prm_vc_cmd_val_1 = 0x0;
 837     s->prm_vc_hc_conf = 0x0;
 838     s->prm_vc_i2c_cfg = 0x18;
 839     s->prm_vc_bypass_val = 0x0;
 840     s->prm_rstctrl = 0x0;
 841     s->prm_rsttimer = 0x1006;
 842     s->prm_rstst = 0x1;
 843     s->prm_voltctrl = 0x0;
 844     s->prm_sram_pcharge = 0x50;
 845     s->prm_clksrc_ctrl = 0x43;
 846     s->prm_obs = 0x0;
 847     s->prm_voltsetup1 = 0x0;
 848     s->prm_voltoffset = 0x0;
 849     s->prm_clksetup = 0x0;
 850     s->prm_polctrl = 0xa;
 851     s->prm_voltsetup2 = 0x0;
 852
 853     s->rm_rstst_neon = 0x1;
 854     s->pm_wkdep_neon = 0x2;
 855     s->pm_pwstctrl_neon = 0x7;
 856     s->pm_pwstst_neon = 0x3;
 857     s->pm_prepwstst_neon = 0x0;
 858
 859     s->rm_rstst_usbhost = 0x1;
 860     s->pm_wken_usbhost = 0x1;
 861     s->pm_mpugrpsel_usbhost = 0x1;
 862     s->pm_iva2grpsel_usbhost = 0x1;
 863     s->pm_wkst_usbhost = 0x0;
 864     s->pm_wkdep_usbhost = 0x17;
 865     s->pm_pwstctrl_usbhost = 0x30107;
 866     s->pm_pwstst_usbhost = 0x3;
 867     s->pm_prepwstst_usbhost = 0x0;
 868
 869     omap3_prm_int_update(s);
 870 }
 871
 872 static uint32_t omap3_prm_read(void *opaque, target_phys_addr_t addr)
 873 {
 874     struct omap3_prm_s *s = (struct omap3_prm_s *)opaque;
 875
 876     TRACE("%04x", addr);
 877     switch (addr) {
 878         /* IVA2_PRM */
 879         case 0x0050: return s->rm_rstctrl_iva2;
 880         case 0x0058: return s->rm_rstst_iva2;
 881         case 0x00c8: return s->pm_wkdep_iva2;
 882         case 0x00e0: return s->pm_pwstctrl_iva2;
 883         case 0x00e4: return s->pm_pwstst_iva2;
 884         case 0x00e8: return s->pm_prepwstst_iva2;
 885         case 0x00f8: return s->prm_irqstatus_iva2;
 886         case 0x00fc: return s->prm_irqenable_iva2;
 887         /* OCP_System_Reg_PRM */
 888         case 0x0804: return s->prm_revision;
 889         case 0x0814: return s->prm_sysconfig;
 890         case 0x0818: return s->prm_irqstatus_mpu;
 891         case 0x081c: return s->prm_irqenable_mpu;
 892         /* MPU_PRM */
 893         case 0x0958: return s->rm_rstst_mpu;
 894         case 0x09c8: return s->pm_wkdep_mpu;
 895         case 0x09d4: return s->pm_evgenctrl_mpu;
 896         case 0x09d8: return s->pm_evgenontim_mpu;
 897         case 0x09dc: return s->pm_evgenofftim_mpu;
 898         case 0x09e0: return s->pm_pwstctrl_mpu;
 899         case 0x09e4: return s->pm_pwstst_mpu;
 900         case 0x09e8: return s->pm_perpwstst_mpu;
 901         /* CORE_PRM */
 902         case 0x0a58: return s->rm_rstst_core;
 903         case 0x0aa0: return s->pm_wken1_core;
 904         case 0x0aa4: return s->pm_mpugrpsel1_core;
 905         case 0x0aa8: return s->pm_iva2grpsel1_core;
 906         case 0x0ab0: return s->pm_wkst1_core;
 907         case 0x0ab8: return s->pm_wkst3_core;
 908         case 0x0ae0: return s->pm_pwstctrl_core;
 909         case 0x0ae4: return s->pm_pwstst_core;
 910         case 0x0ae8: return s->pm_prepwstst_core;
 911         case 0x0af0: return s->pm_wken3_core;
 912         case 0x0af4: return s->pm_iva2grpsel3_core;
 913         case 0x0af8: return s->pm_mpugrpsel3_core;
 914         /* SGX_PRM */
 915         case 0x0b58: return s->rm_rstst_sgx;
 916         case 0x0bc8: return s->pm_wkdep_sgx;
 917         case 0x0be0: return s->pm_pwstctrl_sgx;
 918         case 0x0be4: return s->pm_pwstst_sgx;
 919         case 0x0be8: return s->pm_prepwstst_sgx;
 920         /* WKUP_PRM */
 921         case 0x0ca0: return s->pm_wken_wkup;
 922         case 0x0ca4: return s->pm_mpugrpsel_wkup;
 923         case 0x0ca8: return s->pm_iva2grpsel_wkup;
 924         case 0x0cb0: return s->pm_wkst_wkup;
 925         //case 0x0ce4: return 0x3; /* power on */
 926         /* Clock_Control_Reg_PRM */
 927         case 0x0d40: return s->prm_clksel;
 928         case 0x0d70: return s->prm_clkout_ctrl;
 929         //case 0x0de4: return 0x3; /* power on */
 930         /* DSS_PRM */
 931         case 0x0e58: return s->rm_rstst_dss;
 932         case 0x0ea0: return s->pm_wken_dss;
 933         case 0x0ec8: return s->pm_wkdep_dss;
 934         case 0x0ee0: return s->pm_pwstctrl_dss;
 935         case 0x0ee4: return s->pm_pwstst_dss;
 936         case 0x0ee8: return s->pm_prepwstst_dss;
 937         /* CAM_PRM */
 938         case 0x0f58: return s->rm_rstst_cam;
 939         case 0x0fc8: return s->pm_wkdep_cam;
 940         case 0x0fe0: return s->pm_pwstctrl_cam;
 941         case 0x0fe4: return s->pm_pwstst_cam;
 942         case 0x0fe8: return s->pm_prepwstst_cam;
 943         /* PER_PRM */
 944         case 0x1058: return s->rm_rstst_per;
 945         case 0x10a0: return s->pm_wken_per;
 946         case 0x10a4: return s->pm_mpugrpsel_per;
 947         case 0x10a8: return s->pm_iva2grpsel_per;
 948         case 0x10b0: return s->pm_wkst_per;
 949         case 0x10c8: return s->pm_wkdep_per;
 950         case 0x10e0: return s->pm_pwstctrl_per;
 951         case 0x10e4: return s->pm_pwstst_per;
 952         case 0x10e8: return s->pm_perpwstst_per;
 953         /* EMU_PRM */
 954         case 0x1158: return s->rm_rstst_emu;
 955         case 0x11e4: return s->pm_pwstst_emu;
 956         /* Global_Reg_PRM */
 957         case 0x1220: return s->prm_vc_smps_sa;
 958         case 0x1224: return s->prm_vc_smps_vol_ra;
 959         case 0x1228: return s->prm_vc_smps_cmd_ra;
 960         case 0x122c: return s->prm_vc_cmd_val_0;
 961         case 0x1230: return s->prm_vc_cmd_val_1;
 962         case 0x1234: return s->prm_vc_hc_conf;
 963         case 0x1238: return s->prm_vc_i2c_cfg;
 964         case 0x123c: return s->prm_vc_bypass_val;
 965         case 0x1250: return s->prm_rstctrl;
 966         case 0x1254: return s->prm_rsttimer;
 967         case 0x1258: return s->prm_rstst;
 968         case 0x1260: return s->prm_voltctrl;
 969         case 0x1264: return s->prm_sram_pcharge;
 970         case 0x1270: return s->prm_clksrc_ctrl;
 971         case 0x1280: return s->prm_obs;
 972         case 0x1290: return s->prm_voltsetup1;
 973         case 0x1294: return s->prm_voltoffset;
 974         case 0x1298: return s->prm_clksetup;
 975         case 0x129c: return s->prm_polctrl;
 976         case 0x12a0: return s->prm_voltsetup2;
 977         /* NEON_PRM */
 978         case 0x1358: return s->rm_rstst_neon;
 979         case 0x13c8: return s->pm_wkdep_neon;
 980         case 0x13e0: return s->pm_pwstctrl_neon;
 981         case 0x13e4: return s->pm_pwstst_neon;
 982         case 0x13e8: return s->pm_prepwstst_neon;
 983         /* USBHOST_PRM */
 984         case 0x1458: return s->rm_rstst_usbhost;
 985         case 0x14a0: return s->pm_wken_usbhost;
 986         case 0x14a4: return s->pm_mpugrpsel_usbhost;
 987         case 0x14a8: return s->pm_iva2grpsel_usbhost;
 988         case 0x14b0: return s->pm_wkst_usbhost;
 989         case 0x14c8: return s->pm_wkdep_usbhost;
 990         case 0x14e0: return s->pm_pwstctrl_usbhost;
 991         case 0x14e4: return s->pm_pwstst_usbhost;
 992         case 0x14e8: return s->pm_prepwstst_usbhost;
 993         default:
 994             OMAP_BAD_REG(addr);
 995             return 0;
 996     }
 997 }
 998
 999 static inline void omap3_prm_clksrc_ctrl_update(struct omap3_prm_s *s,
1000                                                 uint32_t value)
1001 {
1002     if ((value & 0xd0) == 0x40)
1003         omap_clk_setrate(omap_findclk(s->mpu, "omap3_sys_clk"), 1, 1);
1004     else if ((value & 0xd0) == 0x80)
1005         omap_clk_setrate(omap_findclk(s->mpu, "omap3_sys_clk"), 2, 1);
1006 }
1007
1008 static void omap3_prm_write(void *opaque, target_phys_addr_t addr,
1009                             uint32_t value)
1010 {
1011     struct omap3_prm_s *s = (struct omap3_prm_s *)opaque;
1012
1013     TRACE("%04x = %08x", addr, value);
1014     switch (addr) {
1015         /* IVA2_PRM */
1016         case 0x0050: s->rm_rstctrl_iva2 = value & 0x7; break;
1017         case 0x0058: s->rm_rstst_iva2 &= ~(value & 0x3f0f); break;
1018         case 0x00c8: s->pm_wkdep_iva2 = value & 0xb3; break;
1019         case 0x00e0: s->pm_pwstctrl_iva2 = 0xcff000 | (value & 0x300f0f); break;
1020         case 0x00e4: OMAP_RO_REG(addr); break;
1021         case 0x00e8: s->pm_prepwstst_iva2 = value & 0xff7;
1022         case 0x00f8:
1023             s->prm_irqstatus_iva2 &= ~(value & 0x7);
1024             omap3_prm_int_update(s);
1025             break;
1026         case 0x00fc:
1027             s->prm_irqenable_iva2 = value & 0x7;
1028             omap3_prm_int_update(s);
1029             break;
1030         /* OCP_System_Reg_PRM */
1031         case 0x0804: OMAP_RO_REG(addr); break;
1032         case 0x0814: s->prm_sysconfig = value & 0x1; break;
1033         case 0x0818:
1034             s->prm_irqstatus_mpu &= ~(value & 0x03c003fd);
1035             omap3_prm_int_update(s);
1036             break;
1037         case 0x081c:
1038             s->prm_irqenable_mpu = value & 0x03c003fd;
1039             omap3_prm_int_update(s);
1040             break;
1041         /* MPU_PRM */
1042         case 0x0958: s->rm_rstst_mpu &= ~(value & 0x080f); break;
1043         case 0x09c8: s->pm_wkdep_mpu = value & 0xa5; break;
1044         case 0x09d4: s->pm_evgenctrl_mpu = value & 0x1f; break;
1045         case 0x09d8: s->pm_evgenontim_mpu = value; break;
1046         case 0x09dc: s->pm_evgenofftim_mpu = value; break;
1047         case 0x09e0: s->pm_pwstctrl_mpu = value & 0x3010f; break;
1048         case 0x09e4: OMAP_RO_REG(addr); break;
1049         case 0x09e8: s->pm_perpwstst_mpu = value & 0xc7; break;
1050         /* CORE_PRM */
1051         case 0x0a58: s->rm_rstst_core &= ~(value & 0x7); break;
1052         case 0x0aa0: s->pm_wken1_core = 0x80000008 | (value & 0x433ffe10); break;
1053         case 0x0aa4: s->pm_mpugrpsel1_core = 0x80000008 | (value & 0x433ffe10); break;
1054         case 0x0aa8: s->pm_iva2grpsel1_core = 0x80000008 | (value & 0x433ffe10); break;
1055         case 0x0ab0: s->pm_wkst1_core = value & 0x433ffe10; break;
1056         case 0x0ab8: s->pm_wkst3_core &= ~(value & 0x4); break;
1057         case 0x0ae0: s->pm_pwstctrl_core = (value & 0x0f031f); break;
1058         case 0x0ae4: OMAP_RO_REG(addr); break;
1059         case 0x0ae8: s->pm_prepwstst_core = value & 0xf7; break;
1060         case 0x0af0: s->pm_wken3_core = value & 0x4; break;
1061         case 0x0af4: s->pm_iva2grpsel3_core = value & 0x4; break;
1062         case 0x0af8: s->pm_mpugrpsel3_core = value & 0x4; break;
1063         /* SGX_PRM */
1064         case 0x0b58: s->rm_rstst_sgx &= ~(value & 0xf); break;
1065         case 0x0bc8: s->pm_wkdep_sgx = value & 0x16; break;
1066         case 0x0be0: s->pm_pwstctrl_sgx = 0x030104 | (value & 0x3); break;
1067         case 0x0be4: OMAP_RO_REG(addr); break;
1068         case 0x0be8: s->pm_prepwstst_sgx = value & 0x3; break;
1069         /* WKUP_PRM */
1070         case 0x0ca0: s->pm_wken_wkup = 0x2 | (value & 0x0103c9); break;
1071         case 0x0ca4: s->pm_mpugrpsel_wkup = 0x0102 | (value & 0x02c9); break;
1072         case 0x0ca8: s->pm_iva2grpsel_wkup = value & 0x03cb; break;
1073         case 0x0cb0: s->pm_wkst_wkup &= ~(value & 0x0103cb); break;
1074         /* Clock_Control_Reg_PRM */
1075         case 0x0d40:
1076             s->prm_clksel = value & 0x7;
1077             fprintf(stderr, "%s PRM_CLKSEL = 0x%x\n", __FUNCTION__,
1078                     s->prm_clksel);
1079             /* TODO: update clocks */
1080             break;
1081         case 0x0d70:
1082             s->prm_clkout_ctrl = value & 0x80;
1083             fprintf(stderr, "%s PRM_CLKOUT_CTRL = 0x%x\n", __FUNCTION__,
1084                     s->prm_clkout_ctrl);
1085             /* TODO: update clocks */
1086             break;
1087         /* DSS_PRM */
1088         case 0x0e58: s->rm_rstst_dss &= ~(value & 0xf); break;
1089         case 0x0ea0: s->pm_wken_dss = value & 1; break;
1090         case 0x0ec8: s->pm_wkdep_dss = value & 0x16; break;
1091         case 0x0ee0: s->pm_pwstctrl_dss = 0x030104 | (value & 3); break;
1092         case 0x0ee4: OMAP_RO_REG(addr); break;
1093         case 0x0ee8: s->pm_prepwstst_dss = value & 3; break;
1094         /* CAM_PRM */
1095         case 0x0f58: s->rm_rstst_cam &= (value & 0xf); break;
1096         case 0x0fc8: s->pm_wkdep_cam = value & 0x16; break;
1097         case 0x0fe0: s->pm_pwstctrl_cam = 0x030104 | (value & 3); break;
1098         case 0x0fe4: OMAP_RO_REG(addr); break;
1099         case 0x0fe8: s->pm_prepwstst_cam = value & 0x3; break;
1100         /* PER_PRM */
1101         case 0x1058: s->rm_rstst_per &= ~(value & 0xf); break;
1102         case 0x10a0: s->pm_wken_per = value & 0x03efff; break;
1103         case 0x10a4: s->pm_mpugrpsel_per = value & 0x03efff; break;
1104         case 0x10a8: s->pm_iva2grpsel_per = value & 0x03efff; break;
1105         case 0x10b0: s->pm_wkst_per &= ~(value & 0x03efff); break;
1106         case 0x10c8: s->pm_wkdep_per = value & 0x17; break;
1107         case 0x10e0: s->pm_pwstctrl_per = 0x030100 | (value & 7); break;
1108         case 0x10e4: OMAP_RO_REG(addr); break;
1109         case 0x10e8: s->pm_perpwstst_per = value & 0x7; break;
1110         /* EMU_PRM */
1111         case 0x1158: s->rm_rstst_emu &= ~(value & 7); break;
1112         case 0x11e4: OMAP_RO_REG(addr); break;
1113         /* Global_Reg_PRM */
1114         case 0x1220: s->prm_vc_smps_sa = value & 0x7f007f; break;
1115         case 0x1224: s->prm_vc_smps_vol_ra = value & 0xff00ff; break;
1116         case 0x1228: s->prm_vc_smps_cmd_ra = value & 0xff00ff; break;
1117         case 0x122c: s->prm_vc_cmd_val_0 = value; break;
1118         case 0x1230: s->prm_vc_cmd_val_1 = value; break;
1119         case 0x1234: s->prm_vc_hc_conf = value & 0x1f001f; break;
1120         case 0x1238: s->prm_vc_i2c_cfg = value & 0x3f; break;
1121         case 0x123c: s->prm_vc_bypass_val = value & 0x01ffff7f; break;
1122         case 0x1250: s->prm_rstctrl = 0; break; /* TODO: resets */
1123         case 0x1254: s->prm_rsttimer = value & 0x1fff; break;
1124         case 0x1258: s->prm_rstst &= ~(value & 0x7fb); break;
1125         case 0x1260: s->prm_voltctrl = value & 0x1f; break;
1126         case 0x1264: s->prm_sram_pcharge = value & 0xff; break;
1127         case 0x1270:
1128             s->prm_clksrc_ctrl = value & (0xd8);
1129             omap3_prm_clksrc_ctrl_update(s, s->prm_clksrc_ctrl);
1130             /* TODO: update SYSCLKSEL bits */
1131             break;
1132         case 0x1280: OMAP_RO_REG(addr); break;
1133         case 0x1290: s->prm_voltsetup1 = value; break;
1134         case 0x1294: s->prm_voltoffset = value & 0xffff; break;
1135         case 0x1298: s->prm_clksetup = value & 0xffff; break;
1136         case 0x129c: s->prm_polctrl = value & 0xf; break;
1137         case 0x12a0: s->prm_voltsetup2 = value & 0xffff; break;
1138         /* NEON_PRM */
1139         case 0x1358: s->rm_rstst_neon &= ~(value & 0xf); break;
1140         case 0x13c8: s->pm_wkdep_neon = value & 0x2; break;
1141         case 0x13e0: s->pm_pwstctrl_neon = 0x4 | (value & 3); break;
1142         case 0x13e4: OMAP_RO_REG(addr); break;
1143         case 0x13e8: s->pm_prepwstst_neon = value & 3; break;
1144         /* USBHOST_PRM */
1145         case 0x1458: s->rm_rstst_usbhost &= ~(value & 0xf); break;
1146         case 0x14a0: s->pm_wken_usbhost = value & 1; break;
1147         case 0x14a4: s->pm_mpugrpsel_usbhost = value & 1; break;
1148         case 0x14a8: s->pm_iva2grpsel_usbhost = value & 1; break;
1149         case 0x14b0: s->pm_wkst_usbhost &= ~(value & 1); break;
1150         case 0x14c8: s->pm_wkdep_usbhost = value & 0x17; break;
1151         case 0x14e0: s->pm_pwstctrl_usbhost = 0x030104 | (value & 0x13); break;
1152         case 0x14e4: OMAP_RO_REG(addr); break;
1153         case 0x14e8: s->pm_prepwstst_usbhost = value & 3; break;
1154         default:
1155             OMAP_BAD_REGV(addr, value);
1156             break;
1157     }
1158 }
1159
1160 static CPUReadMemoryFunc *omap3_prm_readfn[] = {
1161     omap_badwidth_read32,
1162     omap_badwidth_read32,
1163     omap3_prm_read,
1164 };
1165
1166 static CPUWriteMemoryFunc *omap3_prm_writefn[] = {
1167     omap_badwidth_write32,
1168     omap_badwidth_write32,
1169     omap3_prm_write,
1170 };
1171
1172 struct omap3_prm_s *omap3_prm_init(struct omap_target_agent_s *ta,
1173                                    qemu_irq mpu_int, qemu_irq iva_int,
1174                                    struct omap_mpu_state_s *mpu)
1175 {
1176     int iomemtype;
1177     struct omap3_prm_s *s = (struct omap3_prm_s *) qemu_mallocz(sizeof(*s));
1178
1179     s->mpu_irq = mpu_int;
1180     s->iva_irq = iva_int;
1181     s->mpu = mpu;
1182     omap3_prm_reset(s);
1183
1184     iomemtype = l4_register_io_memory(0, omap3_prm_readfn,
1185                                       omap3_prm_writefn, s);
1186     omap_l4_attach(ta, 0, iomemtype);
1187     omap_l4_attach(ta, 1, iomemtype);
1188
1189     return s;
1190 }
1191
1192
1193 struct omap3_cm_s
1194 {
1195     qemu_irq irq[3];
1196     struct omap_mpu_state_s *mpu;
1197
1198     /*IVA2_CM Register */
1199     uint32_t cm_fclken_iva2;    /*0x4800 4000 */
1200     uint32_t cm_clken_pll_iva2; /*0x4800 4004 */
1201     uint32_t cm_idlest_iva2;    /*0x4800 4020 */
1202     uint32_t cm_idlest_pll_iva2;        /*0x4800 4024 */
1203     uint32_t cm_autoidle_pll_iva2;      /*0x4800 4034 */
1204     uint32_t cm_clksel1_pll_iva2;       /*0x4800 4040 */
1205     uint32_t cm_clksel2_pll_iva2;       /*0x4800 4044 */
1206     uint32_t cm_clkstctrl_iva2; /*0x4800 4048 */
1207     uint32_t cm_clkstst_iva2;   /*0x4800 404c */
1208
1209     /*OCP_System_Reg_CM */
1210     uint32_t cm_revision;       /*0x4800 4800 */
1211     uint32_t cm_sysconfig;      /*0x4800 4810 */
1212
1213     /*MPU_CM Register */
1214     uint32_t cm_clken_pll_mpu;  /*0x4800 4904 */
1215     uint32_t cm_idlest_mpu;     /*0x4800 4920 */
1216     uint32_t cm_idlest_pll_mpu; /*0x4800 4924 */
1217     uint32_t cm_autoidle_pll_mpu;       /*0x4800 4934 */
1218     uint32_t cm_clksel1_pll_mpu;        /*0x4800 4940 */
1219     uint32_t cm_clksel2_pll_mpu;        /*0x4800 4944 */
1220     uint32_t cm_clkstctrl_mpu;  /*0x4800 4948 */
1221     uint32_t cm_clkstst_mpu;    /*0x4800 494c */
1222
1223     /*CORE_CM Register */
1224     uint32_t cm_fclken1_core;   /*0x4800 4a00 */
1225     uint32_t cm_fclken3_core;   /*0x4800 4a08 */
1226     uint32_t cm_iclken1_core;   /*0x4800 4a10 */
1227     uint32_t cm_iclken2_core;   /*0x4800 4a14 */
1228     uint32_t cm_iclken3_core;   /*0x4800 4a18 */
1229     uint32_t cm_idlest1_core;   /*0x4800 4a20 */
1230     uint32_t cm_idlest2_core;   /*0x4800 4a24 */
1231     uint32_t cm_idlest3_core;   /*0x4800 4a28 */
1232     uint32_t cm_autoidle1_core; /*0x4800 4a30 */
1233     uint32_t cm_autoidle2_core; /*0x4800 4a34 */
1234     uint32_t cm_autoidle3_core; /*0x4800 4a38 */
1235     uint32_t cm_clksel_core;    /*0x4800 4a40 */
1236     uint32_t cm_clkstctrl_core; /*0x4800 4a48 */
1237     uint32_t cm_clkstst_core;   /*0x4800 4a4c */
1238
1239     /*SGX_CM Register */
1240     uint32_t cm_fclken_sgx;     /*0x4800 4b00 */
1241     uint32_t cm_iclken_sgx;     /*0x4800 4b10 */
1242     uint32_t cm_idlest_sgx;     /*0x4800 4b20 */
1243     uint32_t cm_clksel_sgx;     /*0x4800 4b40 */
1244     uint32_t cm_sleepdep_sgx;   /*0x4800 4b44 */
1245     uint32_t cm_clkstctrl_sgx;  /*0x4800 4b48 */
1246     uint32_t cm_clkstst_sgx;    /*0x4800 4b4c */
1247
1248     /*WKUP_CM Register */
1249     uint32_t cm_fclken_wkup;    /*0x4800 4c00 */
1250     uint32_t cm_iclken_wkup;    /*0x4800 4c10 */
1251     uint32_t cm_idlest_wkup;    /*0x4800 4c20 */
1252     uint32_t cm_autoidle_wkup;  /*0x4800 4c30 */
1253     uint32_t cm_clksel_wkup;    /*0x4800 4c40 */
1254     uint32_t cm_c48;                  /*0x4800 4c48 */
1255
1256     /*Clock_Control_Reg_CM Register */
1257     uint32_t cm_clken_pll;      /*0x4800 4d00 */
1258     uint32_t cm_clken2_pll;     /*0x4800 4d04 */
1259     uint32_t cm_idlest_ckgen;   /*0x4800 4d20 */
1260     uint32_t cm_idlest2_ckgen;  /*0x4800 4d24 */
1261     uint32_t cm_autoidle_pll;   /*0x4800 4d30 */
1262     uint32_t cm_autoidle2_pll;  /*0x4800 4d34 */
1263     uint32_t cm_clksel1_pll;    /*0x4800 4d40 */
1264     uint32_t cm_clksel2_pll;    /*0x4800 4d44 */
1265     uint32_t cm_clksel3_pll;    /*0x4800 4d48 */
1266     uint32_t cm_clksel4_pll;    /*0x4800 4d4c */
1267     uint32_t cm_clksel5_pll;    /*0x4800 4d50 */
1268     uint32_t cm_clkout_ctrl;    /*0x4800 4d70 */
1269
1270     /*DSS_CM Register */
1271     uint32_t cm_fclken_dss;     /*0x4800 4e00 */
1272     uint32_t cm_iclken_dss;     /*0x4800 4e10 */
1273     uint32_t cm_idlest_dss;     /*0x4800 4e20 */
1274     uint32_t cm_autoidle_dss;   /*0x4800 4e30 */
1275     uint32_t cm_clksel_dss;     /*0x4800 4e40 */
1276     uint32_t cm_sleepdep_dss;   /*0x4800 4e44 */
1277     uint32_t cm_clkstctrl_dss;  /*0x4800 4e48 */
1278     uint32_t cm_clkstst_dss;    /*0x4800 4e4c */
1279
1280
1281     /*CAM_CM Register */
1282     uint32_t cm_fclken_cam;     /*0x4800 4f00 */
1283     uint32_t cm_iclken_cam;     /*0x4800 4f10 */
1284     uint32_t cm_idlest_cam;     /*0x4800 4f20 */
1285     uint32_t cm_autoidle_cam;   /*0x4800 4f30 */
1286     uint32_t cm_clksel_cam;     /*0x4800 4f40 */
1287     uint32_t cm_sleepdep_cam;   /*0x4800 4f44 */
1288     uint32_t cm_clkstctrl_cam;  /*0x4800 4f48 */
1289     uint32_t cm_clkstst_cam;    /*0x4800 4f4c */
1290
1291     /*PER_CM Register */
1292     uint32_t cm_fclken_per;     /*0x4800 5000 */
1293     uint32_t cm_iclken_per;     /*0x4800 5010 */
1294     uint32_t cm_idlest_per;     /*0x4800 5020 */
1295     uint32_t cm_autoidle_per;   /*0x4800 5030 */
1296     uint32_t cm_clksel_per;     /*0x4800 5040 */
1297     uint32_t cm_sleepdep_per;   /*0x4800 5044 */
1298     uint32_t cm_clkstctrl_per;  /*0x4800 5048 */
1299     uint32_t cm_clkstst_per;    /*0x4800 504c */
1300
1301     /*EMU_CM Register */
1302     uint32_t cm_clksel1_emu;    /*0x4800 5140 */
1303     uint32_t cm_clkstctrl_emu;  /*0x4800 5148 */
1304     uint32_t cm_clkstst_emu;    /*0x4800 514c */
1305     uint32_t cm_clksel2_emu;    /*0x4800 5150 */
1306     uint32_t cm_clksel3_emu;    /*0x4800 5154 */
1307
1308     /*Global_Reg_CM Register */
1309     uint32_t cm_polctrl;        /*0x4800 529c */
1310
1311     /*NEON_CM Register */
1312     uint32_t cm_idlest_neon;    /*0x4800 5320 */
1313     uint32_t cm_clkstctrl_neon; /*0x4800 5348 */
1314
1315     /*USBHOST_CM Register */
1316     uint32_t cm_fclken_usbhost; /*0x4800 5400 */
1317     uint32_t cm_iclken_usbhost; /*0x4800 5410 */
1318     uint32_t cm_idlest_usbhost; /*0x4800 5420 */
1319     uint32_t cm_autoidle_usbhost;       /*0x4800 5430 */
1320     uint32_t cm_sleepdep_usbhost;       /*0x4800 5444 */
1321     uint32_t cm_clkstctrl_usbhost;      /*0x4800 5448 */
1322     uint32_t cm_clkstst_usbhost;        /*0x4800 544c */
1323
1324 };
1325
1326 /*
1327 static inline void omap3_cm_fclken_wkup_update(struct omap3_cm_s *s,
1328                 uint32_t value)
1329 {
1330
1331         if (value & 0x28)
1332         omap_clk_onoff(omap_findclk(s->mpu,"omap3_wkup_32k_fclk"), 1);
1333     else
1334         omap_clk_onoff(omap_findclk(s->mpu,"omap3_wkup_32k_fclk"), 0);
1335
1336     if (value &0x1)
1337         omap_clk_onoff(omap_findclk(s->mpu,"omap3_gp1_fclk"), 1);
1338     else
1339         omap_clk_onoff(omap_findclk(s->mpu,"omap3_gp1_fclk"), 0);
1340
1341 }
1342 static inline void omap3_cm_iclken_wkup_update(struct omap3_cm_s *s,
1343                 uint32_t value)
1344 {
1345
1346         if (value & 0x3f)
1347         omap_clk_onoff(omap_findclk(s->mpu,"omap3_wkup_l4_iclk"), 1);
1348     else
1349         omap_clk_onoff(omap_findclk(s->mpu,"omap3_wkup_l4_iclk"), 0);
1350
1351 }
1352 */
1353 static inline void omap3_cm_clksel_wkup_update(struct omap3_cm_s *s,
1354                                                uint32_t value)
1355 {
1356     omap_clk gp1_fclk = omap_findclk(s->mpu, "omap3_gp1_fclk");
1357
1358     if (value & 0x1)
1359         omap_clk_reparent(gp1_fclk, omap_findclk(s->mpu, "omap3_sys_clk"));
1360     else
1361         omap_clk_reparent(gp1_fclk, omap_findclk(s->mpu, "omap3_32k_fclk"));
1362     /*Tell GPTIMER to generate new clk rate */
1363     omap_gp_timer_change_clk(s->mpu->gptimer[0]);
1364
1365     TRACE("omap3_gp1_fclk %lld",
1366           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp1_fclk")));
1367
1368     /*TODO:CM_USIM_CLK CLKSEL_RM */
1369 }
1370
1371 static inline void omap3_cm_mpu_update(struct omap3_cm_s *s)
1372 {
1373     uint32_t m, n, divide, m2, cm_clken_pll_mpu;
1374     uint32_t bypass = 1;
1375
1376     cm_clken_pll_mpu = s->cm_clken_pll_mpu;
1377     omap_clk mpu_clk = omap_findclk(s->mpu, "omap3_mpu_clk");
1378
1379     if ((cm_clken_pll_mpu & 0x7) == 0x5)
1380     {
1381         bypass = 1;
1382     }
1383     else if ((cm_clken_pll_mpu & 0x7) == 0x7)
1384     {
1385         m = (s->cm_clksel1_pll_mpu & 0x7ff00) >> 8;
1386         if ((m == 0) || (m == 1))
1387             bypass = 1;
1388         else
1389             bypass = 0;
1390     }
1391     if (bypass == 1)
1392     {
1393         /*BYPASS Model */
1394         divide = (s->cm_clksel1_pll_mpu & 0x380000) >> 19;
1395         //OMAP3_DEBUG(("divide %d\n",divide));
1396         omap_clk_reparent(mpu_clk, omap_findclk(s->mpu, "omap3_core_clk"));
1397         omap_clk_setrate(mpu_clk, divide, 1);
1398
1399     }
1400     else
1401     {
1402         n = (s->cm_clksel1_pll_mpu & 0x7F);
1403         m2 = (s->cm_clksel2_pll_mpu & 0x1F);
1404         //OMAP3_DEBUG(("M  %d N %d M2 %d \n",m,n,m2 ));
1405         omap_clk_reparent(mpu_clk, omap_findclk(s->mpu, "omap3_sys_clk"));
1406         omap_clk_setrate(mpu_clk, (n + 1) * m2, m);
1407         //OMAP3_DEBUG(("mpu %d \n",omap_clk_getrate(mpu_clk)));
1408
1409     }
1410
1411 }
1412 static inline void omap3_cm_iva2_update(struct omap3_cm_s *s)
1413 {
1414     uint32_t m, n, divide, m2, cm_clken_pll_iva2;
1415     uint32_t bypass = 1;
1416
1417     cm_clken_pll_iva2 = s->cm_clken_pll_iva2;
1418     omap_clk iva2_clk = omap_findclk(s->mpu, "omap3_iva2_clk");
1419
1420     if (((cm_clken_pll_iva2 & 0x7) == 0x5)
1421         || ((cm_clken_pll_iva2 & 0x7) == 0x1))
1422     {
1423         bypass = 1;
1424     }
1425     else if ((cm_clken_pll_iva2 & 0x7) == 0x7)
1426     {
1427         m = (s->cm_clksel1_pll_iva2 & 0x7ff00) >> 8;
1428         if ((m == 0) || (m == 1))
1429             bypass = 1;
1430         else
1431             bypass = 0;
1432     }
1433     if (bypass == 1)
1434     {
1435         /*BYPASS Model */
1436         divide = (s->cm_clksel1_pll_iva2 & 0x380000) >> 19;
1437         //OMAP3_DEBUG(("divide %d\n",divide));
1438         omap_clk_reparent(iva2_clk, omap_findclk(s->mpu, "omap3_core_clk"));
1439         omap_clk_setrate(iva2_clk, divide, 1);
1440
1441     }
1442     else
1443     {
1444         n = (s->cm_clksel1_pll_iva2 & 0x7F);
1445         m2 = (s->cm_clksel2_pll_iva2 & 0x1F);
1446         //OMAP3_DEBUG(("M  %d N %d M2 %d \n",m,n,m2 ));
1447         omap_clk_reparent(iva2_clk, omap_findclk(s->mpu, "omap3_sys_clk"));
1448         omap_clk_setrate(iva2_clk, (n + 1) * m2, m);
1449         //OMAP3_DEBUG(("iva2_clk %d \n",omap_clk_getrate(iva2_clk)));
1450
1451     }
1452
1453 }
1454
1455 static inline void omap3_cm_dpll3_update(struct omap3_cm_s *s)
1456 {
1457     uint32_t m, n, m2, m3, cm_clken_pll;
1458     uint32_t bypass = 1;
1459
1460     cm_clken_pll = s->cm_clken_pll;
1461
1462     /*dpll3 bypass mode. parent clock is always omap3_sys_clk */
1463     if (((cm_clken_pll & 0x7) == 0x5) || ((cm_clken_pll & 0x7) == 0x6))
1464     {
1465         bypass = 1;
1466     }
1467     else if ((cm_clken_pll & 0x7) == 0x7)
1468     {
1469         m = (s->cm_clksel1_pll & 0x7ff0000) >> 16;
1470         if ((m == 0) || (m == 1))
1471             bypass = 1;
1472         else
1473             bypass = 0;
1474     }
1475     if (bypass == 1)
1476     {
1477         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core_clk"), 1, 1);
1478         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core2_clk"), 1, 1);
1479         omap_clk_setrate(omap_findclk(s->mpu, "omap3_emu_core_alwon_clk"), 1,
1480                          1);
1481     }
1482     else
1483     {
1484         n = (s->cm_clksel1_pll & 0x3f00) >> 8;
1485         m2 = (s->cm_clksel1_pll & 0xf8000000) >> 27;
1486         m3 = (s->cm_clksel1_emu & 0x1f0000) >> 16;
1487
1488         if (s->cm_clksel2_emu&0x80000)
1489         {
1490                 /*override control of DPLL3*/
1491                 m = (s->cm_clksel2_emu&0x7ff)>>8;
1492                 n =  s->cm_clksel2_emu&0x7f;
1493                 TRACE("DPLL3 override, m 0x%x n 0x%x",m,n);
1494         }
1495
1496         //OMAP3_DEBUG(("dpll3 cm_clksel1_pll %x m  %d n %d m2 %d  m3 %d\n",s->cm_clksel1_pll,m,n,m2,m3 ));
1497         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core_clk"), (n + 1) * m2,
1498                          m);
1499         omap_clk_setrate(omap_findclk(s->mpu, "omap3_core2_clk"), (n + 1) * m2,
1500                          m * 2);
1501         omap_clk_setrate(omap_findclk(s->mpu, "omap3_emu_core_alwon_clk"),
1502                          (n + 1) * m3, m * 2);
1503         TRACE("coreclk %lld",
1504               omap_clk_getrate(omap_findclk(s->mpu, "omap3_core_clk")));
1505     }
1506
1507
1508 }
1509
1510
1511 static inline void omap3_cm_dpll4_update(struct omap3_cm_s *s)
1512 {
1513     uint32_t m, n, m2, m3, m4, m5, m6, cm_clken_pll;
1514     cm_clken_pll = s->cm_clken_pll;
1515     uint32_t bypass = 1;
1516
1517     /*dpll3 bypass mode. parent clock is always omap3_sys_clk */
1518     /*DPLL4 */
1519     if ((cm_clken_pll & 0x70000) == 0x10000)
1520     {
1521         bypass = 1;
1522     }
1523     else if ((cm_clken_pll & 0x70000) == 0x70000)
1524     {
1525         m = (s->cm_clksel2_pll & 0x7ff00) >> 8;
1526         if ((m == 0) || (m == 1))
1527             bypass = 1;
1528         else
1529             bypass = 0;
1530     }
1531     if (bypass == 1)
1532     {
1533         omap_clk_setrate(omap_findclk(s->mpu, "omap3_96m_fclk"), 1, 1);
1534         omap_clk_setrate(omap_findclk(s->mpu, "omap3_54m_fclk"), 1, 1);
1535         omap_clk_setrate(omap_findclk(s->mpu, "omap3_dss1_alwon_fclk"), 1, 1);
1536         omap_clk_setrate(omap_findclk(s->mpu, "omap3_cam_mclk"), 1, 1);
1537         omap_clk_setrate(omap_findclk(s->mpu, "omap3_per_alwon_clk"), 1, 1);
1538     }
1539     else
1540     {
1541         n = (s->cm_clksel2_pll & 0x7f);
1542         m2 = s->cm_clksel3_pll & 0x1f;
1543         m3 = (s->cm_clksel_dss & 0x1f00) >> 8;
1544         m4 = s->cm_clksel_dss & 0x1f;
1545         m5 = s->cm_clksel_cam & 0x1f;
1546         m6 = (s->cm_clksel1_emu & 0x1f000000) >> 24;
1547
1548         if (s->cm_clksel3_emu&0x80000)
1549         {
1550                 /*override control of DPLL4*/
1551                 m = (s->cm_clksel3_emu&0x7ff)>>8;
1552                 n =  s->cm_clksel3_emu&0x7f;
1553                 TRACE("DPLL4 override, m 0x%x n 0x%x",m,n);
1554         }
1555
1556
1557         //OMAP3_DEBUG(("dpll4 m  %d n %d m2 %d  m3 %d m4 %d m5 %d m6 %d \n",m,n,m2,m3,m4,m5,m6 ));
1558         omap_clk_setrate(omap_findclk(s->mpu, "omap3_96m_fclk"), (n + 1) * m2,
1559                          m * 2);
1560         omap_clk_setrate(omap_findclk(s->mpu, "omap3_54m_fclk"), (n + 1) * m3,
1561                          m * 2);
1562         omap_clk_setrate(omap_findclk(s->mpu, "omap3_dss1_alwon_fclk"),
1563                          (n + 1) * m4, m * 2);
1564         omap_clk_setrate(omap_findclk(s->mpu, "omap3_cam_mclk"), (n + 1) * m5,
1565                          m * 2);
1566         omap_clk_setrate(omap_findclk(s->mpu, "omap3_per_alwon_clk"),
1567                          (n + 1) * m6, m * 2);
1568
1569         TRACE("omap3_96m_fclk %lld",
1570               omap_clk_getrate(omap_findclk(s->mpu, "omap3_96m_fclk")));
1571         TRACE("omap3_54m_fclk %lld",
1572               omap_clk_getrate(omap_findclk(s->mpu, "omap3_54m_fclk")));
1573         TRACE("omap3_dss1_alwon_fclk %lld",
1574               omap_clk_getrate(omap_findclk(s->mpu, "omap3_dss1_alwon_fclk")));
1575         TRACE("omap3_cam_mclk %lld",
1576               omap_clk_getrate(omap_findclk(s->mpu, "omap3_cam_mclk")));
1577         TRACE("omap3_per_alwon_clk %lld",
1578               omap_clk_getrate(omap_findclk(s->mpu, "omap3_per_alwon_clk")));
1579         TRACE("omap3_48m_fclk %lld",
1580               omap_clk_getrate(omap_findclk(s->mpu, "omap3_48m_fclk")));
1581         TRACE("omap3_12m_fclk %lld",
1582               omap_clk_getrate(omap_findclk(s->mpu, "omap3_12m_fclk")));
1583     }
1584 }
1585
1586 static inline void omap3_cm_dpll5_update(struct omap3_cm_s *s)
1587 {
1588          uint32_t m, n, m2, cm_idlest2_ckgen;
1589     uint32_t bypass = 1;
1590
1591     cm_idlest2_ckgen = s->cm_idlest2_ckgen;;
1592
1593     /*dpll5 bypass mode */
1594     if ((cm_idlest2_ckgen & 0x1) == 0x0)
1595     {
1596         bypass = 1;
1597     }
1598
1599     if (bypass == 1)
1600     {
1601         omap_clk_setrate(omap_findclk(s->mpu, "omap3_120m_fclk"), 1, 1);
1602     }
1603     else
1604     {
1605          m = (s->cm_clksel4_pll & 0x7ff00)>>8;
1606         n = s->cm_clksel4_pll & 0x3f00;
1607         m2 = s->cm_clksel5_pll & 0x1f;
1608
1609         TRACE("dpll5 m %d n %d m2 %d",m,n,m2);
1610         omap_clk_setrate(omap_findclk(s->mpu, "omap3_120m_fclk"), (n + 1) * m2,
1611                          m);
1612         TRACE("omap3_120m_fclk %lld",
1613               omap_clk_getrate(omap_findclk(s->mpu, "omap3_120m_fclk")));
1614     }
1615
1616
1617 }
1618 static inline void omap3_cm_48m_update(struct omap3_cm_s *s)
1619 {
1620     if (s->cm_clksel1_pll & 0x8)
1621     {
1622         /*parent is sysaltclk */
1623         omap_clk_reparent(omap_findclk(s->mpu, "omap3_48m_fclk"),
1624                           omap_findclk(s->mpu, "omap3_sys_altclk"));
1625         omap_clk_reparent(omap_findclk(s->mpu, "omap3_12m_fclk"),
1626                           omap_findclk(s->mpu, "omap3_sys_altclk"));
1627         /*TODO:need to set rate ? */
1628
1629     }
1630     else
1631     {
1632         omap_clk_reparent(omap_findclk(s->mpu, "omap3_12m_fclk"),
1633                           omap_findclk(s->mpu, "omap3_96m_fclk"));
1634         omap_clk_reparent(omap_findclk(s->mpu, "omap3_48m_fclk"),
1635                           omap_findclk(s->mpu, "omap3_96m_fclk"));
1636         omap_clk_setrate(omap_findclk(s->mpu, "omap3_48m_fclk"), 2, 1);
1637         omap_clk_setrate(omap_findclk(s->mpu, "omap3_12m_fclk"), 8, 1);
1638
1639     }
1640
1641 }
1642
1643 static inline void omap3_cm_gp10_update(struct omap3_cm_s *s)
1644 {
1645     omap_clk gp10_fclk = omap_findclk(s->mpu, "omap3_gp10_fclk");
1646
1647     if (s->cm_clksel_core & 0x40)
1648         omap_clk_reparent(gp10_fclk, omap_findclk(s->mpu, "omap3_sys_clk"));
1649     else
1650         omap_clk_reparent(gp10_fclk, omap_findclk(s->mpu, "omap3_32k_fclk"));
1651
1652     /*Tell GPTIMER10 to generate new clk rate */
1653     omap_gp_timer_change_clk(s->mpu->gptimer[9]);
1654     TRACE("omap3_gp10_fclk %lld",
1655           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp10_fclk")));
1656 }
1657
1658 static inline void omap3_cm_gp11_update(struct omap3_cm_s *s)
1659 {
1660     omap_clk gp11_fclk = omap_findclk(s->mpu, "omap3_gp11_fclk");
1661
1662     if (s->cm_clksel_core & 0x80)
1663         omap_clk_reparent(gp11_fclk, omap_findclk(s->mpu, "omap3_sys_clk"));
1664     else
1665         omap_clk_reparent(gp11_fclk, omap_findclk(s->mpu, "omap3_32k_fclk"));
1666     /*Tell GPTIMER11 to generate new clk rate */
1667     omap_gp_timer_change_clk(s->mpu->gptimer[10]);
1668     TRACE("omap3_gp11_fclk %lld",
1669           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp11_fclk")));
1670 }
1671
1672 static inline void omap3_cm_l3clk_update(struct omap3_cm_s *s)
1673 {
1674     omap_clk l3_iclk = omap_findclk(s->mpu, "omap3_l3_iclk");
1675     if ((s->cm_clksel_core & 0x3) == 0x1)
1676         omap_clk_setrate(l3_iclk, 1, 1);
1677     else if ((s->cm_clksel_core & 0x3) == 0x2)
1678         omap_clk_setrate(l3_iclk, 2, 1);
1679 }
1680
1681 static inline void omap3_cm_l4clk_update(struct omap3_cm_s *s)
1682 {
1683     omap_clk l4_iclk = omap_findclk(s->mpu, "omap3_l4_iclk");
1684     if ((s->cm_clksel_core & 0xc) == 0x4)
1685         omap_clk_setrate(l4_iclk, 1, 1);
1686     else if ((s->cm_clksel_core & 0xc) == 0x8)
1687         omap_clk_setrate(l4_iclk, 2, 1);
1688 }
1689
1690 static inline void omap3_cm_per_gptimer_update(struct omap3_cm_s *s)
1691 {
1692     uint32_t cm_clksel_per = s->cm_clksel_per;
1693
1694     if (cm_clksel_per & 0x1)
1695         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp2_fclk"),
1696                           omap_findclk(s->mpu, "omap3_sys_clk"));
1697     else
1698         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp2_fclk"),
1699                           omap_findclk(s->mpu, "omap3_32k_fclk"));
1700     omap_gp_timer_change_clk(s->mpu->gptimer[1]);
1701
1702     if (cm_clksel_per & 0x2)
1703         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp3_fclk"),
1704                           omap_findclk(s->mpu, "omap3_sys_clk"));
1705     else
1706         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp3_fclk"),
1707                           omap_findclk(s->mpu, "omap3_32k_fclk"));
1708     omap_gp_timer_change_clk(s->mpu->gptimer[2]);
1709
1710     if (cm_clksel_per & 0x4)
1711         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp4_fclk"),
1712                           omap_findclk(s->mpu, "omap3_sys_clk"));
1713     else
1714         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp4_fclk"),
1715                           omap_findclk(s->mpu, "omap3_32k_fclk"));
1716     omap_gp_timer_change_clk(s->mpu->gptimer[3]);
1717
1718     if (cm_clksel_per & 0x8)
1719         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp5_fclk"),
1720                           omap_findclk(s->mpu, "omap3_sys_clk"));
1721     else
1722         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp5_fclk"),
1723                           omap_findclk(s->mpu, "omap3_32k_fclk"));
1724     omap_gp_timer_change_clk(s->mpu->gptimer[4]);
1725
1726     if (cm_clksel_per & 0x10)
1727         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp6_fclk"),
1728                           omap_findclk(s->mpu, "omap3_sys_clk"));
1729     else
1730         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp6_fclk"),
1731                           omap_findclk(s->mpu, "omap3_32k_fclk"));
1732     omap_gp_timer_change_clk(s->mpu->gptimer[5]);
1733
1734     if (cm_clksel_per & 0x20)
1735         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp7_fclk"),
1736                           omap_findclk(s->mpu, "omap3_sys_clk"));
1737     else
1738         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp7_fclk"),
1739                           omap_findclk(s->mpu, "omap3_32k_fclk"));
1740     omap_gp_timer_change_clk(s->mpu->gptimer[6]);
1741
1742
1743     if (cm_clksel_per & 0x40)
1744         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp8_fclk"),
1745                           omap_findclk(s->mpu, "omap3_sys_clk"));
1746     else
1747         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp8_fclk"),
1748                           omap_findclk(s->mpu, "omap3_32k_fclk"));
1749     omap_gp_timer_change_clk(s->mpu->gptimer[7]);
1750
1751     if (cm_clksel_per & 0x80)
1752         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp9_fclk"),
1753                           omap_findclk(s->mpu, "omap3_sys_clk"));
1754     else
1755         omap_clk_reparent(omap_findclk(s->mpu, "omap3_gp9_fclk"),
1756                           omap_findclk(s->mpu, "omap3_32k_fclk"));
1757     omap_gp_timer_change_clk(s->mpu->gptimer[8]);
1758
1759     /*TODO:Tell GPTIMER to generate new clk rate */
1760     TRACE("omap3_gp2_fclk %lld",
1761           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp2_fclk")));
1762     TRACE("omap3_gp3_fclk %lld",
1763           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp3_fclk")));
1764         TRACE("omap3_gp4_fclk %lld",
1765           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp4_fclk")));
1766     TRACE("omap3_gp5_fclk %lld",
1767           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp5_fclk")));
1768     TRACE("omap3_gp6_fclk %lld",
1769           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp6_fclk")));
1770     TRACE("omap3_gp7_fclk %lld",
1771           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp7_fclk")));
1772     TRACE("omap3_gp8_fclk %lld",
1773           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp8_fclk")));
1774     TRACE("omap3_gp9_fclk %lld",
1775           omap_clk_getrate(omap_findclk(s->mpu, "omap3_gp9_fclk")));
1776 }
1777
1778 static inline void omap3_cm_clkout2_update(struct omap3_cm_s *s)
1779 {
1780         uint32 divor;
1781
1782         if (!s->cm_clkout_ctrl&0x80)
1783                 return;
1784
1785         switch (s->cm_clkout_ctrl&0x3)
1786         {
1787                 case 0x0:
1788                         omap_clk_reparent(omap_findclk(s->mpu, "omap3_sys_clkout2"),
1789                           omap_findclk(s->mpu, "omap3_core_clk"));
1790                         break;
1791                 case 0x1:
1792                         omap_clk_reparent(omap_findclk(s->mpu, "omap3_sys_clkout2"),
1793                           omap_findclk(s->mpu, "omap3_sys_clk"));
1794                         break;
1795                 case 0x2:
1796                         omap_clk_reparent(omap_findclk(s->mpu, "omap3_sys_clkout2"),
1797                           omap_findclk(s->mpu, "omap3_96m_fclk"));
1798                         break;
1799                 case 0x3:
1800                         omap_clk_reparent(omap_findclk(s->mpu, "omap3_sys_clkout2"),
1801                           omap_findclk(s->mpu, "omap3_54m_fclk"));
1802                         break;
1803         }
1804
1805         divor = (s->cm_clkout_ctrl&0x31)>>3;
1806         divor = 1<<divor;
1807         omap_clk_setrate(omap_findclk(s->mpu, "omap3_sys_clkout2"), divor, 1);
1808
1809 }
1810
1811 static void omap3_cm_reset(struct omap3_cm_s *s)
1812 {
1813     s->cm_fclken_iva2 = 0x0;
1814     s->cm_clken_pll_iva2 = 0x11;
1815     s->cm_idlest_iva2 = 0x1;
1816     s->cm_idlest_pll_iva2 = 0x0;
1817     s->cm_autoidle_pll_iva2 = 0x0;
1818     s->cm_clksel1_pll_iva2 = 0x80000;
1819     s->cm_clksel2_pll_iva2 = 0x1;
1820     s->cm_clkstctrl_iva2 = 0x0;
1821     s->cm_clkstst_iva2 = 0x0;
1822
1823     s->cm_revision = 0x10;
1824     s->cm_sysconfig = 0x1;
1825
1826     s->cm_clken_pll_mpu = 0x15;
1827     s->cm_idlest_mpu = 0x1;
1828     s->cm_idlest_pll_mpu = 0x0;
1829     s->cm_autoidle_pll_mpu = 0x0;
1830     s->cm_clksel1_pll_mpu = 0x80000;
1831     s->cm_clksel2_pll_mpu = 0x1;
1832     s->cm_clkstctrl_mpu = 0x0;
1833     s->cm_clkstst_mpu = 0x0;
1834
1835     s->cm_fclken1_core = 0x0;
1836     s->cm_fclken3_core = 0x0;
1837     s->cm_iclken1_core = 0x42;
1838     s->cm_iclken2_core = 0x0;
1839     s->cm_iclken3_core = 0x0;
1840     /*allow access to devices*/
1841     s->cm_idlest1_core = 0x0;
1842     s->cm_idlest2_core = 0x0;
1843     /*ide status =0 */
1844     s->cm_idlest3_core = 0xa;
1845     s->cm_autoidle1_core = 0x0;
1846     s->cm_autoidle2_core = 0x0;
1847     s->cm_autoidle3_core = 0x0;
1848     s->cm_clksel_core = 0x105;
1849     s->cm_clkstctrl_core = 0x0;
1850     s->cm_clkstst_core = 0x0;
1851
1852     s->cm_fclken_sgx = 0x0;
1853     s->cm_iclken_sgx = 0x0;
1854     s->cm_idlest_sgx = 0x1;
1855     s->cm_clksel_sgx = 0x0;
1856     s->cm_sleepdep_sgx = 0x0;
1857     s->cm_clkstctrl_sgx = 0x0;
1858     s->cm_clkstst_sgx = 0x0;
1859
1860     s->cm_fclken_wkup = 0x0;
1861     s->cm_iclken_wkup = 0x0;
1862     /*assume all clock can be accessed*/
1863     s->cm_idlest_wkup = 0x0;
1864     s->cm_autoidle_wkup = 0x0;
1865     s->cm_clksel_wkup = 0x12;
1866
1867     s->cm_clken_pll = 0x110015;
1868     s->cm_clken2_pll = 0x11;
1869     s->cm_idlest_ckgen = 0x0;
1870     s->cm_idlest2_ckgen = 0x0;
1871     s->cm_autoidle_pll = 0x0;
1872     s->cm_autoidle2_pll = 0x0;
1873     s->cm_clksel1_pll = 0x8000040;
1874     s->cm_clksel2_pll = 0x0;
1875     s->cm_clksel3_pll = 0x1;
1876     s->cm_clksel4_pll = 0x0;
1877     s->cm_clksel5_pll = 0x1;
1878     s->cm_clkout_ctrl = 0x3;
1879
1880
1881     s->cm_fclken_dss = 0x0;
1882     s->cm_iclken_dss = 0x0;
1883     /*dss can be accessed*/
1884     s->cm_idlest_dss = 0x0;
1885     s->cm_autoidle_dss = 0x0;
1886     s->cm_clksel_dss = 0x1010;
1887     s->cm_sleepdep_dss = 0x0;
1888     s->cm_clkstctrl_dss = 0x0;
1889     s->cm_clkstst_dss = 0x0;
1890
1891     s->cm_fclken_cam = 0x0;
1892     s->cm_iclken_cam = 0x0;
1893     s->cm_idlest_cam = 0x1;
1894     s->cm_autoidle_cam = 0x0;
1895     s->cm_clksel_cam = 0x10;
1896     s->cm_sleepdep_cam = 0x0;
1897     s->cm_clkstctrl_cam = 0x0;
1898     s->cm_clkstst_cam = 0x0;
1899
1900     s->cm_fclken_per = 0x0;
1901     s->cm_iclken_per = 0x0;
1902     //s->cm_idlest_per = 0x3ffff;
1903     s->cm_idlest_per = 0x0; //enable GPIO access
1904     s->cm_autoidle_per = 0x0;
1905     s->cm_clksel_per = 0x0;
1906     s->cm_sleepdep_per = 0x0;
1907     s->cm_clkstctrl_per = 0x0;
1908     s->cm_clkstst_per = 0x0;
1909
1910     s->cm_clksel1_emu = 0x10100a50;
1911     s->cm_clkstctrl_emu = 0x2;
1912     s->cm_clkstst_emu = 0x0;
1913     s->cm_clksel2_emu = 0x0;
1914     s->cm_clksel3_emu = 0x0;
1915
1916     s->cm_polctrl = 0x0;
1917
1918     s->cm_idlest_neon = 0x1;
1919     s->cm_clkstctrl_neon = 0x0;
1920
1921     s->cm_fclken_usbhost = 0x0;
1922     s->cm_iclken_usbhost = 0x0;
1923     s->cm_idlest_usbhost = 0x3;
1924     s->cm_autoidle_usbhost = 0x0;
1925     s->cm_sleepdep_usbhost = 0x0;
1926     s->cm_clkstctrl_usbhost = 0x0;
1927     s->cm_clkstst_usbhost = 0x0;
1928 }
1929
1930 static uint32_t omap3_cm_read(void *opaque, target_phys_addr_t addr)
1931 {
1932     struct omap3_cm_s *s = (struct omap3_cm_s *) opaque;
1933     uint32_t ret;
1934     uint32_t bypass = 0, m;
1935
1936     TRACE("%04x", addr);
1937     switch (addr)
1938     {
1939     case 0x0:
1940         return s->cm_fclken_iva2;
1941     case 0x04:
1942         return s->cm_clken_pll_iva2;
1943     case 0x20:
1944         return s->cm_idlest_iva2;
1945     case 0x24:
1946         if (((s->cm_clken_pll_iva2 & 0x7) == 0x5)
1947             || ((s->cm_clken_pll_iva2 & 0x7) == 0x1))
1948         {
1949             bypass = 1;
1950         }
1951         else if ((s->cm_clken_pll_iva2 & 0x7) == 0x7)
1952         {
1953             m = (s->cm_clksel1_pll_iva2 & 0x7ff00) >> 8;
1954             if ((m == 0) || (m == 1))
1955                 bypass = 1;
1956             else
1957                 bypass = 0;
1958         }
1959         if (bypass)
1960             return 0;
1961         else
1962             return 1;
1963     case 0x34:
1964         return s->cm_autoidle_pll_iva2;
1965     case 0x40:
1966         return s->cm_clksel1_pll_iva2;
1967     case 0x44:
1968         return s->cm_clksel2_pll_iva2;
1969     case 0x48:
1970         return s->cm_clkstctrl_iva2;
1971     case 0x4c:
1972         return s->cm_clkstst_iva2;
1973
1974    case 0x800:
1975                 return s->cm_revision;
1976         case 0x810:
1977                 return s->cm_sysconfig;
1978
1979
1980     case 0x904:                /*CM_CLKEN_PLL_MPU */
1981         return s->cm_clken_pll_mpu;
1982    case 0x920:
1983                 return s->cm_idlest_mpu & 0x0;  /*MPU is active*/
1984     case 0x924:
1985         if ((s->cm_clken_pll_mpu & 0x7) == 0x5)
1986         {
1987             bypass = 1;
1988         }
1989         else if ((s->cm_clken_pll_mpu & 0x7) == 0x7)
1990         {
1991             m = (s->cm_clksel1_pll_mpu & 0x7ff00) >> 8;
1992             if ((m == 0) || (m == 1))
1993                 bypass = 1;
1994             else
1995                 bypass = 0;
1996         }
1997         if (bypass)
1998             return 0;
1999         else
2000             return 1;
2001     case 0x934:
2002         return s->cm_autoidle_pll_mpu;
2003     case 0x940:
2004         return s->cm_clksel1_pll_mpu;
2005     case 0x944:
2006         return s->cm_clksel2_pll_mpu;
2007      case 0x948:
2008         return s->cm_clkstctrl_mpu;
2009      case 0x94c:
2010         return s->cm_clkstst_mpu;
2011
2012
2013
2014     case 0xa00:
2015         return s->cm_fclken1_core;
2016     case 0xa08:
2017         return s->cm_fclken3_core;
2018     case 0xa10:
2019         return s->cm_iclken1_core;
2020     case 0xa14:
2021          return s->cm_iclken2_core;
2022     case 0xa20:
2023         return s->cm_idlest1_core;
2024     case 0xa24:
2025         return s->cm_idlest2_core;
2026     case 0xa28:
2027         return s->cm_idlest3_core;
2028     case 0xa30:
2029         return s->cm_autoidle1_core;
2030     case 0xa34:
2031         return s->cm_autoidle2_core;
2032     case 0xa38:
2033         return s->cm_autoidle3_core;
2034     case 0xa40:                /*CM_CLKSEL_CORE */
2035         return s->cm_clksel_core;
2036     case 0xa48:
2037          return s->cm_clkstctrl_core;
2038      case 0xa4c:
2039         return s->cm_clkstst_core;
2040
2041    case 0xb00:
2042                 return s->cm_fclken_sgx;
2043         case 0xb10:
2044                 return s->cm_iclken_sgx;
2045         case 0xb20:
2046                 return s->cm_idlest_sgx&0x0;
2047    case 0xb40:                /*CM_CLKSEL_SGX */
2048         return s->cm_clksel_sgx;
2049    case 0xb48:
2050                 return s->cm_clkstctrl_sgx;
2051         case 0xb4c:
2052                 return s->cm_clkstst_sgx;
2053
2054
2055     case 0xc00:                /*CM_FCLKEN_WKUP */
2056         return s->cm_fclken_wkup;
2057     case 0xc10:                /*CM_ICLKEN_WKUP */
2058         return s->cm_iclken_wkup;
2059     case 0xc20:                /*CM_IDLEST_WKUP */
2060         /*TODO: Check whether the timer can be accessed. */
2061         return 0x0;
2062     case 0xc30:
2063         return s->cm_idlest_wkup;
2064     case 0xc40:
2065         return s->cm_clksel_wkup;
2066     case 0xc48:
2067         return s->cm_c48;
2068
2069
2070     case 0xd00:                /*CM_CLKEN_PLL */
2071         return s->cm_clken_pll;
2072     case 0xd04:
2073         return s->cm_clken2_pll;
2074     case 0xd20:
2075          /*FIXME: all clock is active. we do not care it. */
2076         ret = 0x3ffff;
2077
2078         /*DPLL3*/
2079         bypass = 0;
2080         if (((s->cm_clken_pll & 0x7) == 0x5) || ((s->cm_clken_pll & 0x7) == 0x6))
2081                 bypass = 1;
2082         else if ((s->cm_clken_pll & 0x7) == 0x7) {
2083             m = (s->cm_clksel1_pll & 0x7ff0000) >> 16;
2084             if ((m == 0) || (m == 1))
2085                 bypass = 1;
2086             else
2087                 bypass = 0;
2088         }
2089         if (bypass)
2090             ret &= 0xfffe;
2091
2092         /*DPLL4*/
2093             bypass = 0;
2094             if ((s->cm_clken_pll & 0x70000) == 0x10000)
2095             bypass = 1;
2096         else if ((s->cm_clken_pll & 0x70000) == 0x70000) {
2097             m = (s->cm_clksel2_pll & 0x7ff00) >> 8;
2098             if ((m == 0) || (m == 1))
2099                 bypass = 1;
2100             else
2101                 bypass = 0;
2102         }
2103         if (bypass)
2104             ret &= 0xfffd;
2105         return ret;
2106
2107     case 0xd24:
2108         return s->cm_idlest2_ckgen;
2109     case 0xd30:
2110         return s->cm_autoidle_pll;
2111     case 0xd34:
2112         return s->cm_autoidle2_pll;
2113     case 0xd40:                /*CM_CLKSEL1_PLL */
2114         return s->cm_clksel1_pll;
2115     case 0xd44:
2116         return s->cm_clksel2_pll;
2117     case 0xd48:                /*CM_CLKSEL3_PLL */
2118         return s->cm_clksel3_pll;
2119     case 0xd4c:
2120         return s->cm_clksel4_pll;
2121     case 0xd50:                /*CM_CLKSEL5_PLL */
2122         return s->cm_clksel5_pll;
2123     case 0xd70:
2124          return s->cm_clkout_ctrl;
2125
2126
2127     case 0xe00:
2128         return s->cm_fclken_dss;
2129         case 0xe10:
2130         return s->cm_iclken_dss;
2131     case 0xe20:
2132         return s->cm_idlest_dss;
2133     case 0xe30:
2134         return s->cm_autoidle_dss;
2135     case 0xe40:
2136         return s->cm_clksel_dss;
2137     case 0xe44:
2138         return s->cm_sleepdep_dss;
2139     case 0xe48:
2140         return s->cm_clkstctrl_dss;
2141     case 0xe4c:
2142         return s->cm_clkstst_dss;
2143
2144
2145     case 0xf00:
2146         return s->cm_fclken_cam;
2147     case 0xf10:
2148         return s->cm_iclken_cam;
2149     case 0xf20:
2150         return s->cm_idlest_cam&0x0;
2151     case 0xf30:
2152         return s->cm_autoidle_cam;
2153     case 0xf40:
2154         return s->cm_clksel_cam;
2155     case 0xf44:
2156         return s->cm_sleepdep_cam;
2157     case 0xf48:
2158         return s->cm_clkstctrl_cam;
2159     case 0xf4c:
2160         return s->cm_clkstst_cam;
2161
2162
2163     case 0x1000:
2164         return s->cm_fclken_per;
2165     case 0x1010:
2166         return s->cm_iclken_per;
2167     case 0x1020:
2168         return s->cm_idlest_per ;
2169     case 0x1030:
2170         return s->cm_autoidle_per;
2171     case 0x1040:
2172         return s->cm_clksel_per;
2173     case 0x1044:
2174         return s->cm_sleepdep_per;
2175     case 0x1048:
2176         return s->cm_clkstctrl_per;
2177     case 0x104c:
2178                 return s->cm_clkstst_per;
2179
2180
2181     case 0x1140:               /*CM_CLKSEL1_EMU */
2182         return s->cm_clksel1_emu;
2183     case 0x1148:
2184          return s->cm_clkstctrl_emu;
2185     case 0x114c:
2186         return s->cm_clkstst_emu&0x0;
2187     case 0x1150:
2188         return s->cm_clksel2_emu;
2189     case 0x1154:
2190         return s->cm_clksel3_emu;
2191
2192    case 0x129c:
2193                 return s->cm_polctrl;
2194
2195         case 0x1320:
2196                 return s->cm_idlest_neon&0x0;
2197         case 0x1348:
2198                 return s->cm_clkstctrl_neon;
2199
2200         case 0x1400:
2201                 return s->cm_fclken_usbhost;
2202         case 0x1410:
2203                 return s->cm_iclken_usbhost;
2204         case 0x1420:
2205                 return s->cm_idlest_usbhost&0x0;
2206     case 0x1430:
2207         return s->cm_autoidle_usbhost;
2208     case 0x1444:
2209         return s->cm_sleepdep_usbhost;
2210     case 0x1448:
2211         return s->cm_clkstctrl_usbhost;
2212     case 0x144c:
2213         return s->cm_clkstst_usbhost;
2214
2215     default:
2216         printf("omap3_cm_read addr %x pc %x \n", addr, cpu_single_env->regs[15] );
2217         exit(-1);
2218     }
2219 }
2220
2221
2222 static void omap3_cm_write(void *opaque, target_phys_addr_t addr,
2223                            uint32_t value)
2224 {
2225     struct omap3_cm_s *s = (struct omap3_cm_s *) opaque;
2226
2227     TRACE("%04x = %08x", addr, value);
2228     switch (addr)
2229     {
2230     case 0x20:
2231     case 0x24:
2232     case 0x4c:
2233     case 0x800:
2234     case 0x920:
2235     case 0x924:
2236     case 0x94c:
2237     case 0xa20:
2238     case 0xa24:
2239     case 0xa28:
2240     case 0xa4c:
2241     case 0xb20:
2242     case 0xb4c:
2243     case 0xc20:                /*CM_IDLEST_WKUP */
2244     case 0xd20:
2245     case 0xd24:
2246     case 0xe20:
2247     case 0xe4c:
2248     case 0xf20:
2249     case 0xf4c:
2250     case 0x1020:
2251     case 0x104c:
2252     case 0x114c:
2253     case 0x1320:
2254     case 0x1420:
2255     case 0x144c:
2256         OMAP_RO_REG(addr);
2257         exit(-1);
2258         break;
2259
2260     case 0x0:
2261         s->cm_fclken_iva2 = value & 0x1;
2262         break;
2263     case 0x4:                  /*CM_CLKEN_PLL_IVA2 */
2264         s->cm_clken_pll_iva2 = value & 0x7ff;
2265         omap3_cm_iva2_update(s);
2266         break;
2267     case 0x34:
2268         s->cm_autoidle_pll_iva2 = value & 0x7;
2269         break;
2270     case 0x40:
2271         s->cm_clksel1_pll_iva2 = value & 0x3fff7f;
2272         //printf("value %x s->cm_clksel1_pll_iva2 %x \n",value,s->cm_clksel1_pll_iva2);
2273         omap3_cm_iva2_update(s);
2274         break;
2275     case 0x44:
2276         s->cm_clksel2_pll_iva2 = value & 0x1f;
2277         omap3_cm_iva2_update(s);
2278         break;
2279     case 0x48:
2280         s->cm_clkstctrl_iva2 = value& 0x3;
2281         break;
2282
2283     case 0x810:
2284         s->cm_sysconfig = value & 0x1;
2285         break;
2286
2287
2288     case 0x904:                /*CM_CLKEN_PLL_MPU */
2289         s->cm_clken_pll_mpu = value & 0x7ff;
2290         omap3_cm_mpu_update(s);
2291         break;
2292     case 0x934:
2293         s->cm_autoidle_pll_mpu = value & 0x7;
2294         break;
2295     case 0x940:
2296         //printf("s->cm_clksel1_pll_mpu  %x\n",s->cm_clksel1_pll_mpu );
2297         s->cm_clksel1_pll_mpu = value & 0x3fff7f;
2298         omap3_cm_mpu_update(s);
2299         break;
2300     case 0x944:
2301         s->cm_clksel2_pll_mpu = value & 0x1f;
2302         omap3_cm_mpu_update(s);
2303         break;
2304     case 0x948:
2305         s->cm_clkstctrl_mpu = value & 0x3;
2306         break;
2307
2308
2309     case 0xa00:
2310         s->cm_fclken1_core = value & 0x43fffe00;
2311          break;
2312     case 0xa08:
2313          s->cm_fclken3_core = value & 0x7;
2314          break;
2315     case 0xa10:
2316         s->cm_iclken1_core = value & 0x637ffed2;
2317         s->cm_idlest1_core = ~s->cm_iclken1_core;
2318         /* TODO: replace code below with real implementation */
2319         s->cm_idlest1_core &= ~0x20; /* HS OTG USB idle */
2320         s->cm_idlest1_core |= 4; /* SDMA in standby */
2321         break;
2322     case 0xa14:
2323          s->cm_iclken2_core = value & 0x1f;
2324          break;
2325     case 0xa18:
2326         s->cm_iclken3_core = value & 0x4;
2327         s->cm_idlest3_core = 0xd & ~(s->cm_iclken3_core & 4);
2328         break;
2329     case 0xa30:
2330         s->cm_autoidle1_core = value & 0x7ffffed0;
2331         break;
2332     case 0xa34:
2333         s->cm_autoidle2_core = value & 0x1f;
2334         break;
2335     case 0xa38:
2336         s->cm_autoidle3_core = value & 0x2;
2337         break;
2338     case 0xa40:                /*CM_CLKSEL_CORE */
2339         s->cm_clksel_core = (value & 0xff);
2340         s->cm_clksel_core |= 0x100;
2341         omap3_cm_gp10_update(s);
2342         omap3_cm_gp11_update(s);
2343         omap3_cm_l3clk_update(s);
2344         omap3_cm_l4clk_update(s);
2345         break;
2346     case 0xa48:
2347         s->cm_clkstctrl_core = value & 0xf;
2348         break;
2349
2350     case 0xb00:
2351         s->cm_fclken_sgx = value &0x2;
2352         break;
2353     case 0xb10:
2354         s->cm_iclken_sgx = value & 0x1;
2355         break;
2356     case 0xb40:                /*CM_CLKSEL_SGX */
2357         /*TODO: SGX Clock!! */
2358         s->cm_clksel_sgx = value;
2359         break;
2360     case 0xb44:
2361         s->cm_sleepdep_sgx = value &0x2;
2362         break;
2363     case 0xb48:
2364         s->cm_clkstctrl_sgx = value & 0x3;
2365         break;
2366
2367
2368     case 0xc00:                /*CM_FCLKEN_WKUP */
2369         s->cm_fclken_wkup = value & 0x2e9;
2370         break;
2371     case 0xc10:                /*CM_ICLKEN_WKUP */
2372         s->cm_iclken_wkup = value & 0x2ff;
2373         break;
2374     case 0xc30:
2375         s->cm_autoidle_wkup = value & 0x23f;
2376         break;
2377     case 0xc40:                /*CM_CLKSEL_WKUP */
2378         s->cm_clksel_wkup = value & 0x7f;
2379         omap3_cm_clksel_wkup_update(s, s->cm_clksel_wkup);
2380         break;
2381
2382
2383     case 0xd00:                /*CM_CLKEN_PLL */
2384         s->cm_clken_pll = value & 0xffff17ff;
2385         omap3_cm_dpll3_update(s);
2386         omap3_cm_dpll4_update(s);
2387         break;
2388     case 0xd04:
2389         s->cm_clken2_pll = value & 0x7ff;
2390         break;
2391     case 0xd30:
2392         s->cm_autoidle_pll = value & 0x3f;
2393         break;
2394     case 0xd34:
2395         s->cm_autoidle2_pll = value & 0x7;
2396         break;
2397     case 0xd40:                /*CM_CLKSEL1_PLL */
2398         //OMAP3_DEBUG(("WD40 value %x \n",value));
2399         s->cm_clksel1_pll = value & 0xffffbffc;
2400         //OMAP3_DEBUG(("WD40 value %x \n",value));
2401         omap3_cm_dpll3_update(s);
2402         omap3_cm_48m_update(s);
2403         break;
2404     case 0xd44:
2405         s->cm_clksel2_pll = value & 0x7ff7f;
2406         omap3_cm_dpll4_update(s);
2407         break;
2408     case 0xd48:                /*CM_CLKSEL3_PLL */
2409         s->cm_clksel3_pll = value & 0x1f;
2410         omap3_cm_dpll4_update(s);
2411         break;
2412     case 0xd4c:                /*CM_CLKSEL4_PLL */
2413         s->cm_clksel4_pll = value & 0x7ff7f;
2414         omap3_cm_dpll5_update(s);
2415         break;
2416      case 0xd50:                /*CM_CLKSEL5_PLL */
2417         s->cm_clksel5_pll = value & 0x1f;
2418         omap3_cm_dpll5_update(s);
2419         break;
2420     case 0xd70:
2421         s->cm_clkout_ctrl = value & 0xbb;
2422         omap3_cm_clkout2_update(s);
2423         break;
2424
2425     case 0xe00:
2426         s->cm_fclken_dss = value & 0x7;
2427         break;
2428         case 0xe10:
2429         s->cm_iclken_dss = value & 0x1;
2430         break;
2431     case 0xe30:
2432         s->cm_autoidle_dss = value & 0x1;
2433         break;
2434     case 0xe40:
2435         s->cm_clksel_dss = value & 0x1f1f;
2436         omap3_cm_dpll4_update(s);
2437         break;
2438    case 0xe44:
2439                 s->cm_sleepdep_dss = value & 0x7;
2440        break;
2441    case 0xe48:
2442                 s->cm_clkstctrl_dss = value & 0x3;
2443        break;
2444
2445     case 0xf00:
2446         s->cm_fclken_cam = value & 0x3;
2447         break;
2448     case 0xf10:
2449         s->cm_iclken_cam = value & 0x1;
2450         break;
2451     case 0xf30:
2452         s->cm_autoidle_cam = value & 0x1;
2453         break;
2454     case 0xf40:
2455         s->cm_clksel_cam = value & 0x1f;
2456         omap3_cm_dpll4_update(s);
2457         break;
2458     case 0xf44:
2459         s->cm_sleepdep_cam = value & 0x2;
2460         break;
2461     case 0xf48:
2462         s->cm_clkstctrl_cam = value & 0x3;
2463         break;
2464
2465     case 0x1000:
2466         s->cm_fclken_per = value & 0x3ffff;
2467         break;
2468     case 0x1010:
2469         s->cm_iclken_per = value & 0x3ffff;
2470         break;
2471
2472     case 0x1030:
2473         s->cm_autoidle_per = value &0x3ffff;
2474         break;
2475     case 0x1040:
2476         s->cm_clksel_per = value & 0xff;
2477         omap3_cm_per_gptimer_update(s);
2478         break;
2479     case 0x1044:
2480         s->cm_sleepdep_per = value & 0x6;
2481         break;
2482     case 0x1048:
2483          s->cm_clkstctrl_per = value &0x7;
2484          break;
2485
2486     case 0x1140:               /*CM_CLKSEL1_EMU */
2487         s->cm_clksel1_emu = value & 0x1f1f3fff;
2488         //printf("cm_clksel1_emu %x\n",s->cm_clksel1_emu);
2489         omap3_cm_dpll3_update(s);
2490         omap3_cm_dpll4_update(s);
2491         break;
2492     case 0x1148:
2493         s->cm_clkstctrl_emu = value & 0x3;
2494         break;
2495          case 0x1150:
2496                  s->cm_clksel2_emu = value & 0xfff7f;
2497                  omap3_cm_dpll3_update(s);
2498         break;
2499     case 0x1154:
2500          s->cm_clksel3_emu = value & 0xfff7f;
2501                  omap3_cm_dpll4_update(s);
2502         break;
2503
2504     case 0x129c:
2505          s->cm_polctrl = value & 0x1;
2506          break;
2507
2508    case 0x1348:
2509                 s->cm_clkstctrl_neon = value & 0x3;
2510                 break;
2511
2512         case 0x1400:
2513                 s->cm_fclken_usbhost = value & 0x3;
2514                 break;
2515         case 0x1410:
2516                 s->cm_iclken_usbhost = value & 0x1;
2517                 break;
2518     case 0x1430:
2519         s->cm_autoidle_usbhost = value & 0x1;
2520         break;
2521     case 0x1444:
2522         s->cm_sleepdep_usbhost = value & 0x6;
2523         break;
2524     case 0x1448:
2525         s->cm_clkstctrl_usbhost = value & 0x3;
2526         break;
2527
2528     default:
2529         printf("omap3_cm_write addr %x value %x pc %x\n", addr, value,cpu_single_env->regs[15] );
2530         exit(-1);
2531     }
2532 }
2533
2534
2535
2536 static CPUReadMemoryFunc *omap3_cm_readfn[] = {
2537     omap_badwidth_read32,
2538     omap_badwidth_read32,
2539     omap3_cm_read,
2540 };
2541
2542 static CPUWriteMemoryFunc *omap3_cm_writefn[] = {
2543     omap_badwidth_write32,
2544     omap_badwidth_write32,
2545     omap3_cm_write,
2546 };
2547
2548 struct omap3_cm_s *omap3_cm_init(struct omap_target_agent_s *ta,
2549                                  qemu_irq mpu_int, qemu_irq dsp_int,
2550                                  qemu_irq iva_int, struct omap_mpu_state_s *mpu)
2551 {
2552     int iomemtype;
2553     struct omap3_cm_s *s = (struct omap3_cm_s *) qemu_mallocz(sizeof(*s));
2554
2555     s->irq[0] = mpu_int;
2556     s->irq[1] = dsp_int;
2557     s->irq[2] = iva_int;
2558     s->mpu = mpu;
2559     omap3_cm_reset(s);
2560
2561     iomemtype = l4_register_io_memory(0, omap3_cm_readfn, omap3_cm_writefn, s);
2562     omap_l4_attach(ta, 0, iomemtype);
2563     omap_l4_attach(ta, 1, iomemtype);
2564
2565     return s;
2566 }
2567
2568 #define OMAP3_SEC_WDT          1
2569 #define OMAP3_MPU_WDT         2
2570 #define OMAP3_IVA2_WDT        3
2571 /*omap3 watchdog timer*/
2572 struct omap3_wdt_s
2573 {
2574     qemu_irq irq;               /*IVA2 IRQ */
2575     struct omap_mpu_state_s *mpu;
2576     omap_clk clk;
2577     QEMUTimer *timer;
2578
2579     int active;
2580     int64_t rate;
2581     int64_t time;
2582     //int64_t ticks_per_sec;
2583
2584     uint32_t wd_sysconfig;
2585     uint32_t wd_sysstatus;
2586     uint32_t wisr;
2587     uint32_t wier;
2588     uint32_t wclr;
2589     uint32_t wcrr;
2590     uint32_t wldr;
2591     uint32_t wtgr;
2592     uint32_t wwps;
2593     uint32_t wspr;
2594
2595     /*pre and ptv in wclr */
2596     uint32_t pre;
2597     uint32_t ptv;
2598     //uint32_t val;
2599
2600     uint16_t writeh;            /* LSB */
2601     uint16_t readh;             /* MSB */
2602
2603 };
2604
2605
2606
2607
2608
2609 static inline void omap3_wdt_timer_update(struct omap3_wdt_s *wdt_timer)
2610 {
2611     int64_t expires;
2612     if (wdt_timer->active)
2613     {
2614         expires = muldiv64(0xffffffffll - wdt_timer->wcrr,
2615                            ticks_per_sec, wdt_timer->rate);
2616         qemu_mod_timer(wdt_timer->timer, wdt_timer->time + expires);
2617     }
2618     else
2619         qemu_del_timer(wdt_timer->timer);
2620 }
2621 static void omap3_wdt_clk_setup(struct omap3_wdt_s *timer)
2622 {
2623     /*TODO: Add irq as user to clk */
2624 }
2625
2626 static inline uint32_t omap3_wdt_timer_read(struct omap3_wdt_s *timer)
2627 {
2628     uint64_t distance;
2629
2630     if (timer->active)
2631     {
2632         distance = qemu_get_clock(vm_clock) - timer->time;
2633         distance = muldiv64(distance, timer->rate, ticks_per_sec);
2634
2635         if (distance >= 0xffffffff - timer->wcrr)
2636             return 0xffffffff;
2637         else
2638             return timer->wcrr + distance;
2639     }
2640     else
2641         return timer->wcrr;
2642 }
2643
2644 /*
2645 static inline void omap3_wdt_timer_sync(struct omap3_wdt_s *timer)
2646 {
2647     if (timer->active) {
2648         timer->val = omap3_wdt_timer_read(timer);
2649         timer->time = qemu_get_clock(vm_clock);
2650     }
2651 }*/
2652
2653 static void omap3_wdt_reset(struct omap3_wdt_s *s, int wdt_index)
2654 {
2655     s->wd_sysconfig = 0x0;
2656     s->wd_sysstatus = 0x0;
2657     s->wisr = 0x0;
2658     s->wier = 0x0;
2659     s->wclr = 0x20;
2660     s->wcrr = 0x0;
2661     switch (wdt_index)
2662     {
2663     case OMAP3_MPU_WDT:
2664     case OMAP3_IVA2_WDT:
2665         s->wldr = 0xfffb0000;
2666         break;
2667     case OMAP3_SEC_WDT:
2668         s->wldr = 0xffa60000;
2669         break;
2670     }
2671     s->wtgr = 0x0;
2672     s->wwps = 0x0;
2673     s->wspr = 0x0;
2674
2675     switch (wdt_index)
2676     {
2677     case OMAP3_SEC_WDT:
2678     case OMAP3_MPU_WDT:
2679         s->active = 1;
2680         break;
2681     case OMAP3_IVA2_WDT:
2682         s->active = 0;
2683         break;
2684     }
2685     s->pre = s->wclr & (1 << 5);
2686     s->ptv = (s->wclr & 0x1c) >> 2;
2687     s->rate = omap_clk_getrate(s->clk) >> (s->pre ? s->ptv : 0);
2688
2689     s->active = 1;
2690     s->time = qemu_get_clock(vm_clock);
2691     omap3_wdt_timer_update(s);
2692 }
2693
2694 static uint32_t omap3_wdt_read32(void *opaque, target_phys_addr_t addr,
2695                                  int wdt_index)
2696 {
2697     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
2698
2699     //uint32_t ret;
2700     //printf("omap3_wdt_read32 addr %x \n",addr);
2701     switch (addr)
2702     {
2703     case 0x10:                 /*WD_SYSCONFIG */
2704         return s->wd_sysconfig;
2705     case 0x14:                 /*WD_SYSSTATUS */
2706         return s->wd_sysstatus;
2707     case 0x18:
2708          /*WISR*/ return s->wisr & 0x1;
2709     case 0x1c:
2710          /*WIER*/ return s->wier & 0x1;
2711     case 0x24:
2712          /*WCLR*/ return s->wclr & 0x3c;
2713     case 0x28:
2714          /*WCRR*/ s->wcrr = omap3_wdt_timer_read(s);
2715         s->time = qemu_get_clock(vm_clock);
2716         return s->wcrr;
2717     case 0x2c:
2718          /*WLDR*/ return s->wldr;
2719     case 0x30:
2720          /*WTGR*/ return s->wtgr;
2721     case 0x34:
2722          /*WWPS*/ return s->wwps;
2723     case 0x48:
2724          /*WSPR*/ return s->wspr;
2725     default:
2726         printf("omap3_wdt_read32 addr %x \n", addr);
2727         exit(-1);
2728     }
2729 }
2730 static uint32_t omap3_mpu_wdt_read16(void *opaque, target_phys_addr_t addr)
2731 {
2732     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
2733     uint32_t ret;
2734
2735     if (addr & 2)
2736         return s->readh;
2737     else
2738     {
2739         ret = omap3_wdt_read32(opaque, addr, OMAP3_MPU_WDT);
2740         s->readh = ret >> 16;
2741         return ret & 0xffff;
2742     }
2743 }
2744 static uint32_t omap3_mpu_wdt_read32(void *opaque, target_phys_addr_t addr)
2745 {
2746     return omap3_wdt_read32(opaque, addr, OMAP3_MPU_WDT);
2747 }
2748
2749 static void omap3_wdt_write32(void *opaque, target_phys_addr_t addr,
2750                               uint32_t value, int wdt_index)
2751 {
2752     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
2753
2754     //printf("omap3_wdt_write32 addr %x value %x \n",addr,value);
2755     switch (addr)
2756     {
2757     case 0x14:                 /*WD_SYSSTATUS */
2758     case 0x34:
2759          /*WWPS*/ OMAP_RO_REG(addr);
2760         exit(-1);
2761         break;
2762     case 0x10:                 /*WD_SYSCONFIG */
2763         s->wd_sysconfig = value & 0x33f;
2764         break;
2765     case 0x18:
2766          /*WISR*/ s->wisr = value & 0x1;
2767         break;
2768     case 0x1c:
2769          /*WIER*/ s->wier = value & 0x1;
2770         break;
2771     case 0x24:
2772          /*WCLR*/ s->wclr = value & 0x3c;
2773         break;
2774     case 0x28:
2775          /*WCRR*/ s->wcrr = value;
2776         s->time = qemu_get_clock(vm_clock);
2777         omap3_wdt_timer_update(s);
2778         break;
2779     case 0x2c:
2780          /*WLDR*/ s->wldr = value;      /*It will take effect after next overflow */
2781         break;
2782     case 0x30:
2783          /*WTGR*/ if (value != s->wtgr)
2784         {
2785             s->wcrr = s->wldr;
2786             s->pre = s->wclr & (1 << 5);
2787             s->ptv = (s->wclr & 0x1c) >> 2;
2788             s->rate = omap_clk_getrate(s->clk) >> (s->pre ? s->ptv : 0);
2789             s->time = qemu_get_clock(vm_clock);
2790             omap3_wdt_timer_update(s);
2791         }
2792         s->wtgr = value;
2793         break;
2794     case 0x48:
2795          /*WSPR*/
2796             if (((value & 0xffff) == 0x5555) && ((s->wspr & 0xffff) == 0xaaaa))
2797         {
2798             s->active = 0;
2799             s->wcrr = omap3_wdt_timer_read(s);
2800             omap3_wdt_timer_update(s);
2801         }
2802         if (((value & 0xffff) == 0x4444) && ((s->wspr & 0xffff) == 0xbbbb))
2803         {
2804             s->active = 1;
2805             s->time = qemu_get_clock(vm_clock);
2806             omap3_wdt_timer_update(s);
2807         }
2808         s->wspr = value;
2809         break;
2810     default:
2811         printf("omap3_wdt_write32 addr %x \n", addr);
2812         exit(-1);
2813     }
2814 }
2815
2816 static void omap3_mpu_wdt_write16(void *opaque, target_phys_addr_t addr,
2817                                   uint32_t value)
2818 {
2819     struct omap3_wdt_s *s = (struct omap3_wdt_s *) opaque;
2820
2821     if (addr & 2)
2822         return omap3_wdt_write32(opaque, addr, (value << 16) | s->writeh,
2823                                  OMAP3_MPU_WDT);
2824     else
2825         s->writeh = (uint16_t) value;
2826 }
2827 static void omap3_mpu_wdt_write32(void *opaque, target_phys_addr_t addr,
2828                                   uint32_t value)
2829 {
2830     omap3_wdt_write32(opaque, addr, value, OMAP3_MPU_WDT);
2831 }
2832
2833
2834 static CPUReadMemoryFunc *omap3_mpu_wdt_readfn[] = {
2835     omap_badwidth_read32,
2836     omap3_mpu_wdt_read16,
2837     omap3_mpu_wdt_read32,
2838 };
2839
2840 static CPUWriteMemoryFunc *omap3_mpu_wdt_writefn[] = {
2841     omap_badwidth_write32,
2842     omap3_mpu_wdt_write16,
2843     omap3_mpu_wdt_write32,
2844 };
2845
2846
2847
2848 static void omap3_mpu_wdt_timer_tick(void *opaque)
2849 {
2850     struct omap3_wdt_s *wdt_timer = (struct omap3_wdt_s *) opaque;
2851
2852     /*TODO:Sent reset pulse to PRCM */
2853     wdt_timer->wcrr = wdt_timer->wldr;
2854
2855     /*after overflow, generate the new wdt_timer->rate */
2856     wdt_timer->pre = wdt_timer->wclr & (1 << 5);
2857     wdt_timer->ptv = (wdt_timer->wclr & 0x1c) >> 2;
2858     wdt_timer->rate =
2859         omap_clk_getrate(wdt_timer->clk) >> (wdt_timer->pre ? wdt_timer->
2860                                              ptv : 0);
2861
2862     wdt_timer->time = qemu_get_clock(vm_clock);
2863     omap3_wdt_timer_update(wdt_timer);
2864 }
2865
2866 static struct omap3_wdt_s *omap3_mpu_wdt_init(struct omap_target_agent_s *ta,
2867                                               qemu_irq irq, omap_clk fclk,
2868                                               omap_clk iclk,
2869                                               struct omap_mpu_state_s *mpu)
2870 {
2871     int iomemtype;
2872     struct omap3_wdt_s *s = (struct omap3_wdt_s *) qemu_mallocz(sizeof(*s));
2873
2874     s->irq = irq;
2875     s->clk = fclk;
2876     s->timer = qemu_new_timer(vm_clock, omap3_mpu_wdt_timer_tick, s);
2877
2878     omap3_wdt_reset(s, OMAP3_MPU_WDT);
2879     if (irq != NULL)
2880         omap3_wdt_clk_setup(s);
2881
2882     iomemtype = l4_register_io_memory(0, omap3_mpu_wdt_readfn,
2883                                       omap3_mpu_wdt_writefn, s);
2884     omap_l4_attach(ta, 0, iomemtype);
2885
2886     return s;
2887
2888 }
2889
2890
2891 /*dummy system control module*/
2892 struct omap3_scm_s
2893 {
2894     struct omap_mpu_state_s *mpu;
2895
2896         uint8 interface[48];           /*0x4800 2000*/
2897         uint8 padconfs[576];         /*0x4800 2030*/
2898         uint32 general[228];            /*0x4800 2270*/
2899         uint8 mem_wkup[1024];     /*0x4800 2600*/
2900         uint8 padconfs_wkup[84]; /*0x4800 2a00*/
2901         uint32 general_wkup[8];    /*0x4800 2a60*/
2902 };
2903
2904 #define PADCONFS_VALUE(wakeup0,wakeup1,offmode0,offmode1, \
2905                                                 inputenable0,inputenable1,pupd0,pupd1,muxmode0,muxmode1,offset) \
2906         do { \
2907                  *(padconfs+offset/4) = (wakeup0 <<14)|(offmode0<<9)|(inputenable0<<8)|(pupd0<<3)|(muxmode0); \
2908                  *(padconfs+offset/4) |= (wakeup1 <<30)|(offmode1<<25)|(inputenable1<<24)|(pupd1<<19)|(muxmode1<<16); \
2909 } while (0)
2910
2911
2912 static void omap3_scm_reset(struct omap3_scm_s *s)
2913 {
2914          uint32 * padconfs;
2915     padconfs = (uint32 *)(s->padconfs);
2916     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x0);
2917     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x4);
2918     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x8);
2919     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0xc);
2920     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x10);
2921     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x14);
2922     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x18);
2923     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x1c);
2924     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x20);
2925     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x24);
2926     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x28);
2927     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x2c);
2928     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x30);
2929     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x34);
2930     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x38);
2931     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x3c);
2932     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x40);
2933     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x44);
2934     PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,7,0x48);
2935     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x4c);
2936     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x50);
2937     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x54);
2938     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x58);
2939     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,0,0x5c);
2940     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x60);
2941     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x64);
2942     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x68);
2943     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x6c);
2944     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x70);
2945     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x74);
2946     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x78);
2947     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x7c);
2948     PADCONFS_VALUE(0,0,0,0,1,1,0,3,0,7,0x80);
2949     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x84);
2950     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x88);
2951     PADCONFS_VALUE(0,0,0,0,1,1,3,0,7,0,0x8c);
2952     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x90);
2953     PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x94);
2954     PADCONFS_VALUE(0,0,0,0,1,1,1,0,7,0,0x98);
2955     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,7,0x9c);
2956     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0xa0);
2957     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0xa4);
2958     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0xa8);
2959     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xac);
2960     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb0);
2961     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb4);
2962     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xb8);
2963     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xbc);
2964     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc0);
2965     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc4);
2966     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xc8);
2967     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xcc);
2968     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd0);
2969     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd4);
2970     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xd8);
2971     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xdc);
2972     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe0);
2973     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe4);
2974     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xe8);
2975     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xec);
2976     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf0);
2977     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf4);
2978     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xf8);
2979     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0xfc);
2980     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x100);
2981     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x104);
2982     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x108);
2983     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x10c);
2984     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x110);
2985     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x114);
2986     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x118);
2987     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x11c);
2988     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x120);
2989     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x124);
2990     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x128);
2991     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x12c);
2992     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x130);
2993     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x134);
2994     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x138);
2995     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x13c);
2996     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x140);
2997     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x144);
2998     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x148);
2999     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x14c);
3000     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x150);
3001     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x154);
3002     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x158);
3003     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x15c);
3004     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x160);
3005     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x164);
3006     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x168);
3007     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x16c);
3008     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x170);
3009     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x174);
3010     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x178);
3011     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x17c);
3012     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x180);
3013     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x184);
3014     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x188);
3015     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x18c);
3016     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x190);
3017     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x194);
3018     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x198);
3019     PADCONFS_VALUE(0,0,0,0,1,1,1,3,7,7,0x19c);
3020     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x1a0);
3021     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1a4);
3022     PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x1a8);
3023     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1ac);
3024     PADCONFS_VALUE(0,0,0,0,1,1,3,1,7,7,0x1b0);
3025     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1b4);
3026     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1b8);
3027     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1bc);
3028     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c0);
3029     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c4);
3030     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c8);
3031     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1cc);
3032     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d0);
3033     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d4);
3034     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1d8);
3035     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1dc);
3036     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e0);
3037     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e4);
3038     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1e8);
3039     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1ec);
3040     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f0);
3041     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f4);
3042     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1f8);
3043     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1fc);
3044     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x200);
3045     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x204);
3046     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x208);
3047     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x20c);
3048     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x210);
3049     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x214);
3050     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x218);
3051     PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x21c);
3052     PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x220);
3053     PADCONFS_VALUE(0,0,0,0,1,1,3,1,0,0,0x224);
3054     PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,0,0x228);
3055     PADCONFS_VALUE(0,0,0,0,1,1,0,1,0,0,0x22c);
3056     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x230);
3057     PADCONFS_VALUE(0,0,0,0,1,1,3,3,7,7,0x234);
3058
3059
3060         padconfs = (uint32 *)(s->general);
3061         s->general[1] = 0x4000000;  /*0x4800 2274*/
3062         s->general[0x1c] = 0x1;  /*0x4800 22e0*/
3063         s->general[0x75] = 0x7fc0;  /*0x4800 2444*/
3064         s->general[0x76] = 0xaa;  /*0x4800 2448*/
3065         s->general[0x7c] = 0x2700;  /*0x4800 2460*/
3066         s->general[0x7d] = 0x300000;  /*0x4800 2464*/
3067         s->general[0x7e] = 0x300000;  /*0x4800 2468*/
3068         s->general[0x81] = 0xffff;  /*0x4800 2474*/
3069         s->general[0x82] = 0xffff;  /*0x4800 2478*/
3070         s->general[0x83] = 0xffff;  /*0x4800 247c*/
3071         s->general[0x84] = 0x6;  /*0x4800 2480*/
3072         s->general[0x85] = 0xffffffff;  /*0x4800 2484*/
3073         s->general[0x86] = 0xffff;  /*0x4800 2488*/
3074         s->general[0x87] = 0xffff;  /*0x4800 248c*/
3075         s->general[0x88] = 0x1;  /*0x4800 2490*/
3076         s->general[0x8b] = 0xffffffff;  /*0x4800 249c*/
3077         s->general[0x8c] = 0xffff;  /*0x4800 24a0*/
3078         s->general[0x8e] = 0xffff;  /*0x4800 24a8*/
3079         s->general[0x8f] = 0xffff;  /*0x4800 24ac*/
3080         s->general[0x91] = 0xffff;  /*0x4800 24b4*/
3081         s->general[0x92] = 0xffff;  /*0x4800 24b8*/
3082         s->general[0xac] = 0x109;  /*0x4800 2520*/
3083         s->general[0xb2] = 0xffff;  /*0x4800 2538*/
3084         s->general[0xb3] = 0xffff;  /*0x4800 253c*/
3085         s->general[0xb4] = 0xffff;  /*0x4800 2540*/
3086         PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x368);
3087     PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x36c);
3088     PADCONFS_VALUE(0,0,0,0,1,1,3,3,4,4,0x370);
3089     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x374);
3090     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x378);
3091     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x37c);
3092     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x380);
3093     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x384);
3094     PADCONFS_VALUE(0,0,0,0,1,1,1,1,4,4,0x388);
3095
3096
3097
3098         padconfs = (uint32 *)(s->padconfs_wkup);
3099         PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x0);
3100         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x4);
3101         PADCONFS_VALUE(0,0,0,0,1,1,3,0,0,0,0x8);
3102         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0xc);
3103         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x10);
3104         PADCONFS_VALUE(0,0,0,0,1,1,0,0,0,0,0x14);
3105         PADCONFS_VALUE(0,0,0,0,1,1,1,1,7,7,0x18);
3106         PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x1c);
3107         PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x20);
3108         PADCONFS_VALUE(0,0,0,0,1,1,3,3,0,0,0x24);
3109         PADCONFS_VALUE(0,0,0,0,1,1,1,1,0,0,0x2c);
3110
3111
3112         s->general_wkup[0] = 0x66ff; /*0x4800 2A60*/
3113
3114 }
3115
3116 static uint32_t omap3_scm_read8(void *opaque, target_phys_addr_t addr)
3117 {
3118     struct omap3_scm_s *s = (struct omap3_scm_s *) opaque;
3119     uint8_t* temp;
3120
3121     switch (addr) {
3122     case 0x00 ... 0x2f:
3123         return s->interface[addr];
3124     case 0x30 ... 0x26f:
3125         return s->padconfs[addr-0x30];
3126     case 0x270 ... 0x5ff:
3127         temp = (uint8_t *)s->general;
3128         return temp[addr-0x270];
3129     case 0x600 ... 0x9ff:
3130         return s->mem_wkup[addr-0x600];
3131     case 0xa00 ... 0xa5f:
3132         return s->padconfs_wkup[addr-0xa00];
3133     case 0xa60 ... 0xa7f:
3134         temp = (uint8_t *)s->general_wkup;
3135         return temp[addr-0xa60];
3136     /* case 0x2f0:
3137         return s->control_status & 0xff;
3138     case 0x2f1:
3139         return (s->control_status & 0xff00) >> 8;
3140     case 0x2f2:
3141         return (s->control_status & 0xff0000) >> 16;
3142     case 0x2f3:
3143         return (s->control_status & 0xff000000) >> 24;    */
3144
3145     default:
3146         break;
3147     }
3148     printf("omap3_scm_read8 addr %x pc %x  \n", addr,cpu_single_env->regs[15] );
3149     return 0;
3150 }
3151
3152 static uint32_t omap3_scm_read16(void *opaque, target_phys_addr_t addr)
3153 {
3154     uint32_t v;
3155     v = omap3_scm_read8(opaque, addr);
3156     v |= omap3_scm_read8(opaque, addr + 1) << 8;
3157     return v;
3158 }
3159
3160 static uint32_t omap3_scm_read32(void *opaque, target_phys_addr_t addr)
3161 {
3162     uint32_t v;
3163     v = omap3_scm_read8(opaque, addr);
3164     v |= omap3_scm_read8(opaque, addr + 1) << 8;
3165     v |= omap3_scm_read8(opaque, addr + 2) << 16;
3166     v |= omap3_scm_read8(opaque, addr + 3) << 24;
3167     return v;
3168 }
3169
3170 static void omap3_scm_write8(void *opaque, target_phys_addr_t addr,
3171                              uint32_t value)
3172 {
3173     struct omap3_scm_s *s = (struct omap3_scm_s *) opaque;
3174     uint8_t* temp;
3175
3176     switch (addr)
3177     {
3178     case 0x00 ... 0x2f:
3179         s->interface[addr] = value;
3180         break;
3181     case 0x30 ... 0x26f:
3182         s->padconfs[addr-0x30] = value;
3183         break;
3184     case 0x270 ... 0x5ff:
3185         temp = (uint8_t *)s->general;
3186         temp[addr-0x270] = value;
3187         break;
3188     case 0x600 ... 0x9ff:
3189         s->mem_wkup[addr-0x600] = value;
3190         break;
3191     case 0xa00 ... 0xa5f:
3192         s->padconfs_wkup[addr-0xa00] = value;
3193         break;
3194     case 0xa60 ... 0xa7f:
3195         temp = (uint8_t *)s->general_wkup;
3196         temp[addr-0xa60] = value;
3197         break;
3198     default:
3199         /*we do not care scm write*/
3200         printf("omap3_scm_write8 addr %x pc %x \n \n", addr,
3201                cpu_single_env->regs[15] - 0x80008000 + 0x80e80000);
3202         exit(1);
3203         //break;
3204     }
3205 }
3206
3207 static void omap3_scm_write16(void *opaque, target_phys_addr_t addr,
3208                               uint32_t value)
3209 {
3210     omap3_scm_write8(opaque, addr + 0, (value) & 0xff);
3211     omap3_scm_write8(opaque, addr + 1, (value >> 8) & 0xff);
3212 }
3213
3214 static void omap3_scm_write32(void *opaque, target_phys_addr_t addr,
3215                               uint32_t value)
3216 {
3217     omap3_scm_write8(opaque, addr + 0, (value) & 0xff);
3218     omap3_scm_write8(opaque, addr + 1, (value >> 8) & 0xff);
3219     omap3_scm_write8(opaque, addr + 2, (value >> 16) & 0xff);
3220     omap3_scm_write8(opaque, addr + 3, (value >> 24) & 0xff);
3221 }
3222
3223 static CPUReadMemoryFunc *omap3_scm_readfn[] = {
3224     omap3_scm_read8,
3225     omap3_scm_read16,
3226     omap3_scm_read32,
3227 };
3228
3229 static CPUWriteMemoryFunc *omap3_scm_writefn[] = {
3230     omap3_scm_write8,
3231     omap3_scm_write16,
3232     omap3_scm_write32,
3233 };
3234
3235 static struct omap3_scm_s *omap3_scm_init(struct omap_target_agent_s *ta,
3236                                           struct omap_mpu_state_s *mpu)
3237 {
3238     int iomemtype;
3239     struct omap3_scm_s *s = (struct omap3_scm_s *) qemu_mallocz(sizeof(*s));
3240
3241     s->mpu = mpu;
3242
3243     omap3_scm_reset(s);
3244
3245     iomemtype = l4_register_io_memory(0, omap3_scm_readfn,
3246                                       omap3_scm_writefn, s);
3247     omap_l4_attach(ta, 0, iomemtype);
3248
3249     return s;
3250 }
3251
3252
3253 /*dummy port protection*/
3254 struct omap3_pm_s
3255 {
3256     struct omap_mpu_state_s *mpu;
3257
3258     uint32_t l3_pm_rt_error_log;        /*0x6801 0020 */
3259     uint32_t l3_pm_rt_control;  /*0x6801 0028 */
3260     uint32_t l3_pm_rt_error_clear_single;       /*0x6801 0030 */
3261     uint32_t l3_pm_rt_error_clear_multi;        /*0x6801 0038 */
3262     uint32_t l3_pm_rt_req_info_permission[2];   /*0x6801 0048 + (0x20*i) */
3263     uint32_t l3_pm_rt_read_permission[2];       /*0x6801 0050 + (0x20*i) */
3264     uint32_t l3_pm_rt_write_permission[2];      /*0x6801 0058 + (0x20*i) */
3265     uint32_t l3_pm_rt_addr_match[1];    /*0x6801 0060 + (0x20*k) */
3266
3267     uint32_t l3_pm_gpmc_error_log;      /*0x6801 2420 */
3268     uint32_t l3_pm_gpmc_control;        /*0x6801 2428 */
3269     uint32_t l3_pm_gpmc_error_clear_single;     /*0x6801 2430 */
3270     uint32_t l3_pm_gpmc_error_clear_multi;      /*0x6801 2438 */
3271     uint32_t l3_pm_gpmc_req_info_permission[8]; /*0x6801 2448 + (0x20*i) */
3272     uint32_t l3_pm_gpmc_read_permission[8];     /*0x6801 2450 + (0x20*i) */
3273     uint32_t l3_pm_gpmc_write_permission[8];    /*0x6801 2458 + (0x20*i) */
3274     uint32_t l3_pm_gpmc_addr_match[7];  /*0x6801 2460 + (0x20*k) */
3275
3276     uint32_t l3_pm_ocmram_error_log;    /*0x6801 2820 */
3277     uint32_t l3_pm_ocmram_control;      /*0x6801 2828 */
3278     uint32_t l3_pm_ocmram_error_clear_single;   /*0x6801 2830 */
3279     uint32_t l3_pm_ocmram_error_clear_multi;    /*0x6801 2838 */
3280     uint32_t l3_pm_ocmram_req_info_permission[8];       /*0x6801 2848 + (0x20*i) */
3281     uint32_t l3_pm_ocmram_read_permission[8];   /*0x6801 2850 + (0x20*i) */
3282     uint32_t l3_pm_ocmram_write_permission[8];  /*0x6801 2858 + (0x20*i) */
3283     uint32_t l3_pm_ocmram_addr_match[7];        /*0x6801 2860 + (0x20*k) */
3284
3285     uint32_t l3_pm_ocmrom_error_log;    /*0x6801 2c20 */
3286     uint32_t l3_pm_ocmrom_control;      /*0x6801 2c28 */
3287     uint32_t l3_pm_ocmrom_error_clear_single;   /*0x6801 2c30 */
3288     uint32_t l3_pm_ocmrom_error_clear_multi;    /*0x6801 2c38 */
3289     uint32_t l3_pm_ocmrom_req_info_permission[2];       /*0x6801 2c48 + (0x20*i) */
3290     uint32_t l3_pm_ocmrom_read_permission[2];   /*0x6801 2c50 + (0x20*i) */
3291     uint32_t l3_pm_ocmrom_write_permission[2];  /*0x6801 2c58 + (0x20*i) */
3292     uint32_t l3_pm_ocmrom_addr_match[1];        /*0x6801 2c60 + (0x20*k) */
3293
3294     uint32_t l3_pm_mad2d_error_log;     /*0x6801 3020 */
3295     uint32_t l3_pm_mad2d_control;       /*0x6801 3028 */
3296     uint32_t l3_pm_mad2d_error_clear_single;    /*0x6801 3030 */
3297     uint32_t l3_pm_mad2d_error_clear_multi;     /*0x6801 3038 */
3298     uint32_t l3_pm_mad2d_req_info_permission[8];        /*0x6801 3048 + (0x20*i) */
3299     uint32_t l3_pm_mad2d_read_permission[8];    /*0x6801 3050 + (0x20*i) */
3300     uint32_t l3_pm_mad2d_write_permission[8];   /*0x6801 3058 + (0x20*i) */
3301     uint32_t l3_pm_mad2d_addr_match[7]; /*0x6801 3060 + (0x20*k) */
3302
3303     uint32_t l3_pm_iva_error_log;       /*0x6801 4020 */
3304     uint32_t l3_pm_iva_control; /*0x6801 4028 */
3305     uint32_t l3_pm_iva_error_clear_single;      /*0x6801 4030 */
3306     uint32_t l3_pm_iva_error_clear_multi;       /*0x6801 4038 */
3307     uint32_t l3_pm_iva_req_info_permission[4];  /*0x6801 4048 + (0x20*i) */
3308     uint32_t l3_pm_iva_read_permission[4];      /*0x6801 4050 + (0x20*i) */
3309     uint32_t l3_pm_iva_write_permission[4];     /*0x6801 4058 + (0x20*i) */
3310     uint32_t l3_pm_iva_addr_match[3];   /*0x6801 4060 + (0x20*k) */
3311 };
3312
3313 static void omap3_pm_reset(struct omap3_pm_s *s)
3314 {
3315     int i;
3316
3317     s->l3_pm_rt_control = 0x3000000;
3318     s->l3_pm_gpmc_control = 0x3000000;
3319     s->l3_pm_ocmram_control = 0x3000000;
3320     s->l3_pm_ocmrom_control = 0x3000000;
3321     s->l3_pm_mad2d_control = 0x3000000;
3322     s->l3_pm_iva_control = 0x3000000;
3323
3324     s->l3_pm_rt_req_info_permission[0] = 0xffff;
3325     s->l3_pm_rt_req_info_permission[1] = 0x0;
3326     for (i = 3; i < 8; i++)
3327         s->l3_pm_gpmc_req_info_permission[i] = 0xffff;
3328     for (i = 1; i < 8; i++)
3329         s->l3_pm_ocmram_req_info_permission[i] = 0xffff;
3330     s->l3_pm_ocmrom_req_info_permission[1] = 0xffff;
3331     for (i = 1; i < 8; i++)
3332         s->l3_pm_mad2d_req_info_permission[i] = 0xffff;
3333     for (i = 1; i < 4; i++)
3334         s->l3_pm_iva_req_info_permission[i] = 0xffff;
3335
3336     s->l3_pm_rt_read_permission[0] = 0x1406;
3337     s->l3_pm_rt_read_permission[1] = 0x1406;
3338     s->l3_pm_rt_write_permission[0] = 0x1406;
3339     s->l3_pm_rt_write_permission[1] = 0x1406;
3340     for (i = 0; i < 8; i++)
3341     {
3342         s->l3_pm_gpmc_read_permission[i] = 0x563e;
3343         s->l3_pm_gpmc_write_permission[i] = 0x563e;
3344     }
3345     for (i = 0; i < 8; i++)
3346     {
3347         s->l3_pm_ocmram_read_permission[i] = 0x5f3e;
3348         s->l3_pm_ocmram_write_permission[i] = 0x5f3e;
3349     }
3350     for (i = 0; i < 2; i++)
3351     {
3352         s->l3_pm_ocmrom_read_permission[i] = 0x1002;
3353         s->l3_pm_ocmrom_write_permission[i] = 0x1002;
3354     }
3355
3356     for (i = 0; i < 8; i++)
3357     {
3358         s->l3_pm_mad2d_read_permission[i] = 0x5f1e;
3359         s->l3_pm_mad2d_write_permission[i] = 0x5f1e;
3360     }
3361
3362     for (i = 0; i < 4; i++)
3363     {
3364         s->l3_pm_iva_read_permission[i] = 0x140e;
3365         s->l3_pm_iva_write_permission[i] = 0x140e;
3366     }
3367
3368
3369     s->l3_pm_rt_addr_match[0] = 0x10230;
3370
3371     s->l3_pm_gpmc_addr_match[0] = 0x10230;
3372 }
3373
3374 static uint32_t omap3_pm_read8(void *opaque, target_phys_addr_t addr)
3375 {
3376     //struct omap3_pm_s *s = (struct omap3_pm_s *) opaque;
3377
3378     switch (addr)
3379     {
3380     default:
3381         printf("omap3_pm_read8 addr %x \n", addr);
3382         exit(-1);
3383     }
3384 }
3385
3386 static uint32_t omap3_pm_read16(void *opaque, target_phys_addr_t addr)
3387 {
3388     uint32_t v;
3389     v = omap3_pm_read8(opaque, addr);
3390     v |= omap3_pm_read8(opaque, addr + 1) << 8;
3391     return v;
3392 }
3393
3394 static uint32_t omap3_pm_read32(void *opaque, target_phys_addr_t addr)
3395 {
3396     uint32_t v;
3397     v = omap3_pm_read8(opaque, addr);
3398     v |= omap3_pm_read8(opaque, addr + 1) << 8;
3399     v |= omap3_pm_read8(opaque, addr + 2) << 16;
3400     v |= omap3_pm_read8(opaque, addr + 3) << 24;
3401     return v;
3402 }
3403
3404 static void omap3_pm_write8(void *opaque, target_phys_addr_t addr,
3405                             uint32_t value)
3406 {
3407     struct omap3_pm_s *s = (struct omap3_pm_s *) opaque;
3408     int i;
3409
3410     switch (addr)
3411     {
3412     case 0x48 ... 0x4b:
3413     case 0x68 ... 0x6b:
3414         i = (addr - 0x48) / 0x20;
3415         s->l3_pm_rt_req_info_permission[i] &=
3416             (~(0xff << ((addr - 0x48 - i * 0x20) * 8)));
3417         s->l3_pm_rt_req_info_permission[i] |=
3418             (value << (addr - 0x48 - i * 0x20) * 8);
3419         break;
3420     case 0x50 ... 0x53:
3421     case 0x70 ... 0x73:
3422         i = (addr - 0x50) / 0x20;
3423         s->l3_pm_rt_read_permission[i] &=
3424             (~(0xff << ((addr - 0x50 - i * 0x20) * 8)));
3425         s->l3_pm_rt_read_permission[i] |=
3426             (value << (addr - 0x50 - i * 0x20) * 8);
3427         break;
3428     case 0x58 ... 0x5b:
3429     case 0x78 ... 0x7b:
3430         i = (addr - 0x58) / 0x20;
3431         s->l3_pm_rt_write_permission[i] &=
3432             (~(0xff << ((addr - 0x58 - i * 0x20) * 8)));
3433         s->l3_pm_rt_write_permission[i] |=
3434             (value << (addr - 0x58 - i * 0x20) * 8);
3435         break;
3436     case 0x60 ... 0x63:
3437         s->l3_pm_rt_addr_match[0] &= (~(0xff << ((addr - 0x60) * 8)));
3438         s->l3_pm_rt_addr_match[0] |= (value << (addr - 0x60) * 8);
3439         break;
3440     case 0x2448 ... 0x244b:
3441     case 0x2468 ... 0x246b:
3442     case 0x2488 ... 0x248b:
3443     case 0x24a8 ... 0x24ab:
3444     case 0x24c8 ... 0x24cb:
3445     case 0x24e8 ... 0x24eb:
3446     case 0x2508 ... 0x250b:
3447     case 0x2528 ... 0x252b:
3448         i = (addr - 0x2448) / 0x20;
3449         s->l3_pm_gpmc_req_info_permission[i] &=
3450             (~(0xff << ((addr - 0x2448 - i * 0x20) * 8)));
3451         s->l3_pm_gpmc_req_info_permission[i] |=
3452             (value << (addr - 0x2448 - i * 0x20) * 8);
3453         break;
3454     case 0x2450 ... 0x2453:
3455     case 0x2470 ... 0x2473:
3456     case 0x2490 ... 0x2493:
3457     case 0x24b0 ... 0x24b3:
3458     case 0x24d0 ... 0x24d3:
3459     case 0x24f0 ... 0x24f3:
3460     case 0x2510 ... 0x2513:
3461     case 0x2530 ... 0x2533:
3462         i = (addr - 0x2450) / 0x20;
3463         s->l3_pm_gpmc_read_permission[i] &=
3464             (~(0xff << ((addr - 0x2450 - i * 0x20) * 8)));
3465         s->l3_pm_gpmc_read_permission[i] |=
3466             (value << (addr - 0x2450 - i * 0x20) * 8);
3467         break;
3468     case 0x2458 ... 0x245b:
3469     case 0x2478 ... 0x247b:
3470     case 0x2498 ... 0x249b:
3471     case 0x24b8 ... 0x24bb:
3472     case 0x24d8 ... 0x24db:
3473     case 0x24f8 ... 0x24fb:
3474     case 0x2518 ... 0x251b:
3475     case 0x2538 ... 0x253b:
3476         i = (addr - 0x2458) / 0x20;
3477         s->l3_pm_gpmc_write_permission[i] &=
3478             (~(0xff << ((addr - 0x2458 - i * 0x20) * 8)));
3479         s->l3_pm_gpmc_write_permission[i] |=
3480             (value << (addr - 0x2458 - i * 0x20) * 8);
3481         break;
3482     case 0x2848 ... 0x284b:
3483     case 0x2868 ... 0x286b:
3484     case 0x2888 ... 0x288b:
3485     case 0x28a8 ... 0x28ab:
3486     case 0x28c8 ... 0x28cb:
3487     case 0x28e8 ... 0x28eb:
3488     case 0x2908 ... 0x290b:
3489     case 0x2928 ... 0x292b:
3490         i = (addr - 0x2848) / 0x20;
3491         s->l3_pm_ocmram_req_info_permission[i] &=
3492             (~(0xff << ((addr - 0x2848 - i * 0x20) * 8)));
3493         s->l3_pm_ocmram_req_info_permission[i] |=
3494             (value << (addr - 0x2848 - i * 0x20) * 8);
3495         break;
3496     case 0x2850 ... 0x2853:
3497     case 0x2870 ... 0x2873:
3498     case 0x2890 ... 0x2893:
3499     case 0x28b0 ... 0x28b3:
3500     case 0x28d0 ... 0x28d3:
3501     case 0x28f0 ... 0x28f3:
3502     case 0x2910 ... 0x2913:
3503     case 0x2930 ... 0x2933:
3504         i = (addr - 0x2850) / 0x20;
3505         s->l3_pm_ocmram_read_permission[i] &=
3506             (~(0xff << ((addr - 0x2850 - i * 0x20) * 8)));
3507         s->l3_pm_ocmram_read_permission[i] |=
3508             (value << (addr - 0x2850 - i * 0x20) * 8);
3509         break;
3510     case 0x2858 ... 0x285b:
3511     case 0x2878 ... 0x287b:
3512     case 0x2898 ... 0x289b:
3513     case 0x28b8 ... 0x28bb:
3514     case 0x28d8 ... 0x28db:
3515     case 0x28f8 ... 0x28fb:
3516     case 0x2918 ... 0x291b:
3517     case 0x2938 ... 0x293b:
3518         i = (addr - 0x2858) / 0x20;
3519         s->l3_pm_ocmram_write_permission[i] &=
3520             (~(0xff << ((addr - 0x2858 - i * 0x20) * 8)));
3521         s->l3_pm_ocmram_write_permission[i] |=
3522             (value << (addr - 0x2858 - i * 0x20) * 8);
3523         break;
3524
3525     case 0x2860 ... 0x2863:
3526     case 0x2880 ... 0x2883:
3527     case 0x28a0 ... 0x28a3:
3528     case 0x28c0 ... 0x28c3:
3529     case 0x28e0 ... 0x28e3:
3530     case 0x2900 ... 0x2903:
3531     case 0x2920 ... 0x2923:
3532         i = (addr - 0x2860) / 0x20;
3533         s->l3_pm_ocmram_addr_match[i] &=
3534             (~(0xff << ((addr - 0x2860 - i * 0x20) * 8)));
3535         s->l3_pm_ocmram_addr_match[i] |=
3536             (value << (addr - 0x2860 - i * 0x20) * 8);
3537         break;
3538
3539     case 0x4048 ... 0x404b:
3540     case 0x4068 ... 0x406b:
3541     case 0x4088 ... 0x408b:
3542     case 0x40a8 ... 0x40ab:
3543         i = (addr - 0x4048) / 0x20;
3544         s->l3_pm_iva_req_info_permission[i] &=
3545             (~(0xff << ((addr - 0x4048 - i * 0x20) * 8)));
3546         s->l3_pm_iva_req_info_permission[i] |=
3547             (value << (addr - 0x4048 - i * 0x20) * 8);
3548         break;
3549     case 0x4050 ... 0x4053:
3550     case 0x4070 ... 0x4073:
3551     case 0x4090 ... 0x4093:
3552     case 0x40b0 ... 0x40b3:
3553         i = (addr - 0x4050) / 0x20;
3554         s->l3_pm_iva_read_permission[i] &=
3555             (~(0xff << ((addr - 0x4050 - i * 0x20) * 8)));
3556         s->l3_pm_iva_read_permission[i] |=
3557             (value << (addr - 0x4050 - i * 0x20) * 8);
3558         break;
3559     case 0x4058 ... 0x405b:
3560     case 0x4078 ... 0x407b:
3561     case 0x4098 ... 0x409b:
3562     case 0x40b8 ... 0x40bb:
3563         i = (addr - 0x4058) / 0x20;
3564         s->l3_pm_iva_write_permission[i] &=
3565             (~(0xff << ((addr - 0x4058 - i * 0x20) * 8)));
3566         s->l3_pm_iva_write_permission[i] |=
3567             (value << (addr - 0x4058 - i * 0x20) * 8);
3568         break;
3569     default:
3570         printf("omap3_pm_write8 addr %x \n", addr);
3571         exit(-1);
3572     }
3573 }
3574
3575 static void omap3_pm_write16(void *opaque, target_phys_addr_t addr,
3576                              uint32_t value)
3577 {
3578     omap3_pm_write8(opaque, addr + 0, (value) & 0xff);
3579     omap3_pm_write8(opaque, addr + 1, (value >> 8) & 0xff);
3580 }
3581
3582 static void omap3_pm_write32(void *opaque, target_phys_addr_t addr,
3583                              uint32_t value)
3584 {
3585     omap3_pm_write8(opaque, addr + 0, (value) & 0xff);
3586     omap3_pm_write8(opaque, addr + 1, (value >> 8) & 0xff);
3587     omap3_pm_write8(opaque, addr + 2, (value >> 16) & 0xff);
3588     omap3_pm_write8(opaque, addr + 3, (value >> 24) & 0xff);
3589 }
3590
3591 static CPUReadMemoryFunc *omap3_pm_readfn[] = {
3592     omap3_pm_read8,
3593     omap3_pm_read16,
3594     omap3_pm_read32,
3595 };
3596
3597 static CPUWriteMemoryFunc *omap3_pm_writefn[] = {
3598     omap3_pm_write8,
3599     omap3_pm_write16,
3600     omap3_pm_write32,
3601 };
3602
3603 static struct omap3_pm_s *omap3_pm_init(struct omap_mpu_state_s *mpu)
3604 {
3605     int iomemtype;
3606     struct omap3_pm_s *s = (struct omap3_pm_s *) qemu_mallocz(sizeof(*s));
3607
3608     s->mpu = mpu;
3609     //s->base = 0x68010000;
3610     //s->size = 0x4400;
3611
3612     omap3_pm_reset(s);
3613
3614     iomemtype = cpu_register_io_memory(0, omap3_pm_readfn, omap3_pm_writefn, s);
3615     cpu_register_physical_memory(0x68010000, 0x4400, iomemtype);
3616
3617     return s;
3618 }
3619
3620 /*dummy SDRAM Memory Scheduler emulation*/
3621 struct omap3_sms_s
3622 {
3623     struct omap_mpu_state_s *mpu;
3624
3625     uint32 sms_sysconfig;
3626     uint32 sms_sysstatus;
3627     uint32 sms_rg_att[8];
3628     uint32 sms_rg_rdperm[8];
3629     uint32 sms_rg_wrperm[8];
3630     uint32 sms_rg_start[7];
3631     uint32 sms_rg_end[7];
3632     uint32 sms_security_control;
3633     uint32 sms_class_arbiter0;
3634     uint32 sms_class_arbiter1;
3635     uint32 sms_class_arbiter2;
3636     uint32 sms_interclass_arbiter;
3637     uint32 sms_class_rotation[3];
3638     uint32 sms_err_addr;
3639     uint32 sms_err_type;
3640     uint32 sms_pow_ctrl;
3641     uint32 sms_rot_control[12];
3642     uint32 sms_rot_size[12];
3643     uint32 sms_rot_physical_ba[12];
3644
3645
3646 };
3647
3648 static uint32_t omap3_sms_read32(void *opaque, target_phys_addr_t addr)
3649 {
3650     struct omap3_sms_s *s = (struct omap3_sms_s *) opaque;
3651
3652     switch (addr)
3653     {
3654     case 0x10:
3655         return s->sms_sysconfig;
3656     case 0x14:
3657         return s->sms_sysstatus;
3658     case 0x48:
3659     case 0x68:
3660     case 0x88:
3661     case 0xa8:
3662     case 0xc8:
3663     case 0xe8:
3664     case 0x108:
3665     case 0x128:
3666         return s->sms_rg_att[(addr-0x48)/0x20];
3667     case 0x50:
3668     case 0x70:
3669     case 0x90:
3670     case 0xb0:
3671     case 0xd0:
3672     case 0xf0:
3673     case 0x110:
3674     case 0x130:
3675         return s->sms_rg_rdperm[(addr-0x50)/0x20];
3676     case 0x58:
3677     case 0x78:
3678     case 0x98:
3679     case 0xb8:
3680     case 0xd8:
3681     case 0xf8:
3682     case 0x118:
3683         return s->sms_rg_wrperm[(addr-0x58)/0x20];
3684     case 0x60:
3685     case 0x80:
3686     case 0xa0:
3687     case 0xc0:
3688     case 0xe0:
3689     case 0x100:
3690     case 0x120:
3691         return s->sms_rg_start[(addr-0x60)/0x20];
3692
3693     case 0x64:
3694     case 0x84:
3695     case 0xa4:
3696     case 0xc4:
3697     case 0xe4:
3698     case 0x104:
3699     case 0x124:
3700         return s->sms_rg_end[(addr-0x64)/0x20];
3701     case 0x140:
3702         return s->sms_security_control;
3703     case 0x150:
3704         return s->sms_class_arbiter0;
3705         case 0x154:
3706                 return s->sms_class_arbiter1;
3707         case 0x158:
3708                 return s->sms_class_arbiter2;
3709         case 0x160:
3710                 return s->sms_interclass_arbiter;
3711         case 0x164:
3712         case 0x168:
3713         case 0x16c:
3714                 return s->sms_class_rotation[(addr-0x164)/4];
3715         case 0x170:
3716                 return s->sms_err_addr;
3717         case 0x174:
3718                 return s->sms_err_type;
3719         case 0x178:
3720                 return s->sms_pow_ctrl;
3721         case 0x180:
3722         case 0x190:
3723         case 0x1a0:
3724         case 0x1b0:
3725         case 0x1c0:
3726         case 0x1d0:
3727         case 0x1e0:
3728         case 0x1f0:
3729         case 0x200:
3730         case 0x210:
3731         case 0x220:
3732         case 0x230:
3733                 return s->sms_rot_control[(addr-0x180)/0x10];
3734         case 0x184:
3735         case 0x194:
3736         case 0x1a4:
3737         case 0x1b4:
3738         case 0x1c4:
3739         case 0x1d4:
3740         case 0x1e4:
3741         case 0x1f4:
3742         case 0x204:
3743         case 0x214:
3744         case 0x224:
3745         case 0x234:
3746                 return s->sms_rot_size[(addr-0x184)/0x10];
3747
3748         case 0x188:
3749         case 0x198:
3750         case 0x1a8:
3751         case 0x1b8:
3752         case 0x1c8:
3753         case 0x1d8:
3754         case 0x1e8:
3755         case 0x1f8:
3756         case 0x208:
3757         case 0x218:
3758         case 0x228:
3759         case 0x238:
3760                 return s->sms_rot_size[(addr-0x188)/0x10];
3761
3762     default:
3763         printf("omap3_sms_read32 addr %x \n", addr);
3764         exit(-1);
3765     }
3766 }
3767
3768 static void omap3_sms_write32(void *opaque, target_phys_addr_t addr,
3769                               uint32_t value)
3770 {
3771     struct omap3_sms_s *s = (struct omap3_sms_s *) opaque;
3772     //int i;
3773
3774     switch (addr)
3775     {
3776     case 0x14:
3777         OMAP_RO_REG(addr);
3778         return;
3779     case 0x10:
3780         s->sms_sysconfig = value & 0x1f;
3781         break;
3782
3783     case 0x48:
3784     case 0x68:
3785     case 0x88:
3786     case 0xa8:
3787     case 0xc8:
3788     case 0xe8:
3789     case 0x108:
3790     case 0x128:
3791         s->sms_rg_att[(addr-0x48)/0x20] = value;
3792         break;
3793     case 0x50:
3794     case 0x70:
3795     case 0x90:
3796     case 0xb0:
3797     case 0xd0:
3798     case 0xf0:
3799     case 0x110:
3800     case 0x130:
3801         s->sms_rg_rdperm[(addr-0x50)/0x20] = value&0xffff;
3802         break;
3803     case 0x58:
3804     case 0x78:
3805     case 0x98:
3806     case 0xb8:
3807     case 0xd8:
3808     case 0xf8:
3809     case 0x118:
3810         s->sms_rg_wrperm[(addr-0x58)/0x20] = value&0xffff;
3811         break;
3812     case 0x60:
3813     case 0x80:
3814     case 0xa0:
3815     case 0xc0:
3816     case 0xe0:
3817     case 0x100:
3818     case 0x120:
3819         s->sms_rg_start[(addr-0x60)/0x20] = value;
3820         break;
3821     case 0x64:
3822     case 0x84:
3823     case 0xa4:
3824     case 0xc4:
3825     case 0xe4:
3826     case 0x104:
3827     case 0x124:
3828         s->sms_rg_end[(addr-0x64)/0x20] = value;
3829         break;
3830     case 0x140:
3831         s->sms_security_control = value &0xfffffff;
3832         break;
3833     case 0x150:
3834         s->sms_class_arbiter0 = value;
3835         break;
3836         case 0x154:
3837                 s->sms_class_arbiter1 = value;
3838                 break;
3839         case 0x158:
3840                 s->sms_class_arbiter2 = value;
3841                 break;
3842         case 0x160:
3843                 s->sms_interclass_arbiter = value;
3844                 break;
3845         case 0x164:
3846         case 0x168:
3847         case 0x16c:
3848                 s->sms_class_rotation[(addr-0x164)/4] = value;
3849                 break;
3850         case 0x170:
3851                 s->sms_err_addr = value;
3852                 break;
3853         case 0x174:
3854                 s->sms_err_type = value;
3855                 break;
3856         case 0x178:
3857                 s->sms_pow_ctrl = value;
3858                 break;
3859         case 0x180:
3860         case 0x190:
3861         case 0x1a0:
3862         case 0x1b0:
3863         case 0x1c0:
3864         case 0x1d0:
3865         case 0x1e0:
3866         case 0x1f0:
3867         case 0x200:
3868         case 0x210:
3869         case 0x220:
3870         case 0x230:
3871                 s->sms_rot_control[(addr-0x180)/0x10] = value;
3872                 break;
3873         case 0x184:
3874         case 0x194:
3875         case 0x1a4:
3876         case 0x1b4:
3877         case 0x1c4:
3878         case 0x1d4:
3879         case 0x1e4:
3880         case 0x1f4:
3881         case 0x204:
3882         case 0x214:
3883         case 0x224:
3884         case 0x234:
3885                 s->sms_rot_size[(addr-0x184)/0x10] = value;
3886                 break;
3887
3888         case 0x188:
3889         case 0x198:
3890         case 0x1a8:
3891         case 0x1b8:
3892         case 0x1c8:
3893         case 0x1d8:
3894         case 0x1e8:
3895         case 0x1f8:
3896         case 0x208:
3897         case 0x218:
3898         case 0x228:
3899         case 0x238:
3900                 s->sms_rot_size[(addr-0x188)/0x10] = value;
3901                 break;
3902         default:
3903         printf("omap3_sms_write32 addr %x\n", addr);
3904         exit(-1);
3905     }
3906 }
3907
3908 static CPUReadMemoryFunc *omap3_sms_readfn[] = {
3909     omap_badwidth_read32,
3910     omap_badwidth_read32,
3911     omap3_sms_read32,
3912 };
3913
3914 static CPUWriteMemoryFunc *omap3_sms_writefn[] = {
3915     omap_badwidth_write32,
3916     omap_badwidth_write32,
3917     omap3_sms_write32,
3918 };
3919
3920 static void omap3_sms_reset(struct omap3_sms_s *s)
3921 {
3922         s->sms_sysconfig = 0x1;
3923         s->sms_class_arbiter0 = 0x500000;
3924         s->sms_class_arbiter1 = 0x500;
3925         s->sms_class_arbiter2 = 0x55000;
3926         s->sms_interclass_arbiter = 0x400040;
3927         s->sms_class_rotation[0] = 0x1;
3928         s->sms_class_rotation[1] = 0x1;
3929         s->sms_class_rotation[2] = 0x1;
3930         s->sms_pow_ctrl = 0x80;
3931 }
3932
3933 static struct omap3_sms_s *omap3_sms_init(struct omap_mpu_state_s *mpu)
3934 {
3935     int iomemtype;
3936     struct omap3_sms_s *s = (struct omap3_sms_s *) qemu_mallocz(sizeof(*s));
3937
3938     s->mpu = mpu;
3939
3940     omap3_sms_reset(s);
3941
3942     iomemtype = cpu_register_io_memory(0, omap3_sms_readfn,
3943                                        omap3_sms_writefn, s);
3944     cpu_register_physical_memory(0x6c000000, 0x10000, iomemtype);
3945
3946     return s;
3947 }
3948
3949 static const struct dma_irq_map omap3_dma_irq_map[] = {
3950     {0, OMAP_INT_35XX_SDMA_IRQ0},
3951     {0, OMAP_INT_35XX_SDMA_IRQ1},
3952     {0, OMAP_INT_35XX_SDMA_IRQ2},
3953     {0, OMAP_INT_35XX_SDMA_IRQ3},
3954 };
3955
3956 static int omap3_validate_addr(struct omap_mpu_state_s *s,
3957                                target_phys_addr_t addr)
3958 {
3959     return 1;
3960 }
3961
3962 /*
3963   set the kind of memory connected to GPMC that we are trying to boot form.
3964   Uses SYS BOOT settings.
3965 */
3966 void omap3_set_mem_type(struct omap_mpu_state_s *s,int bootfrom)
3967 {
3968         switch (bootfrom)
3969         {
3970                 case 0x0: /*GPMC_NOR*/
3971                         s->omap3_scm->general[32] |= 7;
3972                         break;
3973                 case 0x1: /*GPMC_NAND*/
3974                         s->omap3_scm->general[32] |= 1;
3975                         break;
3976                 case 0x2:
3977                         s->omap3_scm->general[32] |= 8;
3978                         break;
3979                 case 0x3:
3980                         s->omap3_scm->general[32] |= 0;
3981                         break;
3982                 case 0x4:
3983                         s->omap3_scm->general[32] |= 17;
3984                         break;
3985                 case 0x5:
3986                         s->omap3_scm->general[32] |= 3;
3987                         break;
3988         }
3989 }
3990
3991 void omap3_set_device_type(struct omap_mpu_state_s *s,int device_type)
3992 {
3993         s->omap3_scm->general[32] |= (device_type & 0x7) << 8;
3994 }
3995
3996 struct omap_mpu_state_s *omap3530_mpu_init(unsigned long sdram_size,
3997                                            const char *core)
3998 {
3999     struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
4000         qemu_mallocz(sizeof(struct omap_mpu_state_s));
4001     ram_addr_t sram_base, q2_base;
4002     qemu_irq *cpu_irq;
4003     qemu_irq dma_irqs[4];
4004     int i;
4005     int sdindex;
4006     //omap_clk gpio_clks[4];
4007
4008
4009     s->mpu_model = omap3530;
4010     s->env = cpu_init("cortex-a8-r2");
4011     if (!s->env)
4012     {
4013         fprintf(stderr, "Unable to find CPU definition\n");
4014         exit(1);
4015     }
4016     s->sdram_size = sdram_size;
4017     s->sram_size = OMAP3530_SRAM_SIZE;
4018
4019     sdindex = drive_get_index(IF_SD, 0, 0);
4020     if (sdindex == -1) {
4021         fprintf(stderr, "qemu: missing SecureDigital device\n");
4022         exit(1);
4023     }
4024
4025     /* Clocks */
4026     omap_clk_init(s);
4027
4028     /* Memory-mapped stuff */
4029
4030     q2_base = qemu_ram_alloc(s->sdram_size);
4031     cpu_register_physical_memory(OMAP3_Q2_BASE, s->sdram_size,
4032                                  (q2_base | IO_MEM_RAM));
4033     sram_base = qemu_ram_alloc(s->sram_size);
4034     cpu_register_physical_memory(OMAP3_SRAM_BASE, s->sram_size,
4035                                  (sram_base | IO_MEM_RAM));
4036
4037     s->l4 = omap_l4_init(OMAP3_L4_BASE,
4038                          sizeof(omap3_l4_agent_info)
4039                          / sizeof(struct omap_l4_agent_info_s));
4040
4041     cpu_irq = arm_pic_init_cpu(s->env);
4042     s->ih[0] = omap2_inth_init(s, 0x48200000, 0x1000, 3, &s->irq[0],
4043                                cpu_irq[ARM_PIC_CPU_IRQ],
4044                                cpu_irq[ARM_PIC_CPU_FIQ],
4045                                omap_findclk(s, "omap3_mpu_intc_fclk"),
4046                                omap_findclk(s, "omap3_mpu_intc_iclk"));
4047
4048     for (i = 0; i < 4; i++)
4049         dma_irqs[i] =
4050             s->irq[omap3_dma_irq_map[i].ih][omap3_dma_irq_map[i].intr];
4051     s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
4052                             omap_findclk(s, "omap3_sdma_fclk"),
4053                             omap_findclk(s, "omap3_sdma_iclk"));
4054     s->port->addr_valid = omap3_validate_addr;
4055
4056
4057     /* Register SDRAM and SRAM ports for fast DMA transfers.  */
4058     soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
4059     soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
4060
4061
4062     s->omap3_cm = omap3_cm_init(omap3_l4ta_get(s->l4, L4A_CM), NULL, NULL, NULL, s);
4063
4064     s->omap3_prm = omap3_prm_init(omap3_l4ta_get(s->l4, L4A_PRM),
4065                                   s->irq[0][OMAP_INT_35XX_PRCM_MPU_IRQ],
4066                                   NULL, s);
4067
4068     s->omap3_mpu_wdt = omap3_mpu_wdt_init(omap3_l4ta_get(s->l4, L4A_WDTIMER2),
4069                                           NULL,
4070                                           omap_findclk(s, "omap3_wkup_32k_fclk"),
4071                                           omap_findclk(s, "omap3_wkup_l4_iclk"),
4072                                           s);
4073
4074     s->omap3_scm = omap3_scm_init(omap3_l4ta_get(s->l4, L4A_SCM), s);
4075
4076     s->omap3_pm = omap3_pm_init(s);
4077     s->omap3_sms = omap3_sms_init(s);
4078
4079     s->gptimer[0] = omap_gp_timer_init(omap3_l4ta_get(s->l4, L4A_GPTIMER1),
4080                                        s->irq[0][OMAP_INT_35XX_GPTIMER1],
4081                                        omap_findclk(s, "omap3_gp1_fclk"),
4082                                        omap_findclk(s, "omap3_wkup_l4_iclk"));
4083     s->gptimer[1] = omap_gp_timer_init(omap3_l4ta_get(s->l4, L4A_GPTIMER2),
4084                                        s->irq[0][OMAP_INT_35XX_GPTIMER2],
4085                                        omap_findclk(s, "omap3_gp2_fclk"),
4086                                        omap_findclk(s, "omap3_per_l4_iclk"));
4087     s->gptimer[2] = omap_gp_timer_init(omap3_l4ta_get(s->l4, L4A_GPTIMER3),
4088                                        s->irq[0][OMAP_INT_35XX_GPTIMER3],
4089                                        omap_findclk(s, "omap3_gp3_fclk"),
4090                                        omap_findclk(s, "omap3_per_l4_iclk"));
4091     s->gptimer[3] = omap_gp_timer_init(omap3_l4ta_get(s->l4, L4A_GPTIMER4),
4092                                        s->irq[0][OMAP_INT_35XX_GPTIMER4],
4093                                        omap_findclk(s, "omap3_gp4_fclk"),
4094                                        omap_findclk(s, "omap3_per_l4_iclk"));
4095     s->gptimer[4] = omap_gp_timer_init(omap3_l4ta_get(s->l4, L4A_GPTIMER5),
4096                                        s->irq[0][OMAP_INT_35XX_GPTIMER5],
4097                                        omap_findclk(s, "omap3_gp5_fclk"),
4098                                        omap_findclk(s, "omap3_per_l4_iclk"));
4099     s->gptimer[5] = omap_gp_timer_init(omap3_l4ta_get(s->l4, L4A_GPTIMER6),
4100                                        s->irq[0][OMAP_INT_35XX_GPTIMER6],
4101                                        omap_findclk(s, "omap3_gp6_fclk"),
4102                                        omap_findclk(s, "omap3_per_l4_iclk"));
4103     s->gptimer[6] = omap_gp_timer_init(omap3_l4ta_get(s->l4, L4A_GPTIMER7),
4104                                        s->irq[0][OMAP_INT_35XX_GPTIMER7],
4105                                        omap_findclk(s, "omap3_gp7_fclk"),
4106                                        omap_findclk(s, "omap3_per_l4_iclk"));
4107     s->gptimer[7] = omap_gp_timer_init(omap3_l4ta_get(s->l4, L4A_GPTIMER8),
4108                                        s->irq[0][OMAP_INT_35XX_GPTIMER8],
4109                                        omap_findclk(s, "omap3_gp8_fclk"),
4110                                        omap_findclk(s, "omap3_per_l4_iclk"));
4111     s->gptimer[8] = omap_gp_timer_init(omap3_l4ta_get(s->l4, L4A_GPTIMER9),
4112                                        s->irq[0][OMAP_INT_35XX_GPTIMER9],
4113                                        omap_findclk(s, "omap3_gp9_fclk"),
4114                                        omap_findclk(s, "omap3_per_l4_iclk"));
4115     s->gptimer[9] = omap_gp_timer_init(omap3_l4ta_get(s->l4, L4A_GPTIMER10),
4116                                        s->irq[0][OMAP_INT_35XX_GPTIMER10],
4117                                        omap_findclk(s, "omap3_gp10_fclk"),
4118                                        omap_findclk(s, "omap3_core_l4_iclk"));
4119     s->gptimer[10] = omap_gp_timer_init(omap3_l4ta_get(s->l4, L4A_GPTIMER11),
4120                                        s->irq[0][OMAP_INT_35XX_GPTIMER11],
4121                                        omap_findclk(s, "omap3_gp12_fclk"),
4122                                        omap_findclk(s, "omap3_core_l4_iclk"));
4123     s->gptimer[11] = omap_gp_timer_init(omap3_l4ta_get(s->l4, L4A_GPTIMER12),
4124                                         s->irq[0][OMAP_INT_35XX_GPTIMER12],
4125                                         omap_findclk(s, "omap3_gp12_fclk"),
4126                                         omap_findclk(s, "omap3_wkup_l4_iclk"));
4127
4128
4129     omap_synctimer_init(omap3_l4ta_get(s->l4, L4A_32KTIMER), s,
4130                         omap_findclk(s, "omap3_sys_32k"), NULL);
4131
4132     s->sdrc = omap_sdrc_init(0x6d000000);
4133
4134     s->gpmc = omap_gpmc_init(s, 0x6e000000, s->irq[0][OMAP_INT_35XX_GPMC_IRQ]);
4135
4136
4137     s->uart[0] = omap2_uart_init(omap3_l4ta_get(s->l4, L4A_UART1),
4138                                  s->irq[0][OMAP_INT_35XX_UART1_IRQ],
4139                                  omap_findclk(s, "omap3_uart1_fclk"),
4140                                  omap_findclk(s, "omap3_uart1_iclk"),
4141                                  s->drq[OMAP35XX_DMA_UART1_TX],
4142                                  s->drq[OMAP35XX_DMA_UART1_RX], serial_hds[0]);
4143     s->uart[1] = omap2_uart_init(omap3_l4ta_get(s->l4, L4A_UART2),
4144                                  s->irq[0][OMAP_INT_35XX_UART2_IRQ],
4145                                  omap_findclk(s, "omap3_uart2_fclk"),
4146                                  omap_findclk(s, "omap3_uart2_iclk"),
4147                                  s->drq[OMAP35XX_DMA_UART2_TX],
4148                                  s->drq[OMAP35XX_DMA_UART2_RX],
4149                                  serial_hds[0] ? serial_hds[1] : 0);
4150     s->uart[2] = omap2_uart_init(omap3_l4ta_get(s->l4, L4A_UART3),
4151                                  s->irq[0][OMAP_INT_35XX_UART3_IRQ],
4152                                  omap_findclk(s, "omap3_uart2_fclk"),
4153                                  omap_findclk(s, "omap3_uart3_iclk"),
4154                                  s->drq[OMAP35XX_DMA_UART3_TX],
4155                                  s->drq[OMAP35XX_DMA_UART3_RX],
4156                                  serial_hds[0]
4157                                  && serial_hds[1] ? serial_hds[2] : 0);
4158
4159     /*attach serial[0] to uart 2 for beagle board */
4160     omap_uart_attach(s->uart[2], serial_hds[0]);
4161
4162     s->dss = omap_dss_init(omap3_l4ta_get(s->l4, L4A_DSS), 0x68005400,
4163                     s->irq[0][OMAP_INT_35XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
4164                    NULL,NULL,NULL,NULL,NULL,1);
4165
4166     //gpio_clks[0] = NULL;
4167     //gpio_clks[1] = NULL;
4168     //gpio_clks[2] = NULL;
4169     //gpio_clks[3] = NULL;
4170
4171     s->gpif = omap3_gpif_init();
4172     omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, L4A_GPIO1),
4173                     &s->irq[0][OMAP_INT_35XX_GPIO_BANK1],
4174                     NULL,NULL,0);
4175     omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, L4A_GPIO2),
4176                     &s->irq[0][OMAP_INT_35XX_GPIO_BANK2],
4177                     NULL,NULL,1);
4178     omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, L4A_GPIO3),
4179                     &s->irq[0][OMAP_INT_35XX_GPIO_BANK3],
4180                     NULL,NULL,2);
4181     omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, L4A_GPIO4),
4182                     &s->irq[0][OMAP_INT_35XX_GPIO_BANK4],
4183                     NULL,NULL,3);
4184     omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, L4A_GPIO5),
4185                     &s->irq[0][OMAP_INT_35XX_GPIO_BANK5],
4186                     NULL,NULL,4);
4187     omap3_gpio_init(s, s->gpif ,omap3_l4ta_get(s->l4, L4A_GPIO6),
4188                     &s->irq[0][OMAP_INT_35XX_GPIO_BANK6],
4189                     NULL,NULL,5);
4190
4191     omap_tap_init(omap3_l4ta_get(s->l4, L4A_TAP), s);
4192
4193     s->omap3_mmc[0] = omap3_mmc_init(omap3_l4ta_get(s->l4, L4A_MMC1),
4194                                      drives_table[sdindex].bdrv,
4195                                      s->irq[0][OMAP_INT_35XX_MMC1_IRQ],
4196                                      &s->drq[OMAP35XX_DMA_MMC1_TX],
4197                                      omap_findclk(s, "omap3_mmc1_fclk"),
4198                                      omap_findclk(s, "omap3_mmc1_iclk"));
4199
4200     s->omap3_mmc[1] = omap3_mmc_init(omap3_l4ta_get(s->l4, L4A_MMC2),
4201                                      NULL,
4202                                      s->irq[0][OMAP_INT_35XX_MMC2_IRQ],
4203                                      &s->drq[OMAP35XX_DMA_MMC2_TX],
4204                                      omap_findclk(s, "omap3_mmc2_fclk"),
4205                                      omap_findclk(s, "omap3_mmc2_iclk"));
4206
4207     s->omap3_mmc[2] = omap3_mmc_init(omap3_l4ta_get(s->l4, L4A_MMC3),
4208                                      NULL,
4209                                      s->irq[0][OMAP_INT_35XX_MMC3_IRQ],
4210                                      &s->drq[OMAP35XX_DMA_MMC3_TX],
4211                                      omap_findclk(s, "omap3_mmc3_fclk"),
4212                                      omap_findclk(s, "omap3_mmc3_iclk"));
4213
4214     s->i2c[0] = omap3_i2c_init(omap3_l4ta_get(s->l4, L4A_I2C1),
4215                                s->irq[0][OMAP_INT_35XX_I2C1_IRQ],
4216                                &s->drq[OMAP35XX_DMA_I2C1_TX],
4217                                omap_findclk(s, "omap3_i2c1_fclk"),
4218                                omap_findclk(s, "omap3_i2c1_iclk"),
4219                                8);
4220     s->i2c[1] = omap3_i2c_init(omap3_l4ta_get(s->l4, L4A_I2C2),
4221                                s->irq[0][OMAP_INT_35XX_I2C2_IRQ],
4222                                &s->drq[OMAP35XX_DMA_I2C2_TX],
4223                                omap_findclk(s, "omap3_i2c2_fclk"),
4224                                omap_findclk(s, "omap3_i2c2_iclk"),
4225                                8);
4226     s->i2c[2] = omap3_i2c_init(omap3_l4ta_get(s->l4, L4A_I2C3),
4227                                s->irq[0][OMAP_INT_35XX_I2C3_IRQ],
4228                                &s->drq[OMAP35XX_DMA_I2C3_TX],
4229                                omap_findclk(s, "omap3_i2c3_fclk"),
4230                                omap_findclk(s, "omap3_i2c3_iclk"),
4231                                64);
4232
4233     return s;
4234 }
4235
4236
4237 static uint32_t omap3_get_le32(void *p)
4238 {
4239     uint8_t *q = (uint8_t *)p;
4240     uint32_t v;
4241     v = q[3]; v <<= 8;
4242     v |= q[2]; v <<= 8;
4243     v |= q[1]; v <<= 8;
4244     v |= q[0];
4245     return v;
4246 }
4247
4248 static uint32_t omap3_get_le16(void *p)
4249 {
4250     uint8_t *q = (uint8_t *)p;
4251     uint32_t v;
4252     v = q[1]; v <<= 8;
4253     v |= q[0];
4254     return v;
4255 }
4256
4257 /* returns ptr to matching dir entry / zero entry or 0 if unsuccessful */
4258 static uint8_t *omap3_scan_fat_dir_sector(uint8_t *s)
4259 {
4260     int i;
4261
4262     /* there are 0x10 items with 0x20 bytes per item */
4263     for (i = 0x10; i--; s += 0x20) {
4264         if (*s == 0xe5 || (s[0x0b] & 0x0f) == 0x0f) continue; /* erased/LFN */
4265         if (!*s || !strncasecmp((void *)s, "mlo        ", 8+3)) return s;
4266     }
4267     return 0;
4268 }
4269
4270 struct omap3_fat_drv_s {
4271     BlockDriverState *bs;
4272     uint8_t ptype; // 12, 16, 32
4273     uint64_t c0;   // physical byte offset for data cluster 0
4274     uint64_t fat;  // physical byte offset for used FAT sector 0
4275     uint32_t spc;  // sectors per cluster
4276 };
4277
4278 /* returns cluster data in the buffer and next cluster chain number
4279    or 0 if unsuccessful */
4280 static uint32_t omap3_read_fat_cluster(uint8_t *data,
4281                                        struct omap3_fat_drv_s *drv,
4282                                        uint32_t cl)
4283 {
4284     uint8_t buf[ 4 ];
4285     uint32_t len = drv->spc * 0x200; // number of bytes to read
4286
4287     switch (drv->ptype) { /* check for EOF */
4288         case 12: if (cl > 0xff0) return 0; break;
4289         case 16: if (cl > 0xfff0) return 0; break;
4290         case 32: if (cl > 0x0ffffff0) return 0; break;
4291         default: return 0;
4292     }
4293
4294     if (bdrv_pread(drv->bs,
4295                    drv->c0 + ((drv->ptype == 32 ? cl - 2 : cl) * len),
4296                    data, len) != len)
4297         return 0;
4298
4299     switch (drv->ptype) { /* determine next cluster # */
4300         case 12:
4301             fprintf(stderr, "%s: FAT12 parsing not implemented!\n",
4302                     __FUNCTION__);
4303             break;
4304         case 16:
4305             return (bdrv_pread(drv->bs, drv->fat + cl * 2, buf, 2) != 2)
4306             ? 0 : omap3_get_le16(buf);
4307         case 32:
4308             return (bdrv_pread(drv->bs, drv->fat + cl * 4, buf, 4) != 4)
4309             ? 0 : omap3_get_le32(buf) & 0x0fffffff;
4310         default:
4311             break;
4312     }
4313     return 0;
4314 }
4315
4316 static int omap3_mmc_fat_boot(BlockDriverState *bs,
4317                               uint8_t *sector,
4318                               uint32_t pstart,
4319                               struct omap_mpu_state_s *mpu)
4320 {
4321     struct omap3_fat_drv_s drv;
4322     uint32_t i, j, k, cluster0, fatsize, bootsize, rootsize;
4323     uint32_t img_size, img_addr;
4324     uint8_t *p, *q;
4325     int result = 0;
4326
4327     /* determine FAT type */
4328
4329     drv.bs = bs;
4330     fatsize = omap3_get_le16(sector + 0x16);
4331     if (!fatsize)
4332         fatsize = omap3_get_le32(sector + 0x24);
4333     bootsize = omap3_get_le16(sector + 0x0e);
4334     cluster0 = bootsize + fatsize * sector[0x10];
4335     rootsize = omap3_get_le16(sector + 0x11);
4336     if (rootsize & 0x0f)
4337         rootsize += 0x10;
4338     rootsize >>= 4;
4339     drv.spc = sector[0x0d];
4340     i = omap3_get_le16(sector + 0x13);
4341     if (!i)
4342         i = omap3_get_le32(sector + 0x20);
4343     i = (i - (cluster0 + rootsize)) / drv.spc;
4344     drv.ptype = (i < 4085) ? 12 : (i < 65525) ? 16 : 32;
4345
4346     /* search for boot loader file */
4347
4348     drv.fat = (bootsize + pstart) * 0x200;
4349     drv.c0 = (cluster0 + pstart) * 0x200;
4350     if (drv.ptype == 32) {
4351         i = omap3_get_le32(sector + 0x2c); /* first root cluster # */
4352         j = omap3_get_le16(sector + 0x28);
4353         if (j & 0x80)
4354             drv.fat += (j & 0x0f) * fatsize * 0x200;
4355         uint8_t *cluster = qemu_mallocz(drv.spc * 0x200);
4356         for (p = 0; !p && (i = omap3_read_fat_cluster(cluster, &drv, i)); ) {
4357             for (j = drv.spc, q=cluster; j-- & !p; q += 0x200)
4358                 p = omap3_scan_fat_dir_sector(q);
4359             if (p)
4360                 memcpy(sector, q - 0x200, 0x200); // save the sector
4361         }
4362         free(cluster);
4363     } else { /* FAT12/16 */
4364         for (i = rootsize, j = 0, p = 0; i-- && !p; j++) {
4365             if (bdrv_pread(drv.bs, drv.c0 + j * 0x200, sector, 0x200) != 0x200)
4366                 break;
4367             p = omap3_scan_fat_dir_sector(sector);
4368         }
4369     }
4370
4371     if (p && *p) { // did we indeed find the file?
4372         i = omap3_get_le16(p + 0x14);
4373         i <<= 16;
4374         i |= omap3_get_le16(p + 0x1a);
4375         j = drv.spc * 0x200;
4376         uint8 *data = qemu_mallocz(j);
4377         if ((i = omap3_read_fat_cluster(data, &drv, i))) {
4378             /* TODO: support HS device boot
4379                for now only GP device is supported */
4380             img_size = omap3_get_le32(data);
4381             img_addr = omap3_get_le32(data + 4);
4382             mpu->env->regs[15] = img_addr;
4383             cpu_physical_memory_write(img_addr, data + 8,
4384                                       (k = (j - 8 >= img_size) ? img_size : j - 8));
4385             for (img_addr += k, img_size -= k;
4386                  img_size && (i = omap3_read_fat_cluster(data, &drv, i));
4387                  img_addr += k, img_size -= k) {
4388                 cpu_physical_memory_write(img_addr, data,
4389                                           (k = (j >= img_size) ? img_size : j));
4390             }
4391             result = 1;
4392         } else
4393             fprintf(stderr, "%s: unable to read MLO file contents from SD card\n",
4394                     __FUNCTION__);
4395         free(data);
4396     } else
4397         fprintf(stderr, "%s: MLO file not found in the root directory\n",
4398                 __FUNCTION__);
4399
4400     return result;
4401 }
4402
4403 static int omap3_mmc_raw_boot(BlockDriverState *bs,
4404                               uint8_t *sector,
4405                               struct omap_mpu_state_s *mpu)
4406 {
4407     return 0;
4408 }
4409
4410 /* returns non-zero if successful, zero if unsuccessful */
4411 int omap3_mmc_boot(struct omap_mpu_state_s *s)
4412 {
4413     BlockDriverState *bs;
4414     int sdindex = drive_get_index(IF_SD, 0, 0);
4415     uint8_t sector[0x200], *p;
4416     uint32_t pstart, i;
4417
4418     /* very simple implementation, supports only two modes:
4419        1. MBR partition table with an active FAT partition
4420           and boot loader file (MLO) in its root directory, or
4421        2. boot loader located on first sector */
4422     if (sdindex >= 0) {
4423         bs = drives_table[sdindex].bdrv;
4424         if (bdrv_pread(bs, 0, sector, 0x200) == 0x200) {
4425             for (i = 0, p = sector + 0x1be; i < 4; i++, p += 0x10)
4426                 if (p[0] == 0x80) break;
4427             if (sector[0x1fe] == 0x55 && sector[0x1ff] == 0xaa /* signature */
4428                 && i < 4 /* active partition exists */
4429                 && (p[4] == 1 || p[4] == 4 || p[4] == 6 || p[4] == 11
4430                     || p[4] == 12 || p[4] == 14 || p[4] == 15) /* FAT */
4431                 && bdrv_pread(bs, (pstart = omap3_get_le32(p + 8)) * 0x200,
4432                               sector, 0x200) == 0x200
4433                 && sector[0x1fe] == 0x55 && sector[0x1ff] == 0xaa)
4434                 return omap3_mmc_fat_boot(bs, sector, pstart, s);
4435             else
4436                 return omap3_mmc_raw_boot(bs, sector, s);
4437         }
4438     }
4439     return 0;
4440 }
4441