2 * TI OMAP3 High-Speed USB Host and OTG Controller emulation.
4 * Copyright (C) 2009 Nokia Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 #include "qemu-common.h"
21 #include "qemu-timer.h"
28 #define OMAP3_HSUSB_DEBUG
30 #ifdef OMAP3_HSUSB_DEBUG
31 #define TRACE(fmt,...) fprintf(stderr, "%s: " fmt "\n", __FUNCTION__, ##__VA_ARGS__)
37 extern CPUReadMemoryFunc *musb_read[];
38 extern CPUWriteMemoryFunc *musb_write[];
40 struct omap3_hsusb_otg_s {
52 static void omap3_hsusb_otg_save_state(QEMUFile *f, void *opaque)
54 struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
56 qemu_put_be16(f, s->sysconfig);
57 qemu_put_byte(f, s->interfsel);
58 qemu_put_byte(f, s->simenable);
59 qemu_put_byte(f, s->forcestdby);
62 static int omap3_hsusb_otg_load_state(QEMUFile *f, void *opaque,
65 struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
70 s->sysconfig = qemu_get_be16(f);
71 s->interfsel = qemu_get_byte(f);
72 s->simenable = qemu_get_byte(f);
73 s->forcestdby = qemu_get_byte(f);
78 static void omap3_hsusb_otg_reset(struct omap3_hsusb_otg_s *s)
87 static uint32_t omap3_hsusb_otg_readb(void *opaque, target_phys_addr_t addr)
89 struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
91 return musb_read[0](s->musb, addr);
93 return musb_read[0](s->musb, 0x20 + ((addr >> 3 ) & 0x3c));
98 static uint32_t omap3_hsusb_otg_readh(void *opaque, target_phys_addr_t addr)
100 struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
102 return musb_read[1](s->musb, addr);
104 return musb_read[1](s->musb, 0x20 + ((addr >> 3 ) & 0x3c));
109 static uint32_t omap3_hsusb_otg_read(void *opaque, target_phys_addr_t addr)
111 struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
114 return musb_read[2](s->musb, addr);
116 return musb_read[2](s->musb, 0x20 + ((addr >> 3 ) & 0x3c));
119 case 0x400: /* OTG_REVISION */
120 TRACE("OTG_REVISION: 0x%08x", s->rev);
122 case 0x404: /* OTG_SYSCONFIG */
123 TRACE("OTG_SYSCONFIG: 0x%08x", s->sysconfig);
125 case 0x408: /* OTG_SYSSTATUS */
126 TRACE("OTG_SYSSTATUS: 0x00000001");
127 return 1; /* reset finished */
128 case 0x40c: /* OTG_INTERFSEL */
129 TRACE("OTG_INTERFSEL: 0x%08x", s->interfsel);
131 case 0x410: /* OTG_SIMENABLE */
132 TRACE("OTG_SIMENABLE: 0x%08x", s->simenable);
134 case 0x414: /* OTG_FORCESTDBY */
135 TRACE("OTG_FORCESTDBY: 0x%08x", s->forcestdby);
136 return s->forcestdby;
144 static void omap3_hsusb_otg_writeb(void *opaque, target_phys_addr_t addr,
147 struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
150 musb_write[0](s->musb, addr, value);
151 else if (addr < 0x400)
152 musb_write[0](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
157 static void omap3_hsusb_otg_writeh(void *opaque, target_phys_addr_t addr,
160 struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
163 musb_write[1](s->musb, addr, value);
164 else if (addr < 0x400)
165 musb_write[1](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
170 static void omap3_hsusb_otg_write(void *opaque, target_phys_addr_t addr,
173 struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
176 musb_write[2](s->musb, addr, value);
177 else if (addr < 0x400)
178 musb_write[2](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
180 case 0x400: /* OTG_REVISION */
181 case 0x408: /* OTG_SYSSTATUS */
182 OMAP_RO_REGV(addr, value);
184 case 0x404: /* OTG_SYSCONFIG */
185 TRACE("OTG_SYSCONFIG = 0x%08x", value);
186 if (value & 2) /* SOFTRESET */
187 omap3_hsusb_otg_reset(s);
188 s->sysconfig = value & 0x301f;
190 case 0x40c: /* OTG_INTERFSEL */
191 TRACE("OTG_INTERFSEL = 0x%08x", value);
192 s->interfsel = value & 0x3;
194 case 0x410: /* OTG_SIMENABLE */
195 TRACE("OTG_SIMENABLE = 0x%08x", value);
196 cpu_abort(cpu_single_env,
197 "%s: USB simulation mode not supported\n",
200 case 0x414: /* OTG_FORCESTDBY */
201 TRACE("OTG_FORCESTDBY = 0x%08x", value);
202 s->forcestdby = value & 1;
205 OMAP_BAD_REGV(addr, value);
210 static CPUReadMemoryFunc *omap3_hsusb_otg_readfn[] = {
211 omap3_hsusb_otg_readb,
212 omap3_hsusb_otg_readh,
213 omap3_hsusb_otg_read,
216 static CPUWriteMemoryFunc *omap3_hsusb_otg_writefn[] = {
217 omap3_hsusb_otg_writeb,
218 omap3_hsusb_otg_writeh,
219 omap3_hsusb_otg_write,
222 static void omap3_hsusb_musb_core_intr(void *opaque, int source, int level)
224 struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
225 uint32_t value = musb_core_intr_get(s->musb);
226 TRACE("intr 0x%08x, 0x%08x, 0x%08x", source, level, value);
229 TRACE("ignoring VBUS");
231 case musb_set_session:
232 TRACE("ignoring SESSION");
242 qemu_set_irq(s->mc_irq, level);
245 static void omap3_hsusb_otg_init(struct omap_target_agent_s *otg_ta,
248 struct omap3_hsusb_otg_s *s)
251 s->dma_irq = dma_irq;
253 omap_l4_attach(otg_ta, 0, l4_register_io_memory(0,
254 omap3_hsusb_otg_readfn,
255 omap3_hsusb_otg_writefn,
258 s->musb = musb_init(qemu_allocate_irqs(omap3_hsusb_musb_core_intr, s,
260 omap3_hsusb_otg_reset(s);
262 register_savevm("omap3_hsusb_otg", -1, 0,
263 omap3_hsusb_otg_save_state,
264 omap3_hsusb_otg_load_state,
268 struct omap3_hsusb_host_s {
272 uint32_t uhh_sysconfig;
273 uint32_t uhh_hostconfig;
274 uint32_t uhh_debug_csr;
277 static void omap3_hsusb_host_save_state(QEMUFile *f, void *opaque)
279 struct omap3_hsusb_host_s *s = (struct omap3_hsusb_host_s *)opaque;
281 qemu_put_be32(f, s->uhh_sysconfig);
282 qemu_put_be32(f, s->uhh_hostconfig);
283 qemu_put_be32(f, s->uhh_debug_csr);
286 static int omap3_hsusb_host_load_state(QEMUFile *f, void *opaque,
289 struct omap3_hsusb_host_s *s = (struct omap3_hsusb_host_s *)opaque;
294 s->uhh_sysconfig = qemu_get_be32(f);
295 s->uhh_hostconfig = qemu_get_be32(f);
296 s->uhh_debug_csr = qemu_get_be32(f);
301 static void omap3_hsusb_host_reset(struct omap3_hsusb_host_s *s)
303 s->uhh_sysconfig = 1;
304 s->uhh_hostconfig = 0x700;
305 s->uhh_debug_csr = 0x20;
306 /* TODO: perform OHCI & EHCI reset */
309 static uint32_t omap3_hsusb_host_read(void *opaque, target_phys_addr_t addr)
311 struct omap3_hsusb_host_s *s = (struct omap3_hsusb_host_s *)opaque;
314 case 0x00: /* UHH_REVISION */
316 case 0x10: /* UHH_SYSCONFIG */
317 return s->uhh_sysconfig;
318 case 0x14: /* UHH_SYSSTATUS */
319 return 0x7; /* EHCI_RESETDONE | OHCI_RESETDONE | RESETDONE */
320 case 0x40: /* UHH_HOSTCONFIG */
321 return s->uhh_hostconfig;
322 case 0x44: /* UHH_DEBUG_CSR */
323 return s->uhh_debug_csr;
331 static void omap3_hsusb_host_write(void *opaque, target_phys_addr_t addr,
334 struct omap3_hsusb_host_s *s = (struct omap3_hsusb_host_s *)opaque;
337 case 0x00: /* UHH_REVISION */
338 case 0x14: /* UHH_SYSSTATUS */
339 OMAP_RO_REGV(addr, value);
341 case 0x10: /* UHH_SYSCONFIG */
342 s->uhh_sysconfig = value & 0x311d;
343 if (value & 2) { /* SOFTRESET */
344 omap3_hsusb_host_reset(s);
347 case 0x40: /* UHH_HOSTCONFIG */
348 s->uhh_hostconfig = value & 0x1f3d;
350 case 0x44: /* UHH_DEBUG_CSR */
351 s->uhh_debug_csr = value & 0xf00ff;
354 OMAP_BAD_REGV(addr, value);
359 static CPUReadMemoryFunc *omap3_hsusb_host_readfn[] = {
360 omap_badwidth_read32,
361 omap_badwidth_read32,
362 omap3_hsusb_host_read,
365 static CPUWriteMemoryFunc *omap3_hsusb_host_writefn[] = {
366 omap_badwidth_write32,
367 omap_badwidth_write32,
368 omap3_hsusb_host_write,
371 static uint32_t omap3_hsusb_ehci_read(void *opaque, target_phys_addr_t addr)
373 TRACE(OMAP_FMT_plx, addr);
377 static void omap3_hsusb_ehci_write(void *opaque, target_phys_addr_t addr,
380 TRACE(OMAP_FMT_plx " = 0x%08x", addr, value);
383 static CPUReadMemoryFunc *omap3_hsusb_ehci_readfn[] = {
384 omap_badwidth_read32,
385 omap_badwidth_read32,
386 omap3_hsusb_ehci_read,
389 static CPUWriteMemoryFunc *omap3_hsusb_ehci_writefn[] = {
390 omap_badwidth_write32,
391 omap_badwidth_write32,
392 omap3_hsusb_ehci_write,
395 static uint32_t omap3_hsusb_tll_read(void *opaque, target_phys_addr_t addr)
397 TRACE(OMAP_FMT_plx, addr);
401 static void omap3_hsusb_tll_write(void *opaque, target_phys_addr_t addr,
404 TRACE(OMAP_FMT_plx " = 0x%08x", addr, value);
407 static CPUReadMemoryFunc *omap3_hsusb_tll_readfn[] = {
408 omap_badwidth_read32,
409 omap_badwidth_read32,
410 omap3_hsusb_tll_read,
413 static CPUWriteMemoryFunc *omap3_hsusb_tll_writefn[] = {
414 omap_badwidth_write32,
415 omap_badwidth_write32,
416 omap3_hsusb_tll_write,
419 static void omap3_hsusb_host_init(struct omap_target_agent_s *host_ta,
420 struct omap_target_agent_s *tll_ta,
424 struct omap3_hsusb_host_s *s)
426 s->ehci_irq = ehci_irq;
427 s->tll_irq = tll_irq;
429 omap_l4_attach(tll_ta, 0, l4_register_io_memory(0,
430 omap3_hsusb_tll_readfn,
431 omap3_hsusb_tll_writefn,
433 omap_l4_attach(host_ta, 0, l4_register_io_memory(0,
434 omap3_hsusb_host_readfn,
435 omap3_hsusb_host_writefn,
437 omap_l4_attach(host_ta, 1, usb_ohci_init_omap(omap_l4_base(host_ta, 1),
438 omap_l4_size(host_ta, 1),
440 omap_l4_attach(host_ta, 2, l4_register_io_memory(0,
441 omap3_hsusb_ehci_readfn,
442 omap3_hsusb_ehci_writefn,
445 omap3_hsusb_host_reset(s);
447 register_savevm("omap3_hsusb_host", -1, 0,
448 omap3_hsusb_host_save_state,
449 omap3_hsusb_host_load_state, s);
452 struct omap3_hsusb_s {
453 struct omap3_hsusb_otg_s otg;
454 struct omap3_hsusb_host_s host;
457 struct omap3_hsusb_s *omap3_hsusb_init(struct omap_target_agent_s *otg_ta,
458 struct omap_target_agent_s *host_ta,
459 struct omap_target_agent_s *tll_ta,
466 struct omap3_hsusb_s *s = qemu_mallocz(sizeof(struct omap3_hsusb_s));
467 omap3_hsusb_otg_init(otg_ta, mc_irq, dma_irq, &s->otg);
468 omap3_hsusb_host_init(host_ta, tll_ta,
469 ohci_irq, ehci_irq, tll_irq,