3 /* PC-style peripherals (also used by other machines). */
7 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
8 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
9 qemu_irq irq, CharDriverState *chr,
11 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
12 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
13 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
14 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
15 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
16 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
20 typedef struct ParallelState ParallelState;
21 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
22 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
26 typedef struct PicState2 PicState2;
27 extern PicState2 *isa_pic;
28 void pic_set_irq(int irq, int level);
29 void pic_set_irq_new(void *opaque, int irq, int level);
30 qemu_irq *i8259_init(qemu_irq parent_irq);
31 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
32 void *alt_irq_opaque);
33 int pic_read_irq(PicState2 *s);
34 void pic_update_irq(PicState2 *s);
35 uint32_t pic_intack_read(PicState2 *s);
40 typedef struct IOAPICState IOAPICState;
42 int apic_init(CPUState *env);
43 int apic_accept_pic_intr(CPUState *env);
44 int apic_get_interrupt(CPUState *env);
45 IOAPICState *ioapic_init(void);
46 void ioapic_set_irq(void *opaque, int vector, int level);
50 #define PIT_FREQ 1193182
52 typedef struct PITState PITState;
54 PITState *pit_init(int base, qemu_irq irq);
55 void pit_set_gate(PITState *pit, int channel, int val);
56 int pit_get_gate(PITState *pit, int channel);
57 int pit_get_initial_count(PITState *pit, int channel);
58 int pit_get_mode(PITState *pit, int channel);
59 int pit_get_out(PITState *pit, int channel, int64_t current_time);
62 void vmport_init(void);
63 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
66 void *vmmouse_init(void *m);
70 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
71 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
72 target_phys_addr_t base, int it_shift);
76 typedef struct RTCState RTCState;
78 RTCState *rtc_init(int base, qemu_irq irq);
79 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
80 void rtc_set_memory(RTCState *s, int addr, int val);
81 void rtc_set_date(RTCState *s, const struct tm *tm);
84 extern int fd_bootchk;
86 void ioport_set_a20(int enable);
87 int ioport_get_a20(void);
90 extern int acpi_enabled;
91 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
93 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
94 void acpi_bios_init(void);
97 void pcspk_init(PITState *);
98 int pcspk_audio_init(AudioState *, qemu_irq *pic);
101 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
102 void i440fx_set_smm(PCIDevice *d, int val);
103 int piix3_init(PCIBus *bus, int devfn);
104 void i440fx_init_memory_mappings(PCIDevice *d);
106 int piix4_init(PCIBus *bus, int devfn);
111 #define VGA_RAM_SIZE (8192 * 1024)
113 #define VGA_RAM_SIZE (9 * 1024 * 1024)
116 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
117 unsigned long vga_ram_offset, int vga_ram_size);
118 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
119 unsigned long vga_ram_offset, int vga_ram_size,
120 unsigned long vga_bios_offset, int vga_bios_size);
121 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
122 unsigned long vga_ram_offset, int vga_ram_size,
123 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
127 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
128 unsigned long vga_ram_offset, int vga_ram_size);
129 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
130 unsigned long vga_ram_offset, int vga_ram_size);
133 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
134 BlockDriverState *hd0, BlockDriverState *hd1);
135 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
136 int secondary_ide_enabled);
137 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
139 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
144 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);