4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "virtio-net.h"
36 pci_set_irq_fn set_irq;
37 pci_map_irq_fn map_irq;
38 uint32_t config_reg; /* XXX: suppress */
40 SetIRQFunc *low_set_irq;
42 PCIDevice *devices[256];
43 PCIDevice *parent_dev;
45 /* The bus IRQ state is the logical OR of the connected devices.
46 Keep a count of the number of devices with raised IRQs. */
51 static void pci_update_mappings(PCIDevice *d);
52 static void pci_set_irq(void *opaque, int irq_num, int level);
54 target_phys_addr_t pci_mem_base;
55 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
56 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
57 static int pci_irq_index;
58 static PCIBus *first_bus;
60 static void pcibus_save(QEMUFile *f, void *opaque)
62 PCIBus *bus = (PCIBus *)opaque;
65 qemu_put_be32(f, bus->nirq);
66 for (i = 0; i < bus->nirq; i++)
67 qemu_put_be32(f, bus->irq_count[i]);
70 static int pcibus_load(QEMUFile *f, void *opaque, int version_id)
72 PCIBus *bus = (PCIBus *)opaque;
78 nirq = qemu_get_be32(f);
79 if (bus->nirq != nirq) {
80 fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
85 for (i = 0; i < nirq; i++)
86 bus->irq_count[i] = qemu_get_be32(f);
91 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
92 qemu_irq *pic, int devfn_min, int nirq)
97 bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
98 bus->set_irq = set_irq;
99 bus->map_irq = map_irq;
100 bus->irq_opaque = pic;
101 bus->devfn_min = devfn_min;
103 bus->next = first_bus;
105 register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
109 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
112 bus = qemu_mallocz(sizeof(PCIBus));
113 bus->map_irq = map_irq;
114 bus->parent_dev = dev;
115 bus->next = dev->bus->next;
116 dev->bus->next = bus;
120 int pci_bus_num(PCIBus *s)
125 void pci_device_save(PCIDevice *s, QEMUFile *f)
129 qemu_put_be32(f, 2); /* PCI device version */
130 qemu_put_buffer(f, s->config, 256);
131 for (i = 0; i < 4; i++)
132 qemu_put_be32(f, s->irq_state[i]);
135 int pci_device_load(PCIDevice *s, QEMUFile *f)
140 version_id = qemu_get_be32(f);
143 qemu_get_buffer(f, s->config, 256);
144 pci_update_mappings(s);
147 for (i = 0; i < 4; i ++)
148 s->irq_state[i] = qemu_get_be32(f);
153 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
157 id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
158 id[0] = cpu_to_le16(pci_default_sub_vendor_id);
159 id[1] = cpu_to_le16(pci_default_sub_device_id);
164 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
166 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
171 unsigned long dom = 0, bus = 0;
175 val = strtoul(p, &e, 16);
181 val = strtoul(p, &e, 16);
188 val = strtoul(p, &e, 16);
194 if (dom > 0xffff || bus > 0xff || val > 0x1f)
202 /* Note: QEMU doesn't implement domains other than 0 */
203 if (dom != 0 || pci_find_bus(bus) == NULL)
212 int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
216 if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
219 return pci_parse_devaddr(devaddr, domp, busp, slotp);
222 int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
226 if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
229 if (!strcmp(devaddr, "auto")) {
232 /* want to support dom/bus auto-assign at some point */
236 return pci_parse_devaddr(devaddr, domp, busp, slotp);
239 /* -1 for devfn means auto assign */
240 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
241 int instance_size, int devfn,
242 PCIConfigReadFunc *config_read,
243 PCIConfigWriteFunc *config_write)
247 if (pci_irq_index >= PCI_DEVICES_MAX)
251 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
252 if (!bus->devices[devfn])
258 pci_dev = qemu_mallocz(instance_size);
260 pci_dev->devfn = devfn;
261 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
262 memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
263 pci_set_default_subsystem_id(pci_dev);
266 config_read = pci_default_read_config;
268 config_write = pci_default_write_config;
269 pci_dev->config_read = config_read;
270 pci_dev->config_write = config_write;
271 pci_dev->irq_index = pci_irq_index++;
272 bus->devices[devfn] = pci_dev;
273 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
277 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
279 return addr + pci_mem_base;
282 static void pci_unregister_io_regions(PCIDevice *pci_dev)
287 for(i = 0; i < PCI_NUM_REGIONS; i++) {
288 r = &pci_dev->io_regions[i];
289 if (!r->size || r->addr == -1)
291 if (r->type == PCI_ADDRESS_SPACE_IO) {
292 isa_unassign_ioport(r->addr, r->size);
294 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
301 int pci_unregister_device(PCIDevice *pci_dev)
305 if (pci_dev->unregister)
306 ret = pci_dev->unregister(pci_dev);
310 pci_unregister_io_regions(pci_dev);
312 qemu_free_irqs(pci_dev->irq);
314 pci_dev->bus->devices[pci_dev->devfn] = NULL;
319 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
320 uint32_t size, int type,
321 PCIMapIORegionFunc *map_func)
326 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
329 if (size & (size-1)) {
330 fprintf(stderr, "ERROR: PCI region size must be pow2 "
331 "type=0x%x, size=0x%x\n", type, size);
335 r = &pci_dev->io_regions[region_num];
339 r->map_func = map_func;
340 if (region_num == PCI_ROM_SLOT) {
343 addr = 0x10 + region_num * 4;
345 *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
348 static void pci_update_mappings(PCIDevice *d)
352 uint32_t last_addr, new_addr, config_ofs;
354 cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
355 for(i = 0; i < PCI_NUM_REGIONS; i++) {
356 r = &d->io_regions[i];
357 if (i == PCI_ROM_SLOT) {
360 config_ofs = 0x10 + i * 4;
363 if (r->type & PCI_ADDRESS_SPACE_IO) {
364 if (cmd & PCI_COMMAND_IO) {
365 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
367 new_addr = new_addr & ~(r->size - 1);
368 last_addr = new_addr + r->size - 1;
369 /* NOTE: we have only 64K ioports on PC */
370 if (last_addr <= new_addr || new_addr == 0 ||
371 last_addr >= 0x10000) {
378 if (cmd & PCI_COMMAND_MEMORY) {
379 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
381 /* the ROM slot has a specific enable bit */
382 if (i == PCI_ROM_SLOT && !(new_addr & 1))
384 new_addr = new_addr & ~(r->size - 1);
385 last_addr = new_addr + r->size - 1;
386 /* NOTE: we do not support wrapping */
387 /* XXX: as we cannot support really dynamic
388 mappings, we handle specific values as invalid
390 if (last_addr <= new_addr || new_addr == 0 ||
399 /* now do the real mapping */
400 if (new_addr != r->addr) {
402 if (r->type & PCI_ADDRESS_SPACE_IO) {
404 /* NOTE: specific hack for IDE in PC case:
405 only one byte must be mapped. */
406 class = d->config[0x0a] | (d->config[0x0b] << 8);
407 if (class == 0x0101 && r->size == 4) {
408 isa_unassign_ioport(r->addr + 2, 1);
410 isa_unassign_ioport(r->addr, r->size);
413 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
416 qemu_unregister_coalesced_mmio(r->addr, r->size);
421 r->map_func(d, i, r->addr, r->size, r->type);
428 uint32_t pci_default_read_config(PCIDevice *d,
429 uint32_t address, int len)
436 if (address <= 0xfc) {
437 val = le32_to_cpu(*(uint32_t *)(d->config + address));
442 if (address <= 0xfe) {
443 val = le16_to_cpu(*(uint16_t *)(d->config + address));
448 val = d->config[address];
454 void pci_default_write_config(PCIDevice *d,
455 uint32_t address, uint32_t val, int len)
460 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
461 (address >= 0x30 && address < 0x34))) {
465 if ( address >= 0x30 ) {
468 reg = (address - 0x10) >> 2;
470 r = &d->io_regions[reg];
473 /* compute the stored value */
474 if (reg == PCI_ROM_SLOT) {
475 /* keep ROM enable bit */
476 val &= (~(r->size - 1)) | 1;
478 val &= ~(r->size - 1);
481 *(uint32_t *)(d->config + address) = cpu_to_le32(val);
482 pci_update_mappings(d);
486 /* not efficient, but simple */
488 for(i = 0; i < len; i++) {
489 /* default read/write accesses */
490 switch(d->config[0x0e]) {
505 case 0x10 ... 0x27: /* base */
506 case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
507 case 0x30 ... 0x33: /* rom */
530 case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
531 case 0x38 ... 0x3b: /* rom */
542 /* Mask out writes to reserved bits in registers */
545 val &= ~PCI_COMMAND_RESERVED_MASK_HI;
548 val &= ~PCI_STATUS_RESERVED_MASK_LO;
551 val &= ~PCI_STATUS_RESERVED_MASK_HI;
554 d->config[addr] = val;
562 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
563 /* if the command register is modified, we must modify the mappings */
564 pci_update_mappings(d);
568 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
572 int config_addr, bus_num;
574 #if defined(DEBUG_PCI) && 0
575 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
578 bus_num = (addr >> 16) & 0xff;
579 while (s && s->bus_num != bus_num)
583 pci_dev = s->devices[(addr >> 8) & 0xff];
586 config_addr = addr & 0xff;
587 #if defined(DEBUG_PCI)
588 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
589 pci_dev->name, config_addr, val, len);
591 pci_dev->config_write(pci_dev, config_addr, val, len);
594 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
598 int config_addr, bus_num;
601 bus_num = (addr >> 16) & 0xff;
602 while (s && s->bus_num != bus_num)
606 pci_dev = s->devices[(addr >> 8) & 0xff];
623 config_addr = addr & 0xff;
624 val = pci_dev->config_read(pci_dev, config_addr, len);
625 #if defined(DEBUG_PCI)
626 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
627 pci_dev->name, config_addr, val, len);
630 #if defined(DEBUG_PCI) && 0
631 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
637 /***********************************************************/
638 /* generic PCI irq support */
640 /* 0 <= irq_num <= 3. level must be 0 or 1 */
641 static void pci_set_irq(void *opaque, int irq_num, int level)
643 PCIDevice *pci_dev = (PCIDevice *)opaque;
647 change = level - pci_dev->irq_state[irq_num];
651 pci_dev->irq_state[irq_num] = level;
654 irq_num = bus->map_irq(pci_dev, irq_num);
657 pci_dev = bus->parent_dev;
659 bus->irq_count[irq_num] += change;
660 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
663 /***********************************************************/
664 /* monitor info on PCI */
671 static const pci_class_desc pci_class_descriptions[] =
673 { 0x0100, "SCSI controller"},
674 { 0x0101, "IDE controller"},
675 { 0x0102, "Floppy controller"},
676 { 0x0103, "IPI controller"},
677 { 0x0104, "RAID controller"},
678 { 0x0106, "SATA controller"},
679 { 0x0107, "SAS controller"},
680 { 0x0180, "Storage controller"},
681 { 0x0200, "Ethernet controller"},
682 { 0x0201, "Token Ring controller"},
683 { 0x0202, "FDDI controller"},
684 { 0x0203, "ATM controller"},
685 { 0x0280, "Network controller"},
686 { 0x0300, "VGA controller"},
687 { 0x0301, "XGA controller"},
688 { 0x0302, "3D controller"},
689 { 0x0380, "Display controller"},
690 { 0x0400, "Video controller"},
691 { 0x0401, "Audio controller"},
693 { 0x0480, "Multimedia controller"},
694 { 0x0500, "RAM controller"},
695 { 0x0501, "Flash controller"},
696 { 0x0580, "Memory controller"},
697 { 0x0600, "Host bridge"},
698 { 0x0601, "ISA bridge"},
699 { 0x0602, "EISA bridge"},
700 { 0x0603, "MC bridge"},
701 { 0x0604, "PCI bridge"},
702 { 0x0605, "PCMCIA bridge"},
703 { 0x0606, "NUBUS bridge"},
704 { 0x0607, "CARDBUS bridge"},
705 { 0x0608, "RACEWAY bridge"},
707 { 0x0c03, "USB controller"},
711 static void pci_info_device(PCIDevice *d)
713 Monitor *mon = cur_mon;
716 const pci_class_desc *desc;
718 monitor_printf(mon, " Bus %2d, device %3d, function %d:\n",
719 d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
720 class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
721 monitor_printf(mon, " ");
722 desc = pci_class_descriptions;
723 while (desc->desc && class != desc->class)
726 monitor_printf(mon, "%s", desc->desc);
728 monitor_printf(mon, "Class %04x", class);
730 monitor_printf(mon, ": PCI device %04x:%04x\n",
731 le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
732 le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
734 if (d->config[PCI_INTERRUPT_PIN] != 0) {
735 monitor_printf(mon, " IRQ %d.\n",
736 d->config[PCI_INTERRUPT_LINE]);
738 if (class == 0x0604) {
739 monitor_printf(mon, " BUS %d.\n", d->config[0x19]);
741 for(i = 0;i < PCI_NUM_REGIONS; i++) {
742 r = &d->io_regions[i];
744 monitor_printf(mon, " BAR%d: ", i);
745 if (r->type & PCI_ADDRESS_SPACE_IO) {
746 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
747 r->addr, r->addr + r->size - 1);
749 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
750 r->addr, r->addr + r->size - 1);
754 if (class == 0x0604 && d->config[0x19] != 0) {
755 pci_for_each_device(d->config[0x19], pci_info_device);
759 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
761 PCIBus *bus = first_bus;
765 while (bus && bus->bus_num != bus_num)
768 for(devfn = 0; devfn < 256; devfn++) {
769 d = bus->devices[devfn];
776 void pci_info(Monitor *mon)
778 pci_for_each_device(0, pci_info_device);
781 static const char * const pci_nic_models[] = {
793 typedef PCIDevice *(*PCINICInitFn)(PCIBus *, NICInfo *, int);
795 static PCINICInitFn pci_nic_init_fns[] = {
807 /* Initialize a PCI NIC. */
808 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
809 const char *default_model)
814 qemu_check_nic_model_list(nd, pci_nic_models, default_model);
816 for (i = 0; pci_nic_models[i]; i++)
817 if (strcmp(nd->model, pci_nic_models[i]) == 0) {
818 pci_dev = pci_nic_init_fns[i](bus, nd, devfn);
820 nd->private = pci_dev;
832 static void pci_bridge_write_config(PCIDevice *d,
833 uint32_t address, uint32_t val, int len)
835 PCIBridge *s = (PCIBridge *)d;
837 if (address == 0x19 || (address == 0x18 && len > 1)) {
839 s->bus->bus_num = val & 0xff;
841 s->bus->bus_num = (val >> 8) & 0xff;
842 #if defined(DEBUG_PCI)
843 printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
846 pci_default_write_config(d, address, val, len);
849 PCIBus *pci_find_bus(int bus_num)
851 PCIBus *bus = first_bus;
853 while (bus && bus->bus_num != bus_num)
859 PCIDevice *pci_find_device(int bus_num, int slot, int function)
861 PCIBus *bus = pci_find_bus(bus_num);
866 return bus->devices[PCI_DEVFN(slot, function)];
869 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
870 pci_map_irq_fn map_irq, const char *name)
873 s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
874 devfn, NULL, pci_bridge_write_config);
876 pci_config_set_vendor_id(s->dev.config, vid);
877 pci_config_set_device_id(s->dev.config, did);
879 s->dev.config[0x04] = 0x06; // command = bus master, pci mem
880 s->dev.config[0x05] = 0x00;
881 s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
882 s->dev.config[0x07] = 0x00; // status = fast devsel
883 s->dev.config[0x08] = 0x00; // revision
884 s->dev.config[0x09] = 0x00; // programming i/f
885 pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
886 s->dev.config[0x0D] = 0x10; // latency_timer
887 s->dev.config[PCI_HEADER_TYPE] =
888 PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
889 s->dev.config[0x1E] = 0xa0; // secondary status
891 s->bus = pci_register_secondary_bus(&s->dev, map_irq);