4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 pci_set_irq_fn set_irq;
32 uint32_t config_reg; /* XXX: suppress */
34 SetIRQFunc *low_set_irq;
36 PCIDevice *devices[256];
39 static void pci_update_mappings(PCIDevice *d);
41 target_phys_addr_t pci_mem_base;
42 static int pci_irq_index;
43 static PCIBus *first_bus;
45 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, void *pic, int devfn_min)
48 bus = qemu_mallocz(sizeof(PCIBus));
49 bus->set_irq = set_irq;
50 bus->irq_opaque = pic;
51 bus->devfn_min = devfn_min;
56 int pci_bus_num(PCIBus *s)
61 void pci_device_save(PCIDevice *s, QEMUFile *f)
63 qemu_put_be32(f, 1); /* PCI device version */
64 qemu_put_buffer(f, s->config, 256);
67 int pci_device_load(PCIDevice *s, QEMUFile *f)
70 version_id = qemu_get_be32(f);
73 qemu_get_buffer(f, s->config, 256);
74 pci_update_mappings(s);
78 /* -1 for devfn means auto assign */
79 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
80 int instance_size, int devfn,
81 PCIConfigReadFunc *config_read,
82 PCIConfigWriteFunc *config_write)
86 if (pci_irq_index >= PCI_DEVICES_MAX)
90 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
91 if (!bus->devices[devfn])
97 pci_dev = qemu_mallocz(instance_size);
101 pci_dev->devfn = devfn;
102 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
105 config_read = pci_default_read_config;
107 config_write = pci_default_write_config;
108 pci_dev->config_read = config_read;
109 pci_dev->config_write = config_write;
110 pci_dev->irq_index = pci_irq_index++;
111 bus->devices[devfn] = pci_dev;
115 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
116 uint32_t size, int type,
117 PCIMapIORegionFunc *map_func)
122 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
124 r = &pci_dev->io_regions[region_num];
128 r->map_func = map_func;
129 if (region_num == PCI_ROM_SLOT) {
132 addr = 0x10 + region_num * 4;
134 *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
137 target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
139 return addr + pci_mem_base;
142 static void pci_update_mappings(PCIDevice *d)
146 uint32_t last_addr, new_addr, config_ofs;
148 cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
149 for(i = 0; i < PCI_NUM_REGIONS; i++) {
150 r = &d->io_regions[i];
151 if (i == PCI_ROM_SLOT) {
154 config_ofs = 0x10 + i * 4;
157 if (r->type & PCI_ADDRESS_SPACE_IO) {
158 if (cmd & PCI_COMMAND_IO) {
159 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
161 new_addr = new_addr & ~(r->size - 1);
162 last_addr = new_addr + r->size - 1;
163 /* NOTE: we have only 64K ioports on PC */
164 if (last_addr <= new_addr || new_addr == 0 ||
165 last_addr >= 0x10000) {
172 if (cmd & PCI_COMMAND_MEMORY) {
173 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
175 /* the ROM slot has a specific enable bit */
176 if (i == PCI_ROM_SLOT && !(new_addr & 1))
178 new_addr = new_addr & ~(r->size - 1);
179 last_addr = new_addr + r->size - 1;
180 /* NOTE: we do not support wrapping */
181 /* XXX: as we cannot support really dynamic
182 mappings, we handle specific values as invalid
184 if (last_addr <= new_addr || new_addr == 0 ||
193 /* now do the real mapping */
194 if (new_addr != r->addr) {
196 if (r->type & PCI_ADDRESS_SPACE_IO) {
198 /* NOTE: specific hack for IDE in PC case:
199 only one byte must be mapped. */
200 class = d->config[0x0a] | (d->config[0x0b] << 8);
201 if (class == 0x0101 && r->size == 4) {
202 isa_unassign_ioport(r->addr + 2, 1);
204 isa_unassign_ioport(r->addr, r->size);
207 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
214 r->map_func(d, i, r->addr, r->size, r->type);
221 uint32_t pci_default_read_config(PCIDevice *d,
222 uint32_t address, int len)
227 val = d->config[address];
230 val = le16_to_cpu(*(uint16_t *)(d->config + address));
234 val = le32_to_cpu(*(uint32_t *)(d->config + address));
240 void pci_default_write_config(PCIDevice *d,
241 uint32_t address, uint32_t val, int len)
246 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
247 (address >= 0x30 && address < 0x34))) {
251 if ( address >= 0x30 ) {
254 reg = (address - 0x10) >> 2;
256 r = &d->io_regions[reg];
259 /* compute the stored value */
260 if (reg == PCI_ROM_SLOT) {
261 /* keep ROM enable bit */
262 val &= (~(r->size - 1)) | 1;
264 val &= ~(r->size - 1);
267 *(uint32_t *)(d->config + address) = cpu_to_le32(val);
268 pci_update_mappings(d);
272 /* not efficient, but simple */
274 for(i = 0; i < len; i++) {
275 /* default read/write accesses */
276 switch(d->config[0x0e]) {
289 case 0x10 ... 0x27: /* base */
290 case 0x30 ... 0x33: /* rom */
311 case 0x38 ... 0x3b: /* rom */
322 d->config[addr] = val;
329 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
330 /* if the command register is modified, we must modify the mappings */
331 pci_update_mappings(d);
335 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
339 int config_addr, bus_num;
341 #if defined(DEBUG_PCI) && 0
342 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
345 bus_num = (addr >> 16) & 0xff;
348 pci_dev = s->devices[(addr >> 8) & 0xff];
351 config_addr = addr & 0xff;
352 #if defined(DEBUG_PCI)
353 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
354 pci_dev->name, config_addr, val, len);
356 pci_dev->config_write(pci_dev, config_addr, val, len);
359 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
363 int config_addr, bus_num;
366 bus_num = (addr >> 16) & 0xff;
369 pci_dev = s->devices[(addr >> 8) & 0xff];
386 config_addr = addr & 0xff;
387 val = pci_dev->config_read(pci_dev, config_addr, len);
388 #if defined(DEBUG_PCI)
389 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
390 pci_dev->name, config_addr, val, len);
393 #if defined(DEBUG_PCI) && 0
394 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
400 /***********************************************************/
401 /* generic PCI irq support */
403 /* 0 <= irq_num <= 3. level must be 0 or 1 */
404 void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
406 PCIBus *bus = pci_dev->bus;
407 bus->set_irq(pci_dev, bus->irq_opaque, irq_num, level);
410 /***********************************************************/
411 /* monitor info on PCI */
418 static pci_class_desc pci_class_descriptions[] =
420 { 0x0100, "SCSI controller"},
421 { 0x0101, "IDE controller"},
422 { 0x0200, "Ethernet controller"},
423 { 0x0300, "VGA controller"},
424 { 0x0600, "Host bridge"},
425 { 0x0601, "ISA bridge"},
426 { 0x0604, "PCI bridge"},
427 { 0x0c03, "USB controller"},
431 static void pci_info_device(PCIDevice *d)
435 pci_class_desc *desc;
437 term_printf(" Bus %2d, device %3d, function %d:\n",
438 d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
439 class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
441 desc = pci_class_descriptions;
442 while (desc->desc && class != desc->class)
445 term_printf("%s", desc->desc);
447 term_printf("Class %04x", class);
449 term_printf(": PCI device %04x:%04x\n",
450 le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
451 le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
453 if (d->config[PCI_INTERRUPT_PIN] != 0) {
454 term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
456 for(i = 0;i < PCI_NUM_REGIONS; i++) {
457 r = &d->io_regions[i];
459 term_printf(" BAR%d: ", i);
460 if (r->type & PCI_ADDRESS_SPACE_IO) {
461 term_printf("I/O at 0x%04x [0x%04x].\n",
462 r->addr, r->addr + r->size - 1);
464 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
465 r->addr, r->addr + r->size - 1);
471 void pci_for_each_device(void (*fn)(PCIDevice *d))
473 PCIBus *bus = first_bus;
478 for(devfn = 0; devfn < 256; devfn++) {
479 d = bus->devices[devfn];
488 pci_for_each_device(pci_info_device);
491 /* Initialize a PCI NIC. */
492 void pci_nic_init(PCIBus *bus, NICInfo *nd)
494 if (strcmp(nd->model, "ne2k_pci") == 0) {
495 pci_ne2000_init(bus, nd);
496 } else if (strcmp(nd->model, "rtl8139") == 0) {
497 pci_rtl8139_init(bus, nd);
498 } else if (strcmp(nd->model, "pcnet") == 0) {
499 pci_pcnet_init(bus, nd);
501 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);