4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "virtio-net.h"
35 pci_set_irq_fn set_irq;
36 pci_map_irq_fn map_irq;
37 uint32_t config_reg; /* XXX: suppress */
39 SetIRQFunc *low_set_irq;
41 PCIDevice *devices[256];
42 PCIDevice *parent_dev;
44 /* The bus IRQ state is the logical OR of the connected devices.
45 Keep a count of the number of devices with raised IRQs. */
50 static void pci_update_mappings(PCIDevice *d);
51 static void pci_set_irq(void *opaque, int irq_num, int level);
53 target_phys_addr_t pci_mem_base;
54 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
55 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
56 static int pci_irq_index;
57 static PCIBus *first_bus;
59 static void pcibus_save(QEMUFile *f, void *opaque)
61 PCIBus *bus = (PCIBus *)opaque;
64 qemu_put_be32(f, bus->nirq);
65 for (i = 0; i < bus->nirq; i++)
66 qemu_put_be32(f, bus->irq_count[i]);
69 static int pcibus_load(QEMUFile *f, void *opaque, int version_id)
71 PCIBus *bus = (PCIBus *)opaque;
77 nirq = qemu_get_be32(f);
78 if (bus->nirq != nirq) {
79 fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
84 for (i = 0; i < nirq; i++)
85 bus->irq_count[i] = qemu_get_be32(f);
90 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
91 qemu_irq *pic, int devfn_min, int nirq)
96 bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
97 bus->set_irq = set_irq;
98 bus->map_irq = map_irq;
99 bus->irq_opaque = pic;
100 bus->devfn_min = devfn_min;
103 register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
107 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
110 bus = qemu_mallocz(sizeof(PCIBus));
111 bus->map_irq = map_irq;
112 bus->parent_dev = dev;
113 bus->next = dev->bus->next;
114 dev->bus->next = bus;
118 int pci_bus_num(PCIBus *s)
123 void pci_device_save(PCIDevice *s, QEMUFile *f)
127 qemu_put_be32(f, 2); /* PCI device version */
128 qemu_put_buffer(f, s->config, 256);
129 for (i = 0; i < 4; i++)
130 qemu_put_be32(f, s->irq_state[i]);
133 int pci_device_load(PCIDevice *s, QEMUFile *f)
138 version_id = qemu_get_be32(f);
141 qemu_get_buffer(f, s->config, 256);
142 pci_update_mappings(s);
145 for (i = 0; i < 4; i ++)
146 s->irq_state[i] = qemu_get_be32(f);
151 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
155 id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
156 id[0] = cpu_to_le16(pci_default_sub_vendor_id);
157 id[1] = cpu_to_le16(pci_default_sub_device_id);
161 /* -1 for devfn means auto assign */
162 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
163 int instance_size, int devfn,
164 PCIConfigReadFunc *config_read,
165 PCIConfigWriteFunc *config_write)
169 if (pci_irq_index >= PCI_DEVICES_MAX)
173 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
174 if (!bus->devices[devfn])
180 pci_dev = qemu_mallocz(instance_size);
184 pci_dev->devfn = devfn;
185 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
186 memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
187 pci_set_default_subsystem_id(pci_dev);
190 config_read = pci_default_read_config;
192 config_write = pci_default_write_config;
193 pci_dev->config_read = config_read;
194 pci_dev->config_write = config_write;
195 pci_dev->irq_index = pci_irq_index++;
196 bus->devices[devfn] = pci_dev;
197 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
201 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
202 uint32_t size, int type,
203 PCIMapIORegionFunc *map_func)
208 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
210 r = &pci_dev->io_regions[region_num];
214 r->map_func = map_func;
215 if (region_num == PCI_ROM_SLOT) {
218 addr = 0x10 + region_num * 4;
220 *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
223 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
225 return addr + pci_mem_base;
228 static void pci_update_mappings(PCIDevice *d)
232 uint32_t last_addr, new_addr, config_ofs;
234 cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
235 for(i = 0; i < PCI_NUM_REGIONS; i++) {
236 r = &d->io_regions[i];
237 if (i == PCI_ROM_SLOT) {
240 config_ofs = 0x10 + i * 4;
243 if (r->type & PCI_ADDRESS_SPACE_IO) {
244 if (cmd & PCI_COMMAND_IO) {
245 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
247 new_addr = new_addr & ~(r->size - 1);
248 last_addr = new_addr + r->size - 1;
249 /* NOTE: we have only 64K ioports on PC */
250 if (last_addr <= new_addr || new_addr == 0 ||
251 last_addr >= 0x10000) {
258 if (cmd & PCI_COMMAND_MEMORY) {
259 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
261 /* the ROM slot has a specific enable bit */
262 if (i == PCI_ROM_SLOT && !(new_addr & 1))
264 new_addr = new_addr & ~(r->size - 1);
265 last_addr = new_addr + r->size - 1;
266 /* NOTE: we do not support wrapping */
267 /* XXX: as we cannot support really dynamic
268 mappings, we handle specific values as invalid
270 if (last_addr <= new_addr || new_addr == 0 ||
279 /* now do the real mapping */
280 if (new_addr != r->addr) {
282 if (r->type & PCI_ADDRESS_SPACE_IO) {
284 /* NOTE: specific hack for IDE in PC case:
285 only one byte must be mapped. */
286 class = d->config[0x0a] | (d->config[0x0b] << 8);
287 if (class == 0x0101 && r->size == 4) {
288 isa_unassign_ioport(r->addr + 2, 1);
290 isa_unassign_ioport(r->addr, r->size);
293 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
296 qemu_unregister_coalesced_mmio(r->addr, r->size);
301 r->map_func(d, i, r->addr, r->size, r->type);
308 uint32_t pci_default_read_config(PCIDevice *d,
309 uint32_t address, int len)
316 if (address <= 0xfc) {
317 val = le32_to_cpu(*(uint32_t *)(d->config + address));
322 if (address <= 0xfe) {
323 val = le16_to_cpu(*(uint16_t *)(d->config + address));
328 val = d->config[address];
334 void pci_default_write_config(PCIDevice *d,
335 uint32_t address, uint32_t val, int len)
340 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
341 (address >= 0x30 && address < 0x34))) {
345 if ( address >= 0x30 ) {
348 reg = (address - 0x10) >> 2;
350 r = &d->io_regions[reg];
353 /* compute the stored value */
354 if (reg == PCI_ROM_SLOT) {
355 /* keep ROM enable bit */
356 val &= (~(r->size - 1)) | 1;
358 val &= ~(r->size - 1);
361 *(uint32_t *)(d->config + address) = cpu_to_le32(val);
362 pci_update_mappings(d);
366 /* not efficient, but simple */
368 for(i = 0; i < len; i++) {
369 /* default read/write accesses */
370 switch(d->config[0x0e]) {
383 case 0x10 ... 0x27: /* base */
384 case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
385 case 0x30 ... 0x33: /* rom */
406 case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
407 case 0x38 ... 0x3b: /* rom */
418 /* Mask out writes to reserved bits in registers */
421 val &= ~PCI_COMMAND_RESERVED_MASK_HI;
424 val &= ~PCI_STATUS_RESERVED_MASK_LO;
427 val &= ~PCI_STATUS_RESERVED_MASK_HI;
430 d->config[addr] = val;
438 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
439 /* if the command register is modified, we must modify the mappings */
440 pci_update_mappings(d);
444 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
448 int config_addr, bus_num;
450 #if defined(DEBUG_PCI) && 0
451 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
454 bus_num = (addr >> 16) & 0xff;
455 while (s && s->bus_num != bus_num)
459 pci_dev = s->devices[(addr >> 8) & 0xff];
462 config_addr = addr & 0xff;
463 #if defined(DEBUG_PCI)
464 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
465 pci_dev->name, config_addr, val, len);
467 pci_dev->config_write(pci_dev, config_addr, val, len);
470 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
474 int config_addr, bus_num;
477 bus_num = (addr >> 16) & 0xff;
478 while (s && s->bus_num != bus_num)
482 pci_dev = s->devices[(addr >> 8) & 0xff];
499 config_addr = addr & 0xff;
500 val = pci_dev->config_read(pci_dev, config_addr, len);
501 #if defined(DEBUG_PCI)
502 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
503 pci_dev->name, config_addr, val, len);
506 #if defined(DEBUG_PCI) && 0
507 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
513 /***********************************************************/
514 /* generic PCI irq support */
516 /* 0 <= irq_num <= 3. level must be 0 or 1 */
517 static void pci_set_irq(void *opaque, int irq_num, int level)
519 PCIDevice *pci_dev = (PCIDevice *)opaque;
523 change = level - pci_dev->irq_state[irq_num];
527 pci_dev->irq_state[irq_num] = level;
530 irq_num = bus->map_irq(pci_dev, irq_num);
533 pci_dev = bus->parent_dev;
535 bus->irq_count[irq_num] += change;
536 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
539 /***********************************************************/
540 /* monitor info on PCI */
547 static const pci_class_desc pci_class_descriptions[] =
549 { 0x0100, "SCSI controller"},
550 { 0x0101, "IDE controller"},
551 { 0x0102, "Floppy controller"},
552 { 0x0103, "IPI controller"},
553 { 0x0104, "RAID controller"},
554 { 0x0106, "SATA controller"},
555 { 0x0107, "SAS controller"},
556 { 0x0180, "Storage controller"},
557 { 0x0200, "Ethernet controller"},
558 { 0x0201, "Token Ring controller"},
559 { 0x0202, "FDDI controller"},
560 { 0x0203, "ATM controller"},
561 { 0x0280, "Network controller"},
562 { 0x0300, "VGA controller"},
563 { 0x0301, "XGA controller"},
564 { 0x0302, "3D controller"},
565 { 0x0380, "Display controller"},
566 { 0x0400, "Video controller"},
567 { 0x0401, "Audio controller"},
569 { 0x0480, "Multimedia controller"},
570 { 0x0500, "RAM controller"},
571 { 0x0501, "Flash controller"},
572 { 0x0580, "Memory controller"},
573 { 0x0600, "Host bridge"},
574 { 0x0601, "ISA bridge"},
575 { 0x0602, "EISA bridge"},
576 { 0x0603, "MC bridge"},
577 { 0x0604, "PCI bridge"},
578 { 0x0605, "PCMCIA bridge"},
579 { 0x0606, "NUBUS bridge"},
580 { 0x0607, "CARDBUS bridge"},
581 { 0x0608, "RACEWAY bridge"},
583 { 0x0c03, "USB controller"},
587 static void pci_info_device(PCIDevice *d)
591 const pci_class_desc *desc;
593 term_printf(" Bus %2d, device %3d, function %d:\n",
594 d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
595 class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
597 desc = pci_class_descriptions;
598 while (desc->desc && class != desc->class)
601 term_printf("%s", desc->desc);
603 term_printf("Class %04x", class);
605 term_printf(": PCI device %04x:%04x\n",
606 le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
607 le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
609 if (d->config[PCI_INTERRUPT_PIN] != 0) {
610 term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
612 if (class == 0x0604) {
613 term_printf(" BUS %d.\n", d->config[0x19]);
615 for(i = 0;i < PCI_NUM_REGIONS; i++) {
616 r = &d->io_regions[i];
618 term_printf(" BAR%d: ", i);
619 if (r->type & PCI_ADDRESS_SPACE_IO) {
620 term_printf("I/O at 0x%04x [0x%04x].\n",
621 r->addr, r->addr + r->size - 1);
623 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
624 r->addr, r->addr + r->size - 1);
628 if (class == 0x0604 && d->config[0x19] != 0) {
629 pci_for_each_device(d->config[0x19], pci_info_device);
633 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
635 PCIBus *bus = first_bus;
639 while (bus && bus->bus_num != bus_num)
642 for(devfn = 0; devfn < 256; devfn++) {
643 d = bus->devices[devfn];
652 pci_for_each_device(0, pci_info_device);
655 static const char * const pci_nic_models[] = {
667 typedef void (*PCINICInitFn)(PCIBus *, NICInfo *, int);
669 static PCINICInitFn pci_nic_init_fns[] = {
681 /* Initialize a PCI NIC. */
682 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
683 const char *default_model)
687 qemu_check_nic_model_list(nd, pci_nic_models, default_model);
689 for (i = 0; pci_nic_models[i]; i++)
690 if (strcmp(nd->model, pci_nic_models[i]) == 0)
691 pci_nic_init_fns[i](bus, nd, devfn);
699 static void pci_bridge_write_config(PCIDevice *d,
700 uint32_t address, uint32_t val, int len)
702 PCIBridge *s = (PCIBridge *)d;
704 if (address == 0x19 || (address == 0x18 && len > 1)) {
706 s->bus->bus_num = val & 0xff;
708 s->bus->bus_num = (val >> 8) & 0xff;
709 #if defined(DEBUG_PCI)
710 printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
713 pci_default_write_config(d, address, val, len);
716 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
717 pci_map_irq_fn map_irq, const char *name)
720 s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
721 devfn, NULL, pci_bridge_write_config);
723 pci_config_set_vendor_id(s->dev.config, vid);
724 pci_config_set_device_id(s->dev.config, did);
726 s->dev.config[0x04] = 0x06; // command = bus master, pci mem
727 s->dev.config[0x05] = 0x00;
728 s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
729 s->dev.config[0x07] = 0x00; // status = fast devsel
730 s->dev.config[0x08] = 0x00; // revision
731 s->dev.config[0x09] = 0x00; // programming i/f
732 s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge
733 s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge
734 s->dev.config[0x0D] = 0x10; // latency_timer
735 s->dev.config[0x0E] = 0x81; // header_type
736 s->dev.config[0x1E] = 0xa0; // secondary status
738 s->bus = pci_register_secondary_bus(&s->dev, map_irq);