4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
36 pci_set_irq_fn set_irq;
37 pci_map_irq_fn map_irq;
38 uint32_t config_reg; /* XXX: suppress */
40 SetIRQFunc *low_set_irq;
42 PCIDevice *devices[256];
43 PCIDevice *parent_dev;
45 /* The bus IRQ state is the logical OR of the connected devices.
46 Keep a count of the number of devices with raised IRQs. */
51 static void pci_update_mappings(PCIDevice *d);
52 static void pci_set_irq(void *opaque, int irq_num, int level);
54 target_phys_addr_t pci_mem_base;
55 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
56 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
57 static PCIBus *first_bus;
59 static void pcibus_save(QEMUFile *f, void *opaque)
61 PCIBus *bus = (PCIBus *)opaque;
64 qemu_put_be32(f, bus->nirq);
65 for (i = 0; i < bus->nirq; i++)
66 qemu_put_be32(f, bus->irq_count[i]);
69 static int pcibus_load(QEMUFile *f, void *opaque, int version_id)
71 PCIBus *bus = (PCIBus *)opaque;
77 nirq = qemu_get_be32(f);
78 if (bus->nirq != nirq) {
79 fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
84 for (i = 0; i < nirq; i++)
85 bus->irq_count[i] = qemu_get_be32(f);
90 static void pci_bus_reset(void *opaque)
92 PCIBus *bus = (PCIBus *)opaque;
95 for (i = 0; i < bus->nirq; i++) {
96 bus->irq_count[i] = 0;
98 for (i = 0; i < 256; i++) {
100 memset(bus->devices[i]->irq_state, 0,
101 sizeof(bus->devices[i]->irq_state));
105 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
106 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
107 qemu_irq *pic, int devfn_min, int nirq)
112 bus = FROM_QBUS(PCIBus, qbus_create(BUS_TYPE_PCI,
113 sizeof(PCIBus) + (nirq * sizeof(int)),
115 bus->set_irq = set_irq;
116 bus->map_irq = map_irq;
117 bus->irq_opaque = pic;
118 bus->devfn_min = devfn_min;
120 bus->next = first_bus;
122 register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
123 qemu_register_reset(pci_bus_reset, 0, bus);
127 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
130 bus = qemu_mallocz(sizeof(PCIBus));
131 bus->map_irq = map_irq;
132 bus->parent_dev = dev;
133 bus->next = dev->bus->next;
134 dev->bus->next = bus;
138 int pci_bus_num(PCIBus *s)
143 void pci_device_save(PCIDevice *s, QEMUFile *f)
147 qemu_put_be32(f, 2); /* PCI device version */
148 qemu_put_buffer(f, s->config, 256);
149 for (i = 0; i < 4; i++)
150 qemu_put_be32(f, s->irq_state[i]);
153 int pci_device_load(PCIDevice *s, QEMUFile *f)
158 version_id = qemu_get_be32(f);
161 qemu_get_buffer(f, s->config, 256);
162 pci_update_mappings(s);
165 for (i = 0; i < 4; i ++)
166 s->irq_state[i] = qemu_get_be32(f);
171 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
175 id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
176 id[0] = cpu_to_le16(pci_default_sub_vendor_id);
177 id[1] = cpu_to_le16(pci_default_sub_device_id);
182 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
184 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
189 unsigned long dom = 0, bus = 0;
193 val = strtoul(p, &e, 16);
199 val = strtoul(p, &e, 16);
206 val = strtoul(p, &e, 16);
212 if (dom > 0xffff || bus > 0xff || val > 0x1f)
220 /* Note: QEMU doesn't implement domains other than 0 */
221 if (dom != 0 || pci_find_bus(bus) == NULL)
230 int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
234 if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
237 return pci_parse_devaddr(devaddr, domp, busp, slotp);
240 int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
244 if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
247 if (!strcmp(devaddr, "auto")) {
250 /* want to support dom/bus auto-assign at some point */
254 return pci_parse_devaddr(devaddr, domp, busp, slotp);
257 static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
264 return pci_find_bus(0);
267 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
272 return pci_find_bus(bus);
275 /* -1 for devfn means auto assign */
276 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
277 const char *name, int devfn,
278 PCIConfigReadFunc *config_read,
279 PCIConfigWriteFunc *config_write)
282 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
283 if (!bus->devices[devfn])
288 } else if (bus->devices[devfn]) {
292 pci_dev->devfn = devfn;
293 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
294 memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
295 pci_set_default_subsystem_id(pci_dev);
298 config_read = pci_default_read_config;
300 config_write = pci_default_write_config;
301 pci_dev->config_read = config_read;
302 pci_dev->config_write = config_write;
303 bus->devices[devfn] = pci_dev;
304 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
308 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
309 int instance_size, int devfn,
310 PCIConfigReadFunc *config_read,
311 PCIConfigWriteFunc *config_write)
315 pci_dev = qemu_mallocz(instance_size);
316 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
317 config_read, config_write);
320 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
322 return addr + pci_mem_base;
325 static void pci_unregister_io_regions(PCIDevice *pci_dev)
330 for(i = 0; i < PCI_NUM_REGIONS; i++) {
331 r = &pci_dev->io_regions[i];
332 if (!r->size || r->addr == -1)
334 if (r->type == PCI_ADDRESS_SPACE_IO) {
335 isa_unassign_ioport(r->addr, r->size);
337 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
344 int pci_unregister_device(PCIDevice *pci_dev)
348 if (pci_dev->unregister)
349 ret = pci_dev->unregister(pci_dev);
353 pci_unregister_io_regions(pci_dev);
355 qemu_free_irqs(pci_dev->irq);
356 pci_dev->bus->devices[pci_dev->devfn] = NULL;
357 qdev_free(&pci_dev->qdev);
361 void pci_register_bar(PCIDevice *pci_dev, int region_num,
362 uint32_t size, int type,
363 PCIMapIORegionFunc *map_func)
368 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
371 if (size & (size-1)) {
372 fprintf(stderr, "ERROR: PCI region size must be pow2 "
373 "type=0x%x, size=0x%x\n", type, size);
377 r = &pci_dev->io_regions[region_num];
381 r->map_func = map_func;
382 if (region_num == PCI_ROM_SLOT) {
385 addr = 0x10 + region_num * 4;
387 *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
390 static void pci_update_mappings(PCIDevice *d)
394 uint32_t last_addr, new_addr, config_ofs;
396 cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
397 for(i = 0; i < PCI_NUM_REGIONS; i++) {
398 r = &d->io_regions[i];
399 if (i == PCI_ROM_SLOT) {
402 config_ofs = 0x10 + i * 4;
405 if (r->type & PCI_ADDRESS_SPACE_IO) {
406 if (cmd & PCI_COMMAND_IO) {
407 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
409 new_addr = new_addr & ~(r->size - 1);
410 last_addr = new_addr + r->size - 1;
411 /* NOTE: we have only 64K ioports on PC */
412 if (last_addr <= new_addr || new_addr == 0 ||
413 last_addr >= 0x10000) {
420 if (cmd & PCI_COMMAND_MEMORY) {
421 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
423 /* the ROM slot has a specific enable bit */
424 if (i == PCI_ROM_SLOT && !(new_addr & 1))
426 new_addr = new_addr & ~(r->size - 1);
427 last_addr = new_addr + r->size - 1;
428 /* NOTE: we do not support wrapping */
429 /* XXX: as we cannot support really dynamic
430 mappings, we handle specific values as invalid
432 if (last_addr <= new_addr || new_addr == 0 ||
441 /* now do the real mapping */
442 if (new_addr != r->addr) {
444 if (r->type & PCI_ADDRESS_SPACE_IO) {
446 /* NOTE: specific hack for IDE in PC case:
447 only one byte must be mapped. */
448 class = d->config[0x0a] | (d->config[0x0b] << 8);
449 if (class == 0x0101 && r->size == 4) {
450 isa_unassign_ioport(r->addr + 2, 1);
452 isa_unassign_ioport(r->addr, r->size);
455 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
458 qemu_unregister_coalesced_mmio(r->addr, r->size);
463 r->map_func(d, i, r->addr, r->size, r->type);
470 uint32_t pci_default_read_config(PCIDevice *d,
471 uint32_t address, int len)
478 if (address <= 0xfc) {
479 val = le32_to_cpu(*(uint32_t *)(d->config + address));
484 if (address <= 0xfe) {
485 val = le16_to_cpu(*(uint16_t *)(d->config + address));
490 val = d->config[address];
496 void pci_default_write_config(PCIDevice *d,
497 uint32_t address, uint32_t val, int len)
502 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
503 (address >= 0x30 && address < 0x34))) {
507 if ( address >= 0x30 ) {
510 reg = (address - 0x10) >> 2;
512 r = &d->io_regions[reg];
515 /* compute the stored value */
516 if (reg == PCI_ROM_SLOT) {
517 /* keep ROM enable bit */
518 val &= (~(r->size - 1)) | 1;
520 val &= ~(r->size - 1);
523 *(uint32_t *)(d->config + address) = cpu_to_le32(val);
524 pci_update_mappings(d);
528 /* not efficient, but simple */
530 for(i = 0; i < len; i++) {
531 /* default read/write accesses */
532 switch(d->config[0x0e]) {
547 case 0x10 ... 0x27: /* base */
548 case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
549 case 0x30 ... 0x33: /* rom */
572 case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
573 case 0x38 ... 0x3b: /* rom */
584 /* Mask out writes to reserved bits in registers */
587 val &= ~PCI_COMMAND_RESERVED_MASK_HI;
590 val &= ~PCI_STATUS_RESERVED_MASK_LO;
593 val &= ~PCI_STATUS_RESERVED_MASK_HI;
596 d->config[addr] = val;
604 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
605 /* if the command register is modified, we must modify the mappings */
606 pci_update_mappings(d);
610 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
614 int config_addr, bus_num;
616 #if defined(DEBUG_PCI) && 0
617 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
620 bus_num = (addr >> 16) & 0xff;
621 while (s && s->bus_num != bus_num)
625 pci_dev = s->devices[(addr >> 8) & 0xff];
628 config_addr = addr & 0xff;
629 #if defined(DEBUG_PCI)
630 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
631 pci_dev->name, config_addr, val, len);
633 pci_dev->config_write(pci_dev, config_addr, val, len);
636 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
640 int config_addr, bus_num;
643 bus_num = (addr >> 16) & 0xff;
644 while (s && s->bus_num != bus_num)
648 pci_dev = s->devices[(addr >> 8) & 0xff];
665 config_addr = addr & 0xff;
666 val = pci_dev->config_read(pci_dev, config_addr, len);
667 #if defined(DEBUG_PCI)
668 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
669 pci_dev->name, config_addr, val, len);
672 #if defined(DEBUG_PCI) && 0
673 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
679 /***********************************************************/
680 /* generic PCI irq support */
682 /* 0 <= irq_num <= 3. level must be 0 or 1 */
683 static void pci_set_irq(void *opaque, int irq_num, int level)
685 PCIDevice *pci_dev = (PCIDevice *)opaque;
689 change = level - pci_dev->irq_state[irq_num];
693 pci_dev->irq_state[irq_num] = level;
696 irq_num = bus->map_irq(pci_dev, irq_num);
699 pci_dev = bus->parent_dev;
701 bus->irq_count[irq_num] += change;
702 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
705 /***********************************************************/
706 /* monitor info on PCI */
713 static const pci_class_desc pci_class_descriptions[] =
715 { 0x0100, "SCSI controller"},
716 { 0x0101, "IDE controller"},
717 { 0x0102, "Floppy controller"},
718 { 0x0103, "IPI controller"},
719 { 0x0104, "RAID controller"},
720 { 0x0106, "SATA controller"},
721 { 0x0107, "SAS controller"},
722 { 0x0180, "Storage controller"},
723 { 0x0200, "Ethernet controller"},
724 { 0x0201, "Token Ring controller"},
725 { 0x0202, "FDDI controller"},
726 { 0x0203, "ATM controller"},
727 { 0x0280, "Network controller"},
728 { 0x0300, "VGA controller"},
729 { 0x0301, "XGA controller"},
730 { 0x0302, "3D controller"},
731 { 0x0380, "Display controller"},
732 { 0x0400, "Video controller"},
733 { 0x0401, "Audio controller"},
735 { 0x0480, "Multimedia controller"},
736 { 0x0500, "RAM controller"},
737 { 0x0501, "Flash controller"},
738 { 0x0580, "Memory controller"},
739 { 0x0600, "Host bridge"},
740 { 0x0601, "ISA bridge"},
741 { 0x0602, "EISA bridge"},
742 { 0x0603, "MC bridge"},
743 { 0x0604, "PCI bridge"},
744 { 0x0605, "PCMCIA bridge"},
745 { 0x0606, "NUBUS bridge"},
746 { 0x0607, "CARDBUS bridge"},
747 { 0x0608, "RACEWAY bridge"},
749 { 0x0c03, "USB controller"},
753 static void pci_info_device(PCIDevice *d)
755 Monitor *mon = cur_mon;
758 const pci_class_desc *desc;
760 monitor_printf(mon, " Bus %2d, device %3d, function %d:\n",
761 d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
762 class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
763 monitor_printf(mon, " ");
764 desc = pci_class_descriptions;
765 while (desc->desc && class != desc->class)
768 monitor_printf(mon, "%s", desc->desc);
770 monitor_printf(mon, "Class %04x", class);
772 monitor_printf(mon, ": PCI device %04x:%04x\n",
773 le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
774 le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
776 if (d->config[PCI_INTERRUPT_PIN] != 0) {
777 monitor_printf(mon, " IRQ %d.\n",
778 d->config[PCI_INTERRUPT_LINE]);
780 if (class == 0x0604) {
781 monitor_printf(mon, " BUS %d.\n", d->config[0x19]);
783 for(i = 0;i < PCI_NUM_REGIONS; i++) {
784 r = &d->io_regions[i];
786 monitor_printf(mon, " BAR%d: ", i);
787 if (r->type & PCI_ADDRESS_SPACE_IO) {
788 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
789 r->addr, r->addr + r->size - 1);
791 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
792 r->addr, r->addr + r->size - 1);
796 if (class == 0x0604 && d->config[0x19] != 0) {
797 pci_for_each_device(d->config[0x19], pci_info_device);
801 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
803 PCIBus *bus = first_bus;
807 while (bus && bus->bus_num != bus_num)
810 for(devfn = 0; devfn < 256; devfn++) {
811 d = bus->devices[devfn];
818 void pci_info(Monitor *mon)
820 pci_for_each_device(0, pci_info_device);
823 static PCIDevice *pci_create(const char *name, const char *devaddr)
829 bus = pci_get_bus_devfn(&devfn, devaddr);
831 fprintf(stderr, "Invalid PCI device address %s for device %s\n",
836 dev = qdev_create(&bus->qbus, name);
837 qdev_set_prop_int(dev, "devfn", devfn);
838 return (PCIDevice *)dev;
841 static const char * const pci_nic_models[] = {
853 static const char * const pci_nic_names[] = {
865 /* Initialize a PCI NIC. */
866 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
867 const char *default_devaddr)
869 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
874 qemu_check_nic_model_list(nd, pci_nic_models, default_model);
876 for (i = 0; pci_nic_models[i]; i++) {
877 if (strcmp(nd->model, pci_nic_models[i]) == 0) {
878 pci_dev = pci_create(pci_nic_names[i], devaddr);
879 dev = &pci_dev->qdev;
880 qdev_set_netdev(dev, nd);
895 static void pci_bridge_write_config(PCIDevice *d,
896 uint32_t address, uint32_t val, int len)
898 PCIBridge *s = (PCIBridge *)d;
900 if (address == 0x19 || (address == 0x18 && len > 1)) {
902 s->bus->bus_num = val & 0xff;
904 s->bus->bus_num = (val >> 8) & 0xff;
905 #if defined(DEBUG_PCI)
906 printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
909 pci_default_write_config(d, address, val, len);
912 PCIBus *pci_find_bus(int bus_num)
914 PCIBus *bus = first_bus;
916 while (bus && bus->bus_num != bus_num)
922 PCIDevice *pci_find_device(int bus_num, int slot, int function)
924 PCIBus *bus = pci_find_bus(bus_num);
929 return bus->devices[PCI_DEVFN(slot, function)];
932 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
933 pci_map_irq_fn map_irq, const char *name)
936 s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
937 devfn, NULL, pci_bridge_write_config);
939 pci_config_set_vendor_id(s->dev.config, vid);
940 pci_config_set_device_id(s->dev.config, did);
942 s->dev.config[0x04] = 0x06; // command = bus master, pci mem
943 s->dev.config[0x05] = 0x00;
944 s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
945 s->dev.config[0x07] = 0x00; // status = fast devsel
946 s->dev.config[0x08] = 0x00; // revision
947 s->dev.config[0x09] = 0x00; // programming i/f
948 pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
949 s->dev.config[0x0D] = 0x10; // latency_timer
950 s->dev.config[PCI_HEADER_TYPE] =
951 PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
952 s->dev.config[0x1E] = 0xa0; // secondary status
954 s->bus = pci_register_secondary_bus(&s->dev, map_irq);
960 pci_qdev_initfn init;
963 static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
965 PCIDevice *pci_dev = (PCIDevice *)qdev;
966 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
970 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
971 devfn = qdev_get_prop_int(qdev, "devfn", -1);
972 pci_dev = do_pci_register_device(pci_dev, bus, "FIXME", devfn,
973 NULL, NULL);//FIXME:config_read, config_write);
978 void pci_qdev_register(const char *name, int size, pci_qdev_initfn init)
982 info = qemu_mallocz(sizeof(*info));
983 info->qdev.name = qemu_strdup(name);
984 info->qdev.size = size;
986 info->qdev.init = pci_qdev_init;
987 info->qdev.bus_type = BUS_TYPE_PCI;
989 qdev_register(&info->qdev);
992 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
996 dev = qdev_create(&bus->qbus, name);
997 qdev_set_prop_int(dev, "devfn", devfn);
1000 return (PCIDevice *)dev;