4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #define PCI_VENDOR_ID 0x00 /* 16 bits */
29 #define PCI_DEVICE_ID 0x02 /* 16 bits */
30 #define PCI_COMMAND 0x04 /* 16 bits */
31 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
32 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
33 #define PCI_CLASS_DEVICE 0x0a /* Device class */
34 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
35 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
36 #define PCI_MIN_GNT 0x3e /* 8 bits */
37 #define PCI_MAX_LAT 0x3f /* 8 bits */
39 /* just used for simpler irq handling. */
40 #define PCI_DEVICES_MAX 64
41 #define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32)
43 typedef struct PCIBridge {
45 PCIDevice **pci_bus[256];
48 static PCIBridge pci_bridge;
49 target_phys_addr_t pci_mem_base;
50 static int pci_irq_index;
51 static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];
53 /* -1 for devfn means auto assign */
54 PCIDevice *pci_register_device(const char *name, int instance_size,
55 int bus_num, int devfn,
56 PCIConfigReadFunc *config_read,
57 PCIConfigWriteFunc *config_write)
59 PCIBridge *s = &pci_bridge;
60 PCIDevice *pci_dev, **bus;
62 if (pci_irq_index >= PCI_DEVICES_MAX)
65 if (!s->pci_bus[bus_num]) {
66 s->pci_bus[bus_num] = qemu_mallocz(256 * sizeof(PCIDevice *));
67 if (!s->pci_bus[bus_num])
70 bus = s->pci_bus[bus_num];
72 for(devfn = 0 ; devfn < 256; devfn += 8) {
79 pci_dev = qemu_mallocz(instance_size);
82 pci_dev->bus_num = bus_num;
83 pci_dev->devfn = devfn;
84 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
87 config_read = pci_default_read_config;
89 config_write = pci_default_write_config;
90 pci_dev->config_read = config_read;
91 pci_dev->config_write = config_write;
92 pci_dev->irq_index = pci_irq_index++;
97 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
98 uint32_t size, int type,
99 PCIMapIORegionFunc *map_func)
103 if ((unsigned int)region_num >= 6)
105 r = &pci_dev->io_regions[region_num];
109 r->map_func = map_func;
112 static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val)
114 PCIBridge *s = opaque;
118 static uint32_t pci_addr_readl(void* opaque, uint32_t addr)
120 PCIBridge *s = opaque;
121 return s->config_reg;
124 static void pci_update_mappings(PCIDevice *d)
128 uint32_t last_addr, new_addr;
130 cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
131 for(i = 0; i < 6; i++) {
132 r = &d->io_regions[i];
134 if (r->type & PCI_ADDRESS_SPACE_IO) {
135 if (cmd & PCI_COMMAND_IO) {
136 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
138 new_addr = new_addr & ~(r->size - 1);
139 last_addr = new_addr + r->size - 1;
140 /* NOTE: we have only 64K ioports on PC */
141 if (last_addr <= new_addr || new_addr == 0 ||
142 last_addr >= 0x10000) {
149 if (cmd & PCI_COMMAND_MEMORY) {
150 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
152 new_addr = new_addr & ~(r->size - 1);
153 last_addr = new_addr + r->size - 1;
154 /* NOTE: we do not support wrapping */
155 /* XXX: as we cannot support really dynamic
156 mappings, we handle specific values as invalid
158 if (last_addr <= new_addr || new_addr == 0 ||
166 /* now do the real mapping */
167 if (new_addr != r->addr) {
169 if (r->type & PCI_ADDRESS_SPACE_IO) {
171 /* NOTE: specific hack for IDE in PC case:
172 only one byte must be mapped. */
173 class = d->config[0x0a] | (d->config[0x0b] << 8);
174 if (class == 0x0101 && r->size == 4) {
175 isa_unassign_ioport(r->addr + 2, 1);
177 isa_unassign_ioport(r->addr, r->size);
180 cpu_register_physical_memory(r->addr + pci_mem_base,
187 r->map_func(d, i, r->addr, r->size, r->type);
194 uint32_t pci_default_read_config(PCIDevice *d,
195 uint32_t address, int len)
200 val = d->config[address];
203 val = le16_to_cpu(*(uint16_t *)(d->config + address));
207 val = le32_to_cpu(*(uint32_t *)(d->config + address));
213 void pci_default_write_config(PCIDevice *d,
214 uint32_t address, uint32_t val, int len)
219 if (len == 4 && (address >= 0x10 && address < 0x10 + 4 * 6)) {
223 reg = (address - 0x10) >> 2;
224 r = &d->io_regions[reg];
227 /* compute the stored value */
228 val &= ~(r->size - 1);
230 *(uint32_t *)(d->config + 0x10 + reg * 4) = cpu_to_le32(val);
231 pci_update_mappings(d);
235 /* not efficient, but simple */
237 for(i = 0; i < len; i++) {
238 /* default read/write accesses */
257 d->config[addr] = val;
264 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
265 /* if the command register is modified, we must modify the mappings */
266 pci_update_mappings(d);
270 static void pci_data_write(void *opaque, uint32_t addr,
271 uint32_t val, int len)
273 PCIBridge *s = opaque;
274 PCIDevice **bus, *pci_dev;
277 #if defined(DEBUG_PCI) && 0
278 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
279 s->config_reg, val, len);
281 if (!(s->config_reg & (1 << 31))) {
284 if ((s->config_reg & 0x3) != 0) {
287 bus = s->pci_bus[(s->config_reg >> 16) & 0xff];
290 pci_dev = bus[(s->config_reg >> 8) & 0xff];
293 config_addr = (s->config_reg & 0xfc) | (addr & 3);
294 #if defined(DEBUG_PCI)
295 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
296 pci_dev->name, config_addr, val, len);
298 pci_dev->config_write(pci_dev, config_addr, val, len);
301 static uint32_t pci_data_read(void *opaque, uint32_t addr,
304 PCIBridge *s = opaque;
305 PCIDevice **bus, *pci_dev;
309 if (!(s->config_reg & (1 << 31)))
311 if ((s->config_reg & 0x3) != 0)
313 bus = s->pci_bus[(s->config_reg >> 16) & 0xff];
316 pci_dev = bus[(s->config_reg >> 8) & 0xff];
333 config_addr = (s->config_reg & 0xfc) | (addr & 3);
334 val = pci_dev->config_read(pci_dev, config_addr, len);
335 #if defined(DEBUG_PCI)
336 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
337 pci_dev->name, config_addr, val, len);
340 #if defined(DEBUG_PCI) && 0
341 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
342 s->config_reg, val, len);
347 static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val)
349 pci_data_write(opaque, addr, val, 1);
352 static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val)
354 pci_data_write(opaque, addr, val, 2);
357 static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val)
359 pci_data_write(opaque, addr, val, 4);
362 static uint32_t pci_data_readb(void* opaque, uint32_t addr)
364 return pci_data_read(opaque, addr, 1);
367 static uint32_t pci_data_readw(void* opaque, uint32_t addr)
369 return pci_data_read(opaque, addr, 2);
372 static uint32_t pci_data_readl(void* opaque, uint32_t addr)
374 return pci_data_read(opaque, addr, 4);
377 /* i440FX PCI bridge */
379 void i440fx_init(void)
381 PCIBridge *s = &pci_bridge;
384 register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);
385 register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);
387 register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
388 register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
389 register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
390 register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
391 register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
392 register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);
394 d = pci_register_device("i440FX", sizeof(PCIDevice), 0, 0,
397 d->config[0x00] = 0x86; // vendor_id
398 d->config[0x01] = 0x80;
399 d->config[0x02] = 0x37; // device_id
400 d->config[0x03] = 0x12;
401 d->config[0x08] = 0x02; // revision
402 d->config[0x0a] = 0x04; // class_sub = pci2pci
403 d->config[0x0b] = 0x06; // class_base = PCI_bridge
404 d->config[0x0c] = 0x01; // line_size in 32 bit words
405 d->config[0x0e] = 0x01; // header_type
408 /* PIIX3 PCI to ISA bridge */
410 typedef struct PIIX3State {
414 PIIX3State *piix3_state;
416 static void piix3_reset(PIIX3State *d)
418 uint8_t *pci_conf = d->dev.config;
420 pci_conf[0x04] = 0x07; // master, memory and I/O
421 pci_conf[0x05] = 0x00;
422 pci_conf[0x06] = 0x00;
423 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
424 pci_conf[0x4c] = 0x4d;
425 pci_conf[0x4e] = 0x03;
426 pci_conf[0x4f] = 0x00;
427 pci_conf[0x60] = 0x80;
428 pci_conf[0x69] = 0x02;
429 pci_conf[0x70] = 0x80;
430 pci_conf[0x76] = 0x0c;
431 pci_conf[0x77] = 0x0c;
432 pci_conf[0x78] = 0x02;
433 pci_conf[0x79] = 0x00;
434 pci_conf[0x80] = 0x00;
435 pci_conf[0x82] = 0x00;
436 pci_conf[0xa0] = 0x08;
437 pci_conf[0xa0] = 0x08;
438 pci_conf[0xa2] = 0x00;
439 pci_conf[0xa3] = 0x00;
440 pci_conf[0xa4] = 0x00;
441 pci_conf[0xa5] = 0x00;
442 pci_conf[0xa6] = 0x00;
443 pci_conf[0xa7] = 0x00;
444 pci_conf[0xa8] = 0x0f;
445 pci_conf[0xaa] = 0x00;
446 pci_conf[0xab] = 0x00;
447 pci_conf[0xac] = 0x00;
448 pci_conf[0xae] = 0x00;
451 void piix3_init(void)
456 d = (PIIX3State *)pci_register_device("PIIX3", sizeof(PIIX3State),
460 pci_conf = d->dev.config;
462 pci_conf[0x00] = 0x86; // Intel
463 pci_conf[0x01] = 0x80;
464 pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
465 pci_conf[0x03] = 0x70;
466 pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
467 pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
468 pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
473 /***********************************************************/
474 /* generic PCI irq support */
476 /* return the global irq number corresponding to a given device irq
477 pin. We could also use the bus number to have a more precise
479 static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
482 slot_addend = (pci_dev->devfn >> 3);
483 return (irq_num + slot_addend) & 3;
486 /* 0 <= irq_num <= 3. level must be 0 or 1 */
487 void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
489 int irq_index, shift, pic_irq, pic_level;
492 irq_num = pci_slot_get_pirq(pci_dev, irq_num);
493 irq_index = pci_dev->irq_index;
494 p = &pci_irq_levels[irq_num][irq_index >> 5];
495 shift = (irq_index & 0x1f);
496 *p = (*p & ~(1 << shift)) | (level << shift);
498 /* now we change the pic irq level according to the piix irq mappings */
499 pic_irq = piix3_state->dev.config[0x60 + irq_num];
501 /* the pic level is the logical OR of all the PCI irqs mapped
504 #if (PCI_IRQ_WORDS == 2)
505 pic_level = ((pci_irq_levels[irq_num][0] |
506 pci_irq_levels[irq_num][1]) != 0);
511 for(i = 0; i < PCI_IRQ_WORDS; i++) {
512 if (pci_irq_levels[irq_num][i]) {
519 pic_set_irq(pic_irq, pic_level);
523 /***********************************************************/
524 /* monitor info on PCI */
526 static void pci_info_device(PCIDevice *d)
531 printf(" Bus %2d, device %3d, function %d:\n",
532 d->bus_num, d->devfn >> 3, d->devfn & 7);
533 class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
537 printf("IDE controller");
540 printf("Ethernet controller");
543 printf("VGA controller");
546 printf("Class %04x", class);
549 printf(": PCI device %04x:%04x\n",
550 le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
551 le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
553 if (d->config[PCI_INTERRUPT_PIN] != 0) {
554 printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
556 for(i = 0;i < 6; i++) {
557 r = &d->io_regions[i];
559 printf(" BAR%d: ", i);
560 if (r->type & PCI_ADDRESS_SPACE_IO) {
561 printf("I/O at 0x%04x [0x%04x].\n",
562 r->addr, r->addr + r->size - 1);
564 printf("32 bit memory at 0x%08x [0x%08x].\n",
565 r->addr, r->addr + r->size - 1);
573 PCIBridge *s = &pci_bridge;
577 for(bus_num = 0; bus_num < 256; bus_num++) {
578 bus = s->pci_bus[bus_num];
580 for(devfn = 0; devfn < 256; devfn++) {
582 pci_info_device(bus[devfn]);
588 /***********************************************************/
589 /* XXX: the following should be moved to the PC BIOS */
591 static uint32_t isa_inb(uint32_t addr)
593 return cpu_inb(cpu_single_env, addr);
596 static void isa_outb(uint32_t val, uint32_t addr)
598 cpu_outb(cpu_single_env, addr, val);
601 static uint32_t isa_inw(uint32_t addr)
603 return cpu_inw(cpu_single_env, addr);
606 static void isa_outw(uint32_t val, uint32_t addr)
608 cpu_outw(cpu_single_env, addr, val);
611 static uint32_t isa_inl(uint32_t addr)
613 return cpu_inl(cpu_single_env, addr);
616 static void isa_outl(uint32_t val, uint32_t addr)
618 cpu_outl(cpu_single_env, addr, val);
621 static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
623 PCIBridge *s = &pci_bridge;
624 s->config_reg = 0x80000000 | (d->bus_num << 16) |
625 (d->devfn << 8) | addr;
626 pci_data_write(s, 0, val, 4);
629 static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
631 PCIBridge *s = &pci_bridge;
632 s->config_reg = 0x80000000 | (d->bus_num << 16) |
633 (d->devfn << 8) | (addr & ~3);
634 pci_data_write(s, addr & 3, val, 2);
637 static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
639 PCIBridge *s = &pci_bridge;
640 s->config_reg = 0x80000000 | (d->bus_num << 16) |
641 (d->devfn << 8) | (addr & ~3);
642 pci_data_write(s, addr & 3, val, 1);
645 static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
647 PCIBridge *s = &pci_bridge;
648 s->config_reg = 0x80000000 | (d->bus_num << 16) |
649 (d->devfn << 8) | addr;
650 return pci_data_read(s, 0, 4);
653 static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
655 PCIBridge *s = &pci_bridge;
656 s->config_reg = 0x80000000 | (d->bus_num << 16) |
657 (d->devfn << 8) | (addr & ~3);
658 return pci_data_read(s, addr & 3, 2);
661 static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
663 PCIBridge *s = &pci_bridge;
664 s->config_reg = 0x80000000 | (d->bus_num << 16) |
665 (d->devfn << 8) | (addr & ~3);
666 return pci_data_read(s, addr & 3, 1);
669 static uint32_t pci_bios_io_addr;
670 static uint32_t pci_bios_mem_addr;
671 /* host irqs corresponding to PCI irqs A-D */
672 static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
674 static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
679 pci_config_writel(d, 0x10 + region_num * 4, addr);
680 r = &d->io_regions[region_num];
682 /* enable memory mappings */
683 cmd = pci_config_readw(d, PCI_COMMAND);
684 if (r->type & PCI_ADDRESS_SPACE_IO)
688 pci_config_writew(d, PCI_COMMAND, cmd);
691 static void pci_bios_init_device(PCIDevice *d)
696 int i, pin, pic_irq, vendor_id, device_id;
698 class = pci_config_readw(d, PCI_CLASS_DEVICE);
701 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
702 device_id = pci_config_readw(d, PCI_DEVICE_ID);
703 if (vendor_id == 0x8086 && device_id == 0x7010) {
705 pci_config_writew(d, PCI_COMMAND, PCI_COMMAND_IO);
706 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
708 /* IDE: we map it as in ISA mode */
709 pci_set_io_region_addr(d, 0, 0x1f0);
710 pci_set_io_region_addr(d, 1, 0x3f4);
711 pci_set_io_region_addr(d, 2, 0x170);
712 pci_set_io_region_addr(d, 3, 0x374);
716 /* VGA: map frame buffer to default Bochs VBE address */
717 pci_set_io_region_addr(d, 0, 0xE0000000);
720 /* default memory mappings */
721 for(i = 0; i < 6; i++) {
722 r = &d->io_regions[i];
724 if (r->type & PCI_ADDRESS_SPACE_IO)
725 paddr = &pci_bios_io_addr;
727 paddr = &pci_bios_mem_addr;
728 *paddr = (*paddr + r->size - 1) & ~(r->size - 1);
729 pci_set_io_region_addr(d, i, *paddr);
736 /* map the interrupt */
737 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
739 pin = pci_slot_get_pirq(d, pin - 1);
740 pic_irq = pci_irqs[pin];
741 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
746 * This function initializes the PCI devices as a normal PCI BIOS
747 * would do. It is provided just in case the BIOS has no support for
750 void pci_bios_init(void)
752 PCIBridge *s = &pci_bridge;
754 int bus_num, devfn, i, irq;
757 pci_bios_io_addr = 0xc000;
758 pci_bios_mem_addr = 0xf0000000;
760 /* activate IRQ mappings */
763 for(i = 0; i < 4; i++) {
765 /* set to trigger level */
766 elcr[irq >> 3] |= (1 << (irq & 7));
767 /* activate irq remapping in PIIX */
768 pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
770 isa_outb(elcr[0], 0x4d0);
771 isa_outb(elcr[1], 0x4d1);
773 for(bus_num = 0; bus_num < 256; bus_num++) {
774 bus = s->pci_bus[bus_num];
776 for(devfn = 0; devfn < 256; devfn++) {
778 pci_bios_init_device(bus[devfn]);