4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
36 pci_set_irq_fn set_irq;
37 pci_map_irq_fn map_irq;
38 uint32_t config_reg; /* XXX: suppress */
40 SetIRQFunc *low_set_irq;
42 PCIDevice *devices[256];
43 PCIDevice *parent_dev;
45 /* The bus IRQ state is the logical OR of the connected devices.
46 Keep a count of the number of devices with raised IRQs. */
51 static void pci_update_mappings(PCIDevice *d);
52 static void pci_set_irq(void *opaque, int irq_num, int level);
54 target_phys_addr_t pci_mem_base;
55 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
56 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
57 static PCIBus *first_bus;
59 static void pcibus_save(QEMUFile *f, void *opaque)
61 PCIBus *bus = (PCIBus *)opaque;
64 qemu_put_be32(f, bus->nirq);
65 for (i = 0; i < bus->nirq; i++)
66 qemu_put_be32(f, bus->irq_count[i]);
69 static int pcibus_load(QEMUFile *f, void *opaque, int version_id)
71 PCIBus *bus = (PCIBus *)opaque;
77 nirq = qemu_get_be32(f);
78 if (bus->nirq != nirq) {
79 fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
84 for (i = 0; i < nirq; i++)
85 bus->irq_count[i] = qemu_get_be32(f);
90 static void pci_bus_reset(void *opaque)
92 PCIBus *bus = (PCIBus *)opaque;
95 for (i = 0; i < bus->nirq; i++) {
96 bus->irq_count[i] = 0;
98 for (i = 0; i < 256; i++) {
100 memset(bus->devices[i]->irq_state, 0,
101 sizeof(bus->devices[i]->irq_state));
105 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
106 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
107 qemu_irq *pic, int devfn_min, int nirq)
112 bus = FROM_QBUS(PCIBus, qbus_create(BUS_TYPE_PCI,
113 sizeof(PCIBus) + (nirq * sizeof(int)),
115 bus->set_irq = set_irq;
116 bus->map_irq = map_irq;
117 bus->irq_opaque = pic;
118 bus->devfn_min = devfn_min;
120 bus->next = first_bus;
122 register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
123 qemu_register_reset(pci_bus_reset, 0, bus);
127 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
130 bus = qemu_mallocz(sizeof(PCIBus));
131 bus->map_irq = map_irq;
132 bus->parent_dev = dev;
133 bus->next = dev->bus->next;
134 dev->bus->next = bus;
138 int pci_bus_num(PCIBus *s)
143 void pci_device_save(PCIDevice *s, QEMUFile *f)
147 qemu_put_be32(f, 2); /* PCI device version */
148 qemu_put_buffer(f, s->config, 256);
149 for (i = 0; i < 4; i++)
150 qemu_put_be32(f, s->irq_state[i]);
153 int pci_device_load(PCIDevice *s, QEMUFile *f)
158 version_id = qemu_get_be32(f);
161 qemu_get_buffer(f, s->config, 256);
162 pci_update_mappings(s);
165 for (i = 0; i < 4; i ++)
166 s->irq_state[i] = qemu_get_be32(f);
170 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
174 id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
175 id[0] = cpu_to_le16(pci_default_sub_vendor_id);
176 id[1] = cpu_to_le16(pci_default_sub_device_id);
181 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
183 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
188 unsigned long dom = 0, bus = 0;
192 val = strtoul(p, &e, 16);
198 val = strtoul(p, &e, 16);
205 val = strtoul(p, &e, 16);
211 if (dom > 0xffff || bus > 0xff || val > 0x1f)
219 /* Note: QEMU doesn't implement domains other than 0 */
220 if (dom != 0 || pci_find_bus(bus) == NULL)
229 int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
233 if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
236 return pci_parse_devaddr(devaddr, domp, busp, slotp);
239 static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
246 return pci_find_bus(0);
249 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
254 return pci_find_bus(bus);
257 static void pci_init_wmask(PCIDevice *dev)
260 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
261 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
262 dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY
263 | PCI_COMMAND_MASTER;
264 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
265 dev->wmask[i] = 0xff;
268 /* -1 for devfn means auto assign */
269 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
270 const char *name, int devfn,
271 PCIConfigReadFunc *config_read,
272 PCIConfigWriteFunc *config_write)
275 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
276 if (!bus->devices[devfn])
281 } else if (bus->devices[devfn]) {
285 pci_dev->devfn = devfn;
286 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
287 memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
288 pci_set_default_subsystem_id(pci_dev);
289 pci_init_wmask(pci_dev);
292 config_read = pci_default_read_config;
294 config_write = pci_default_write_config;
295 pci_dev->config_read = config_read;
296 pci_dev->config_write = config_write;
297 bus->devices[devfn] = pci_dev;
298 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
302 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
303 int instance_size, int devfn,
304 PCIConfigReadFunc *config_read,
305 PCIConfigWriteFunc *config_write)
309 pci_dev = qemu_mallocz(instance_size);
310 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
311 config_read, config_write);
314 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
316 return addr + pci_mem_base;
319 static void pci_unregister_io_regions(PCIDevice *pci_dev)
324 for(i = 0; i < PCI_NUM_REGIONS; i++) {
325 r = &pci_dev->io_regions[i];
326 if (!r->size || r->addr == -1)
328 if (r->type == PCI_ADDRESS_SPACE_IO) {
329 isa_unassign_ioport(r->addr, r->size);
331 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
338 int pci_unregister_device(PCIDevice *pci_dev)
342 if (pci_dev->unregister)
343 ret = pci_dev->unregister(pci_dev);
347 pci_unregister_io_regions(pci_dev);
349 qemu_free_irqs(pci_dev->irq);
350 pci_dev->bus->devices[pci_dev->devfn] = NULL;
351 qdev_free(&pci_dev->qdev);
355 void pci_register_bar(PCIDevice *pci_dev, int region_num,
356 uint32_t size, int type,
357 PCIMapIORegionFunc *map_func)
363 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
366 if (size & (size-1)) {
367 fprintf(stderr, "ERROR: PCI region size must be pow2 "
368 "type=0x%x, size=0x%x\n", type, size);
372 r = &pci_dev->io_regions[region_num];
376 r->map_func = map_func;
379 if (region_num == PCI_ROM_SLOT) {
381 /* ROM enable bit is writeable */
384 addr = 0x10 + region_num * 4;
386 *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
387 *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask);
390 static void pci_update_mappings(PCIDevice *d)
394 uint32_t last_addr, new_addr, config_ofs;
396 cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
397 for(i = 0; i < PCI_NUM_REGIONS; i++) {
398 r = &d->io_regions[i];
399 if (i == PCI_ROM_SLOT) {
402 config_ofs = 0x10 + i * 4;
405 if (r->type & PCI_ADDRESS_SPACE_IO) {
406 if (cmd & PCI_COMMAND_IO) {
407 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
409 new_addr = new_addr & ~(r->size - 1);
410 last_addr = new_addr + r->size - 1;
411 /* NOTE: we have only 64K ioports on PC */
412 if (last_addr <= new_addr || new_addr == 0 ||
413 last_addr >= 0x10000) {
420 if (cmd & PCI_COMMAND_MEMORY) {
421 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
423 /* the ROM slot has a specific enable bit */
424 if (i == PCI_ROM_SLOT && !(new_addr & 1))
426 new_addr = new_addr & ~(r->size - 1);
427 last_addr = new_addr + r->size - 1;
428 /* NOTE: we do not support wrapping */
429 /* XXX: as we cannot support really dynamic
430 mappings, we handle specific values as invalid
432 if (last_addr <= new_addr || new_addr == 0 ||
441 /* now do the real mapping */
442 if (new_addr != r->addr) {
444 if (r->type & PCI_ADDRESS_SPACE_IO) {
446 /* NOTE: specific hack for IDE in PC case:
447 only one byte must be mapped. */
448 class = d->config[0x0a] | (d->config[0x0b] << 8);
449 if (class == 0x0101 && r->size == 4) {
450 isa_unassign_ioport(r->addr + 2, 1);
452 isa_unassign_ioport(r->addr, r->size);
455 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
458 qemu_unregister_coalesced_mmio(r->addr, r->size);
463 r->map_func(d, i, r->addr, r->size, r->type);
470 uint32_t pci_default_read_config(PCIDevice *d,
471 uint32_t address, int len)
478 if (address <= 0xfc) {
479 val = le32_to_cpu(*(uint32_t *)(d->config + address));
484 if (address <= 0xfe) {
485 val = le16_to_cpu(*(uint16_t *)(d->config + address));
490 val = d->config[address];
496 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
498 uint8_t orig[PCI_CONFIG_SPACE_SIZE];
501 /* not efficient, but simple */
502 memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
503 for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) {
504 uint8_t wmask = d->wmask[addr];
505 d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
507 if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24)
508 || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
509 & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
510 pci_update_mappings(d);
513 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
517 int config_addr, bus_num;
519 #if defined(DEBUG_PCI) && 0
520 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
523 bus_num = (addr >> 16) & 0xff;
524 while (s && s->bus_num != bus_num)
528 pci_dev = s->devices[(addr >> 8) & 0xff];
531 config_addr = addr & 0xff;
532 #if defined(DEBUG_PCI)
533 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
534 pci_dev->name, config_addr, val, len);
536 pci_dev->config_write(pci_dev, config_addr, val, len);
539 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
543 int config_addr, bus_num;
546 bus_num = (addr >> 16) & 0xff;
547 while (s && s->bus_num != bus_num)
551 pci_dev = s->devices[(addr >> 8) & 0xff];
568 config_addr = addr & 0xff;
569 val = pci_dev->config_read(pci_dev, config_addr, len);
570 #if defined(DEBUG_PCI)
571 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
572 pci_dev->name, config_addr, val, len);
575 #if defined(DEBUG_PCI) && 0
576 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
582 /***********************************************************/
583 /* generic PCI irq support */
585 /* 0 <= irq_num <= 3. level must be 0 or 1 */
586 static void pci_set_irq(void *opaque, int irq_num, int level)
588 PCIDevice *pci_dev = (PCIDevice *)opaque;
592 change = level - pci_dev->irq_state[irq_num];
596 pci_dev->irq_state[irq_num] = level;
599 irq_num = bus->map_irq(pci_dev, irq_num);
602 pci_dev = bus->parent_dev;
604 bus->irq_count[irq_num] += change;
605 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
608 /***********************************************************/
609 /* monitor info on PCI */
616 static const pci_class_desc pci_class_descriptions[] =
618 { 0x0100, "SCSI controller"},
619 { 0x0101, "IDE controller"},
620 { 0x0102, "Floppy controller"},
621 { 0x0103, "IPI controller"},
622 { 0x0104, "RAID controller"},
623 { 0x0106, "SATA controller"},
624 { 0x0107, "SAS controller"},
625 { 0x0180, "Storage controller"},
626 { 0x0200, "Ethernet controller"},
627 { 0x0201, "Token Ring controller"},
628 { 0x0202, "FDDI controller"},
629 { 0x0203, "ATM controller"},
630 { 0x0280, "Network controller"},
631 { 0x0300, "VGA controller"},
632 { 0x0301, "XGA controller"},
633 { 0x0302, "3D controller"},
634 { 0x0380, "Display controller"},
635 { 0x0400, "Video controller"},
636 { 0x0401, "Audio controller"},
638 { 0x0480, "Multimedia controller"},
639 { 0x0500, "RAM controller"},
640 { 0x0501, "Flash controller"},
641 { 0x0580, "Memory controller"},
642 { 0x0600, "Host bridge"},
643 { 0x0601, "ISA bridge"},
644 { 0x0602, "EISA bridge"},
645 { 0x0603, "MC bridge"},
646 { 0x0604, "PCI bridge"},
647 { 0x0605, "PCMCIA bridge"},
648 { 0x0606, "NUBUS bridge"},
649 { 0x0607, "CARDBUS bridge"},
650 { 0x0608, "RACEWAY bridge"},
652 { 0x0c03, "USB controller"},
656 static void pci_info_device(PCIDevice *d)
658 Monitor *mon = cur_mon;
661 const pci_class_desc *desc;
663 monitor_printf(mon, " Bus %2d, device %3d, function %d:\n",
664 d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
665 class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
666 monitor_printf(mon, " ");
667 desc = pci_class_descriptions;
668 while (desc->desc && class != desc->class)
671 monitor_printf(mon, "%s", desc->desc);
673 monitor_printf(mon, "Class %04x", class);
675 monitor_printf(mon, ": PCI device %04x:%04x\n",
676 le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
677 le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
679 if (d->config[PCI_INTERRUPT_PIN] != 0) {
680 monitor_printf(mon, " IRQ %d.\n",
681 d->config[PCI_INTERRUPT_LINE]);
683 if (class == 0x0604) {
684 monitor_printf(mon, " BUS %d.\n", d->config[0x19]);
686 for(i = 0;i < PCI_NUM_REGIONS; i++) {
687 r = &d->io_regions[i];
689 monitor_printf(mon, " BAR%d: ", i);
690 if (r->type & PCI_ADDRESS_SPACE_IO) {
691 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
692 r->addr, r->addr + r->size - 1);
694 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
695 r->addr, r->addr + r->size - 1);
699 if (class == 0x0604 && d->config[0x19] != 0) {
700 pci_for_each_device(d->config[0x19], pci_info_device);
704 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
706 PCIBus *bus = first_bus;
710 while (bus && bus->bus_num != bus_num)
713 for(devfn = 0; devfn < 256; devfn++) {
714 d = bus->devices[devfn];
721 void pci_info(Monitor *mon)
723 pci_for_each_device(0, pci_info_device);
726 PCIDevice *pci_create(const char *name, const char *devaddr)
732 bus = pci_get_bus_devfn(&devfn, devaddr);
734 fprintf(stderr, "Invalid PCI device address %s for device %s\n",
739 dev = qdev_create(&bus->qbus, name);
740 qdev_set_prop_int(dev, "devfn", devfn);
741 return (PCIDevice *)dev;
744 static const char * const pci_nic_models[] = {
756 static const char * const pci_nic_names[] = {
768 /* Initialize a PCI NIC. */
769 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
770 const char *default_devaddr)
772 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
777 qemu_check_nic_model_list(nd, pci_nic_models, default_model);
779 for (i = 0; pci_nic_models[i]; i++) {
780 if (strcmp(nd->model, pci_nic_models[i]) == 0) {
781 pci_dev = pci_create(pci_nic_names[i], devaddr);
782 dev = &pci_dev->qdev;
783 qdev_set_netdev(dev, nd);
798 static void pci_bridge_write_config(PCIDevice *d,
799 uint32_t address, uint32_t val, int len)
801 PCIBridge *s = (PCIBridge *)d;
803 pci_default_write_config(d, address, val, len);
804 s->bus->bus_num = d->config[PCI_SECONDARY_BUS];
807 PCIBus *pci_find_bus(int bus_num)
809 PCIBus *bus = first_bus;
811 while (bus && bus->bus_num != bus_num)
817 PCIDevice *pci_find_device(int bus_num, int slot, int function)
819 PCIBus *bus = pci_find_bus(bus_num);
824 return bus->devices[PCI_DEVFN(slot, function)];
827 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
828 pci_map_irq_fn map_irq, const char *name)
831 s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
832 devfn, NULL, pci_bridge_write_config);
834 pci_config_set_vendor_id(s->dev.config, vid);
835 pci_config_set_device_id(s->dev.config, did);
837 s->dev.config[0x04] = 0x06; // command = bus master, pci mem
838 s->dev.config[0x05] = 0x00;
839 s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
840 s->dev.config[0x07] = 0x00; // status = fast devsel
841 s->dev.config[0x08] = 0x00; // revision
842 s->dev.config[0x09] = 0x00; // programming i/f
843 pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
844 s->dev.config[0x0D] = 0x10; // latency_timer
845 s->dev.config[PCI_HEADER_TYPE] =
846 PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
847 s->dev.config[0x1E] = 0xa0; // secondary status
849 s->bus = pci_register_secondary_bus(&s->dev, map_irq);
855 pci_qdev_initfn init;
858 static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
860 PCIDevice *pci_dev = (PCIDevice *)qdev;
861 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
865 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
866 devfn = qdev_get_prop_int(qdev, "devfn", -1);
867 pci_dev = do_pci_register_device(pci_dev, bus, "FIXME", devfn,
868 NULL, NULL);//FIXME:config_read, config_write);
873 void pci_qdev_register(const char *name, int size, pci_qdev_initfn init)
877 info = qemu_mallocz(sizeof(*info));
878 info->qdev.name = qemu_strdup(name);
879 info->qdev.size = size;
881 info->qdev.init = pci_qdev_init;
882 info->qdev.bus_type = BUS_TYPE_PCI;
884 qdev_register(&info->qdev);
887 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
891 dev = qdev_create(&bus->qbus, name);
892 qdev_set_prop_int(dev, "devfn", devfn);
895 return (PCIDevice *)dev;
898 static int pci_find_space(PCIDevice *pdev, uint8_t size)
900 int offset = PCI_CONFIG_HEADER_SIZE;
902 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
905 else if (i - offset + 1 == size)
910 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
915 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
918 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
919 prev = next + PCI_CAP_LIST_NEXT)
920 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
928 /* Reserve space and add capability to the linked list in pci config space */
929 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
931 uint8_t offset = pci_find_space(pdev, size);
932 uint8_t *config = pdev->config + offset;
935 config[PCI_CAP_LIST_ID] = cap_id;
936 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
937 pdev->config[PCI_CAPABILITY_LIST] = offset;
938 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
939 memset(pdev->used + offset, 0xFF, size);
940 /* Make capability read-only by default */
941 memset(pdev->wmask + offset, 0, size);
945 /* Unlink capability from the pci config space. */
946 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
948 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
951 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
952 /* Make capability writeable again */
953 memset(pdev->wmask + offset, 0xff, size);
954 memset(pdev->used + offset, 0, size);
956 if (!pdev->config[PCI_CAPABILITY_LIST])
957 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
960 /* Reserve space for capability at a known offset (to call after load). */
961 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
963 memset(pdev->used + offset, 0xff, size);
966 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
968 return pci_find_capability_list(pdev, cap_id, NULL);