4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 pci_set_irq_fn set_irq;
32 pci_map_irq_fn map_irq;
33 uint32_t config_reg; /* XXX: suppress */
35 SetIRQFunc *low_set_irq;
37 PCIDevice *devices[256];
38 PCIDevice *parent_dev;
40 /* The bus IRQ state is the logical OR of the connected devices.
41 Keep a count of the number of devices with raised IRQs. */
45 static void pci_update_mappings(PCIDevice *d);
47 target_phys_addr_t pci_mem_base;
48 static int pci_irq_index;
49 static PCIBus *first_bus;
51 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
52 void *pic, int devfn_min, int nirq)
55 bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
56 bus->set_irq = set_irq;
57 bus->map_irq = map_irq;
58 bus->irq_opaque = pic;
59 bus->devfn_min = devfn_min;
64 PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
67 bus = qemu_mallocz(sizeof(PCIBus));
68 bus->map_irq = map_irq;
69 bus->parent_dev = dev;
70 bus->next = dev->bus->next;
75 int pci_bus_num(PCIBus *s)
80 void pci_device_save(PCIDevice *s, QEMUFile *f)
82 qemu_put_be32(f, 1); /* PCI device version */
83 qemu_put_buffer(f, s->config, 256);
86 int pci_device_load(PCIDevice *s, QEMUFile *f)
89 version_id = qemu_get_be32(f);
92 qemu_get_buffer(f, s->config, 256);
93 pci_update_mappings(s);
97 /* -1 for devfn means auto assign */
98 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
99 int instance_size, int devfn,
100 PCIConfigReadFunc *config_read,
101 PCIConfigWriteFunc *config_write)
105 if (pci_irq_index >= PCI_DEVICES_MAX)
109 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
110 if (!bus->devices[devfn])
116 pci_dev = qemu_mallocz(instance_size);
120 pci_dev->devfn = devfn;
121 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
122 memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
125 config_read = pci_default_read_config;
127 config_write = pci_default_write_config;
128 pci_dev->config_read = config_read;
129 pci_dev->config_write = config_write;
130 pci_dev->irq_index = pci_irq_index++;
131 bus->devices[devfn] = pci_dev;
135 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
136 uint32_t size, int type,
137 PCIMapIORegionFunc *map_func)
142 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
144 r = &pci_dev->io_regions[region_num];
148 r->map_func = map_func;
149 if (region_num == PCI_ROM_SLOT) {
152 addr = 0x10 + region_num * 4;
154 *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
157 target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
159 return addr + pci_mem_base;
162 static void pci_update_mappings(PCIDevice *d)
166 uint32_t last_addr, new_addr, config_ofs;
168 cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
169 for(i = 0; i < PCI_NUM_REGIONS; i++) {
170 r = &d->io_regions[i];
171 if (i == PCI_ROM_SLOT) {
174 config_ofs = 0x10 + i * 4;
177 if (r->type & PCI_ADDRESS_SPACE_IO) {
178 if (cmd & PCI_COMMAND_IO) {
179 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
181 new_addr = new_addr & ~(r->size - 1);
182 last_addr = new_addr + r->size - 1;
183 /* NOTE: we have only 64K ioports on PC */
184 if (last_addr <= new_addr || new_addr == 0 ||
185 last_addr >= 0x10000) {
192 if (cmd & PCI_COMMAND_MEMORY) {
193 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
195 /* the ROM slot has a specific enable bit */
196 if (i == PCI_ROM_SLOT && !(new_addr & 1))
198 new_addr = new_addr & ~(r->size - 1);
199 last_addr = new_addr + r->size - 1;
200 /* NOTE: we do not support wrapping */
201 /* XXX: as we cannot support really dynamic
202 mappings, we handle specific values as invalid
204 if (last_addr <= new_addr || new_addr == 0 ||
213 /* now do the real mapping */
214 if (new_addr != r->addr) {
216 if (r->type & PCI_ADDRESS_SPACE_IO) {
218 /* NOTE: specific hack for IDE in PC case:
219 only one byte must be mapped. */
220 class = d->config[0x0a] | (d->config[0x0b] << 8);
221 if (class == 0x0101 && r->size == 4) {
222 isa_unassign_ioport(r->addr + 2, 1);
224 isa_unassign_ioport(r->addr, r->size);
227 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
234 r->map_func(d, i, r->addr, r->size, r->type);
241 uint32_t pci_default_read_config(PCIDevice *d,
242 uint32_t address, int len)
247 val = d->config[address];
250 val = le16_to_cpu(*(uint16_t *)(d->config + address));
254 val = le32_to_cpu(*(uint32_t *)(d->config + address));
260 void pci_default_write_config(PCIDevice *d,
261 uint32_t address, uint32_t val, int len)
266 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
267 (address >= 0x30 && address < 0x34))) {
271 if ( address >= 0x30 ) {
274 reg = (address - 0x10) >> 2;
276 r = &d->io_regions[reg];
279 /* compute the stored value */
280 if (reg == PCI_ROM_SLOT) {
281 /* keep ROM enable bit */
282 val &= (~(r->size - 1)) | 1;
284 val &= ~(r->size - 1);
287 *(uint32_t *)(d->config + address) = cpu_to_le32(val);
288 pci_update_mappings(d);
292 /* not efficient, but simple */
294 for(i = 0; i < len; i++) {
295 /* default read/write accesses */
296 switch(d->config[0x0e]) {
309 case 0x10 ... 0x27: /* base */
310 case 0x30 ... 0x33: /* rom */
331 case 0x38 ... 0x3b: /* rom */
342 d->config[addr] = val;
349 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
350 /* if the command register is modified, we must modify the mappings */
351 pci_update_mappings(d);
355 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
359 int config_addr, bus_num;
361 #if defined(DEBUG_PCI) && 0
362 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
365 bus_num = (addr >> 16) & 0xff;
366 while (s && s->bus_num != bus_num)
370 pci_dev = s->devices[(addr >> 8) & 0xff];
373 config_addr = addr & 0xff;
374 #if defined(DEBUG_PCI)
375 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
376 pci_dev->name, config_addr, val, len);
378 pci_dev->config_write(pci_dev, config_addr, val, len);
381 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
385 int config_addr, bus_num;
388 bus_num = (addr >> 16) & 0xff;
389 while (s && s->bus_num != bus_num)
393 pci_dev = s->devices[(addr >> 8) & 0xff];
410 config_addr = addr & 0xff;
411 val = pci_dev->config_read(pci_dev, config_addr, len);
412 #if defined(DEBUG_PCI)
413 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
414 pci_dev->name, config_addr, val, len);
417 #if defined(DEBUG_PCI) && 0
418 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
424 /***********************************************************/
425 /* generic PCI irq support */
427 /* 0 <= irq_num <= 3. level must be 0 or 1 */
428 void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
433 change = level - pci_dev->irq_state[irq_num];
437 pci_dev->irq_state[irq_num] = level;
439 while (!bus->set_irq) {
440 irq_num = bus->map_irq(pci_dev, irq_num);
441 pci_dev = bus->parent_dev;
444 bus->irq_count[irq_num] += change;
445 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
448 /***********************************************************/
449 /* monitor info on PCI */
456 static pci_class_desc pci_class_descriptions[] =
458 { 0x0100, "SCSI controller"},
459 { 0x0101, "IDE controller"},
460 { 0x0200, "Ethernet controller"},
461 { 0x0300, "VGA controller"},
462 { 0x0600, "Host bridge"},
463 { 0x0601, "ISA bridge"},
464 { 0x0604, "PCI bridge"},
465 { 0x0c03, "USB controller"},
469 static void pci_info_device(PCIDevice *d)
473 pci_class_desc *desc;
475 term_printf(" Bus %2d, device %3d, function %d:\n",
476 d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
477 class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
479 desc = pci_class_descriptions;
480 while (desc->desc && class != desc->class)
483 term_printf("%s", desc->desc);
485 term_printf("Class %04x", class);
487 term_printf(": PCI device %04x:%04x\n",
488 le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
489 le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
491 if (d->config[PCI_INTERRUPT_PIN] != 0) {
492 term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
494 if (class == 0x0604) {
495 term_printf(" BUS %d.\n", d->config[0x19]);
497 for(i = 0;i < PCI_NUM_REGIONS; i++) {
498 r = &d->io_regions[i];
500 term_printf(" BAR%d: ", i);
501 if (r->type & PCI_ADDRESS_SPACE_IO) {
502 term_printf("I/O at 0x%04x [0x%04x].\n",
503 r->addr, r->addr + r->size - 1);
505 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
506 r->addr, r->addr + r->size - 1);
510 if (class == 0x0604 && d->config[0x19] != 0) {
511 pci_for_each_device(d->config[0x19], pci_info_device);
515 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
517 PCIBus *bus = first_bus;
521 while (bus && bus->bus_num != bus_num)
524 for(devfn = 0; devfn < 256; devfn++) {
525 d = bus->devices[devfn];
534 pci_for_each_device(0, pci_info_device);
537 /* Initialize a PCI NIC. */
538 void pci_nic_init(PCIBus *bus, NICInfo *nd)
540 if (strcmp(nd->model, "ne2k_pci") == 0) {
541 pci_ne2000_init(bus, nd);
542 } else if (strcmp(nd->model, "rtl8139") == 0) {
543 pci_rtl8139_init(bus, nd);
544 } else if (strcmp(nd->model, "pcnet") == 0) {
545 pci_pcnet_init(bus, nd);
547 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
557 void pci_bridge_write_config(PCIDevice *d,
558 uint32_t address, uint32_t val, int len)
560 PCIBridge *s = (PCIBridge *)d;
562 if (address == 0x19 || (address == 0x18 && len > 1)) {
564 s->bus->bus_num = val & 0xff;
566 s->bus->bus_num = (val >> 8) & 0xff;
567 #if defined(DEBUG_PCI)
568 printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
571 pci_default_write_config(d, address, val, len);
574 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
575 pci_map_irq_fn map_irq, const char *name)
578 s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
579 devfn, NULL, pci_bridge_write_config);
580 s->dev.config[0x00] = id >> 16;
581 s->dev.config[0x01] = id > 24;
582 s->dev.config[0x02] = id; // device_id
583 s->dev.config[0x03] = id >> 8;
584 s->dev.config[0x04] = 0x06; // command = bus master, pci mem
585 s->dev.config[0x05] = 0x00;
586 s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
587 s->dev.config[0x07] = 0x00; // status = fast devsel
588 s->dev.config[0x08] = 0x00; // revision
589 s->dev.config[0x09] = 0x00; // programming i/f
590 s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge
591 s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge
592 s->dev.config[0x0D] = 0x10; // latency_timer
593 s->dev.config[0x0E] = 0x81; // header_type
594 s->dev.config[0x1E] = 0xa0; // secondary status
596 s->bus = pci_register_secondary_bus(&s->dev, map_irq);