4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 pci_set_irq_fn set_irq;
32 pci_map_irq_fn map_irq;
33 uint32_t config_reg; /* XXX: suppress */
35 SetIRQFunc *low_set_irq;
37 PCIDevice *devices[256];
38 /* The bus IRQ state is the logical OR of the connected devices.
39 Keep a count of the number of devices with raised IRQs. */
43 static void pci_update_mappings(PCIDevice *d);
45 target_phys_addr_t pci_mem_base;
46 static int pci_irq_index;
47 static PCIBus *first_bus;
49 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
50 void *pic, int devfn_min)
53 bus = qemu_mallocz(sizeof(PCIBus));
54 bus->set_irq = set_irq;
55 bus->map_irq = map_irq;
56 bus->irq_opaque = pic;
57 bus->devfn_min = devfn_min;
58 memset(bus->irq_count, 0, sizeof(bus->irq_count));
63 int pci_bus_num(PCIBus *s)
68 void pci_device_save(PCIDevice *s, QEMUFile *f)
70 qemu_put_be32(f, 1); /* PCI device version */
71 qemu_put_buffer(f, s->config, 256);
74 int pci_device_load(PCIDevice *s, QEMUFile *f)
77 version_id = qemu_get_be32(f);
80 qemu_get_buffer(f, s->config, 256);
81 pci_update_mappings(s);
85 /* -1 for devfn means auto assign */
86 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
87 int instance_size, int devfn,
88 PCIConfigReadFunc *config_read,
89 PCIConfigWriteFunc *config_write)
93 if (pci_irq_index >= PCI_DEVICES_MAX)
97 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
98 if (!bus->devices[devfn])
104 pci_dev = qemu_mallocz(instance_size);
108 pci_dev->devfn = devfn;
109 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
110 memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
113 config_read = pci_default_read_config;
115 config_write = pci_default_write_config;
116 pci_dev->config_read = config_read;
117 pci_dev->config_write = config_write;
118 pci_dev->irq_index = pci_irq_index++;
119 bus->devices[devfn] = pci_dev;
123 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
124 uint32_t size, int type,
125 PCIMapIORegionFunc *map_func)
130 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
132 r = &pci_dev->io_regions[region_num];
136 r->map_func = map_func;
137 if (region_num == PCI_ROM_SLOT) {
140 addr = 0x10 + region_num * 4;
142 *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
145 target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
147 return addr + pci_mem_base;
150 static void pci_update_mappings(PCIDevice *d)
154 uint32_t last_addr, new_addr, config_ofs;
156 cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
157 for(i = 0; i < PCI_NUM_REGIONS; i++) {
158 r = &d->io_regions[i];
159 if (i == PCI_ROM_SLOT) {
162 config_ofs = 0x10 + i * 4;
165 if (r->type & PCI_ADDRESS_SPACE_IO) {
166 if (cmd & PCI_COMMAND_IO) {
167 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
169 new_addr = new_addr & ~(r->size - 1);
170 last_addr = new_addr + r->size - 1;
171 /* NOTE: we have only 64K ioports on PC */
172 if (last_addr <= new_addr || new_addr == 0 ||
173 last_addr >= 0x10000) {
180 if (cmd & PCI_COMMAND_MEMORY) {
181 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
183 /* the ROM slot has a specific enable bit */
184 if (i == PCI_ROM_SLOT && !(new_addr & 1))
186 new_addr = new_addr & ~(r->size - 1);
187 last_addr = new_addr + r->size - 1;
188 /* NOTE: we do not support wrapping */
189 /* XXX: as we cannot support really dynamic
190 mappings, we handle specific values as invalid
192 if (last_addr <= new_addr || new_addr == 0 ||
201 /* now do the real mapping */
202 if (new_addr != r->addr) {
204 if (r->type & PCI_ADDRESS_SPACE_IO) {
206 /* NOTE: specific hack for IDE in PC case:
207 only one byte must be mapped. */
208 class = d->config[0x0a] | (d->config[0x0b] << 8);
209 if (class == 0x0101 && r->size == 4) {
210 isa_unassign_ioport(r->addr + 2, 1);
212 isa_unassign_ioport(r->addr, r->size);
215 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
222 r->map_func(d, i, r->addr, r->size, r->type);
229 uint32_t pci_default_read_config(PCIDevice *d,
230 uint32_t address, int len)
235 val = d->config[address];
238 val = le16_to_cpu(*(uint16_t *)(d->config + address));
242 val = le32_to_cpu(*(uint32_t *)(d->config + address));
248 void pci_default_write_config(PCIDevice *d,
249 uint32_t address, uint32_t val, int len)
254 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
255 (address >= 0x30 && address < 0x34))) {
259 if ( address >= 0x30 ) {
262 reg = (address - 0x10) >> 2;
264 r = &d->io_regions[reg];
267 /* compute the stored value */
268 if (reg == PCI_ROM_SLOT) {
269 /* keep ROM enable bit */
270 val &= (~(r->size - 1)) | 1;
272 val &= ~(r->size - 1);
275 *(uint32_t *)(d->config + address) = cpu_to_le32(val);
276 pci_update_mappings(d);
280 /* not efficient, but simple */
282 for(i = 0; i < len; i++) {
283 /* default read/write accesses */
284 switch(d->config[0x0e]) {
297 case 0x10 ... 0x27: /* base */
298 case 0x30 ... 0x33: /* rom */
319 case 0x38 ... 0x3b: /* rom */
330 d->config[addr] = val;
337 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
338 /* if the command register is modified, we must modify the mappings */
339 pci_update_mappings(d);
343 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
347 int config_addr, bus_num;
349 #if defined(DEBUG_PCI) && 0
350 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
353 bus_num = (addr >> 16) & 0xff;
356 pci_dev = s->devices[(addr >> 8) & 0xff];
359 config_addr = addr & 0xff;
360 #if defined(DEBUG_PCI)
361 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
362 pci_dev->name, config_addr, val, len);
364 pci_dev->config_write(pci_dev, config_addr, val, len);
367 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
371 int config_addr, bus_num;
374 bus_num = (addr >> 16) & 0xff;
377 pci_dev = s->devices[(addr >> 8) & 0xff];
394 config_addr = addr & 0xff;
395 val = pci_dev->config_read(pci_dev, config_addr, len);
396 #if defined(DEBUG_PCI)
397 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
398 pci_dev->name, config_addr, val, len);
401 #if defined(DEBUG_PCI) && 0
402 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
408 /***********************************************************/
409 /* generic PCI irq support */
411 /* 0 <= irq_num <= 3. level must be 0 or 1 */
412 void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
414 PCIBus *bus = pci_dev->bus;
416 irq_num = bus->map_irq(pci_dev, irq_num);
417 bus->irq_count[irq_num] += level - pci_dev->irq_state[irq_num];
418 pci_dev->irq_state[irq_num] = level;
419 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
422 /***********************************************************/
423 /* monitor info on PCI */
430 static pci_class_desc pci_class_descriptions[] =
432 { 0x0100, "SCSI controller"},
433 { 0x0101, "IDE controller"},
434 { 0x0200, "Ethernet controller"},
435 { 0x0300, "VGA controller"},
436 { 0x0600, "Host bridge"},
437 { 0x0601, "ISA bridge"},
438 { 0x0604, "PCI bridge"},
439 { 0x0c03, "USB controller"},
443 static void pci_info_device(PCIDevice *d)
447 pci_class_desc *desc;
449 term_printf(" Bus %2d, device %3d, function %d:\n",
450 d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
451 class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
453 desc = pci_class_descriptions;
454 while (desc->desc && class != desc->class)
457 term_printf("%s", desc->desc);
459 term_printf("Class %04x", class);
461 term_printf(": PCI device %04x:%04x\n",
462 le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
463 le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
465 if (d->config[PCI_INTERRUPT_PIN] != 0) {
466 term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
468 for(i = 0;i < PCI_NUM_REGIONS; i++) {
469 r = &d->io_regions[i];
471 term_printf(" BAR%d: ", i);
472 if (r->type & PCI_ADDRESS_SPACE_IO) {
473 term_printf("I/O at 0x%04x [0x%04x].\n",
474 r->addr, r->addr + r->size - 1);
476 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
477 r->addr, r->addr + r->size - 1);
483 void pci_for_each_device(void (*fn)(PCIDevice *d))
485 PCIBus *bus = first_bus;
490 for(devfn = 0; devfn < 256; devfn++) {
491 d = bus->devices[devfn];
500 pci_for_each_device(pci_info_device);
503 /* Initialize a PCI NIC. */
504 void pci_nic_init(PCIBus *bus, NICInfo *nd)
506 if (strcmp(nd->model, "ne2k_pci") == 0) {
507 pci_ne2000_init(bus, nd);
508 } else if (strcmp(nd->model, "rtl8139") == 0) {
509 pci_rtl8139_init(bus, nd);
510 } else if (strcmp(nd->model, "pcnet") == 0) {
511 pci_pcnet_init(bus, nd);
513 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);