2 * Arm PrimeCell PL050 Keyboard / Mouse Interface
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
23 static const unsigned char pl050_id[] =
24 { 0x50, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
26 static void pl050_update(void *opaque, int level)
28 pl050_state *s = (pl050_state *)opaque;
32 raise = (s->pending && (s->cr & 0x10) != 0)
33 || (s->cr & 0x08) != 0;
34 qemu_set_irq(s->irq, raise);
37 static uint32_t pl050_read(void *opaque, target_phys_addr_t offset)
39 pl050_state *s = (pl050_state *)opaque;
41 if (offset >= 0xfe0 && offset < 0x1000)
42 return pl050_id[(offset - 0xfe0) >> 2];
44 switch (offset >> 2) {
48 /* KMIC and KMID bits not implemented. */
56 s->last = ps2_read_data(s->dev);
58 case 3: /* KMICLKDIV */
61 return s->pending | 2;
63 cpu_abort (cpu_single_env, "pl050_read: Bad offset %x\n", offset);
68 static void pl050_write(void *opaque, target_phys_addr_t offset,
71 pl050_state *s = (pl050_state *)opaque;
73 switch (offset >> 2) {
76 pl050_update(s, s->pending);
77 /* ??? Need to implement the enable/disable bit. */
80 /* ??? This should toggle the TX interrupt line. */
81 /* ??? This means kbd/mouse can block each other. */
83 ps2_write_mouse(s->dev, value);
85 ps2_write_keyboard(s->dev, value);
88 case 3: /* KMICLKDIV */
92 cpu_abort (cpu_single_env, "pl050_write: Bad offset %x\n", offset);
95 static CPUReadMemoryFunc *pl050_readfn[] = {
101 static CPUWriteMemoryFunc *pl050_writefn[] = {
107 void pl050_init(uint32_t base, qemu_irq irq, int is_mouse)
112 s = (pl050_state *)qemu_mallocz(sizeof(pl050_state));
113 iomemtype = cpu_register_io_memory(0, pl050_readfn,
115 cpu_register_physical_memory(base, 0x00000fff, iomemtype);
118 s->is_mouse = is_mouse;
120 s->dev = ps2_mouse_init(pl050_update, s);
122 s->dev = ps2_kbd_init(pl050_update, s);
123 /* ??? Save/restore. */