2 * Arm PrimeCell PL061 General Purpose IO with additional
3 * Luminary Micro Stellaris bits.
5 * Copyright (c) 2007 CodeSourcery.
6 * Written by Paul Brook
8 * This code is licenced under the GPL.
12 #include "primecell.h"
14 //#define DEBUG_PL061 1
17 #define DPRINTF(fmt, args...) \
18 do { printf("pl061: " fmt , ##args); } while (0)
19 #define BADF(fmt, args...) \
20 do { fprintf(stderr, "pl061: error: " fmt , ##args); exit(1);} while (0)
22 #define DPRINTF(fmt, args...) do {} while(0)
23 #define BADF(fmt, args...) \
24 do { fprintf(stderr, "pl061: error: " fmt , ##args);} while (0)
27 static const uint8_t pl061_id[12] =
28 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
55 static void pl061_update(pl061_state *s)
61 changed = s->old_data ^ s->data;
65 s->old_data = s->data;
66 for (i = 0; i < 8; i++) {
68 if ((changed & mask & s->dir) && s->out) {
69 DPRINTF("Set output %d = %d\n", i, (s->data & mask) != 0);
70 qemu_set_irq(s->out[i], (s->data & mask) != 0);
74 /* FIXME: Implement input interrupts. */
77 static uint32_t pl061_read(void *opaque, target_phys_addr_t offset)
79 pl061_state *s = (pl061_state *)opaque;
82 if (offset >= 0xfd0 && offset < 0x1000) {
83 return pl061_id[(offset - 0xfd0) >> 2];
86 return s->data & (offset >> 2);
89 case 0x400: /* Direction */
91 case 0x404: /* Interrupt sense */
93 case 0x408: /* Interrupt both edges */
95 case 0x40c: /* Interupt event */
97 case 0x410: /* Interrupt mask */
99 case 0x414: /* Raw interrupt status */
101 case 0x418: /* Masked interrupt status */
102 return s->istate | s->im;
103 case 0x420: /* Alternate function select */
105 case 0x500: /* 2mA drive */
107 case 0x504: /* 4mA drive */
109 case 0x508: /* 8mA drive */
111 case 0x50c: /* Open drain */
113 case 0x510: /* Pull-up */
115 case 0x514: /* Pull-down */
117 case 0x518: /* Slew rate control */
119 case 0x51c: /* Digital enable */
121 case 0x520: /* Lock */
123 case 0x524: /* Commit */
126 cpu_abort (cpu_single_env, "pl061_read: Bad offset %x\n",
132 static void pl061_write(void *opaque, target_phys_addr_t offset,
135 pl061_state *s = (pl061_state *)opaque;
139 if (offset < 0x400) {
140 mask = (offset >> 2) & s->dir;
141 s->data = (s->data & ~mask) | (value & mask);
146 case 0x400: /* Direction */
149 case 0x404: /* Interrupt sense */
152 case 0x408: /* Interrupt both edges */
155 case 0x40c: /* Interupt event */
158 case 0x410: /* Interrupt mask */
161 case 0x41c: /* Interrupt clear */
164 case 0x420: /* Alternate function select */
166 s->afsel = (s->afsel & ~mask) | (value & mask);
168 case 0x500: /* 2mA drive */
171 case 0x504: /* 4mA drive */
174 case 0x508: /* 8mA drive */
177 case 0x50c: /* Open drain */
180 case 0x510: /* Pull-up */
183 case 0x514: /* Pull-down */
186 case 0x518: /* Slew rate control */
189 case 0x51c: /* Digital enable */
192 case 0x520: /* Lock */
193 s->locked = (value != 0xacce551);
195 case 0x524: /* Commit */
200 cpu_abort (cpu_single_env, "pl061_write: Bad offset %x\n",
206 static void pl061_reset(pl061_state *s)
212 static void pl061_set_irq(void * opaque, int irq, int level)
214 pl061_state *s = (pl061_state *)opaque;
218 if ((s->dir & mask) == 0) {
226 static CPUReadMemoryFunc *pl061_readfn[] = {
232 static CPUWriteMemoryFunc *pl061_writefn[] = {
238 /* Returns an array of inputs. */
239 qemu_irq *pl061_init(uint32_t base, qemu_irq irq, qemu_irq **out)
244 s = (pl061_state *)qemu_mallocz(sizeof(pl061_state));
245 iomemtype = cpu_register_io_memory(0, pl061_readfn,
247 cpu_register_physical_memory(base, 0x00001000, iomemtype);
254 /* ??? Save/restore. */
255 return qemu_allocate_irqs(pl061_set_irq, s, 8);